The Interface Design IP market explodes, growing by 18% in 2019, with $870 million, when CPU IP category grew by 5% at $1,460 million. In fact, Interface IP market is forecasted to sustain high growth rate for the next five years, as calculated by IPnest in the “Interface IP Survey 2015-2019 & Forecast 2020-2024”, to reach $1,800… Read More
Semiconductor Intellectual Property
Arm Rings the Bell in Supercomputing
Late last year I wrote about Arm’s efforts to play a role in servers, in AWS, and particularly Arm-based supercomputing, in the Sandia Astra roadmap and in partnering with NVIDIA who are in the Oak Ridge Summit supercomputer. These steps came, at least for me, with an implicit “Good for them, playing a role on the edges of these challenging… Read More
Siemens Acquires UltraSoC to Drive Design for Silicon Lifecycle Management
As reported recently by Dan Nenni, Siemens has signed an agreement to acquire Cambridge, UK-based UltraSoC Technologies Ltd. We’ve all seen plenty of mergers and acquisitions in EDA. Some transactions perform better than others. The best ones enhance an existing product or service by blending non-overlapping technologies.… Read More
Waking Up to the Requirements of Voice Activity Detection
There is a famous scene in the 1976 movie Taxi Driver when Robert De Niro’s character Travis is pretending to have a conversation looking in the mirror and repeatedly saying “Are you talking to me?”. I think about this scene every time I use a voice active device – Hey, are you talking to me? Yes, I am, but are you listening?
Voice command,… Read More
Tears in the Rain – Arm and China JVs
We always warn clients that even in the best of times, Joint Ventures (JVs) in China always end in tears. And we are far from the best of times right now. There is a major example of this playing out right now with Arm China.
Arm’s China JV is, to put it simply, a bit of a mess. The Board has fired the CEO, but he has refused to leave. And owing… Read More
Staying on the Right Side in Worst Case Conditions – Performance (Part 2)
In this, the second part of a two-part series we delve further into defining worst case, this time focusing specifically on device performance.
In the last blog we talked about the steady increase in power density per unit silicon area and how worst case is definitely getting worse. We discussed how in each new FinFET node the dynamic… Read More
Nobody Ever Lost Their Job for Spending too Much on Hardware Verification, Did They?
A paper was published last month on the Acuerdo Consultancy Services website authored by Joe Convey of Acuerdo and Bryan Dickman of Valytic Consulting. Joe and Bryan spent combined decades in the Semi and EDA World which means they have a great understanding of hardware bugs first hand, absolutely.
Here is a quick summary… Read More
CEO Interview: Deepak Kumar Tala of SmartDV
SMARTDV is one of the biggest small EDA companies in the industry today in regards to products, customers and number of licenses in use, absolutely. They have a portfolio of more than 600 Design & Verification Solutions, everything from Design & Verification IP to Formal Verification IP, Post-Silicon Verification IP… Read More
Talking Sense with Moortec: Staying on the right side in worst case conditions – Power (Part 1)
In this first part of a 2-part blog series, we look at defining worst case conditions, focusing specifically on device power.
With great power, comes great responsibility…
With each new technology node especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal… Read More
Where’s the Value in Next-Gen Cars?
Value chains can be very robust and seemingly unbreakable – until they’re not. One we’ve taken for granted for many years is the chain for electronics systems in cars. The auto OEM, e.g. Toyota, gets electronics module from a Tier-1 supplier such as Denso. They, in turn, build their modules using chips from a semiconductor chip maker… Read More
Should Intel be Split in Half?