ads mdx semiwiki building trust gen 800x100ai
WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1898
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1898
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
    [is_post] => 
)
IP

Semiconductor Intellectual Property

Posted on

Creating Analog PLL IP for TSMC 5nm and 3nm

Creating Analog PLL IP for TSMC 5nm and 3nm
by Tom Simon on 09-01-2020 at 6:00 am
Categories: EDA, IP, Siemens EDA, Silicon Creations

PLL Optimizations

TSMC’s Open Innovation Platform’s main objective is to create and promote partnership for producing chips. This year’s OIP event included a presentation on the joint efforts of Silicon Creations, Mentor, a Siemens business and TSMC to produce essential PLL IP for 5nm and 3nm designs. The relentless push for smaller geometries… Read More

Posted on

Protocol in Depth – USB

Protocol in Depth – USB
by Luigi Filho on 08-30-2020 at 10:00 am
Categories: IP

Protocol in Depth USB

The USB protocol is a very complex protocol, so there is no way i can explain every detail in a post, but i can let much more easy to understand what happens in a bit level.

There isn’t much good material for easy understand about USB, so i made some assumptions for make easier explain everything. In this post i’ll explain… Read More

Posted on

Making Full Memory IP Robust During Design

Making Full Memory IP Robust During Design
by Daniel Payne on 08-28-2020 at 10:00 am
Categories: Events, IP, Synopsys
1 Comment

64Mb SRAM example, memory IP

Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More

Posted on

CEO Interview: Charlie Janac of Arteris IP

CEO Interview: Charlie Janac of Arteris IP
by Daniel Nenni on 08-28-2020 at 6:00 am
Categories: Arteris, Automotive, CEO Interviews, IP

charlie janac


Charlie Janac is president and CEO of Arteris IP where he is responsible for growing and establishing a strong global presence for the company that is pioneering the concept of NoC technology. Charlie’s career spans over 20 years and multiple industries including electronic design automation, semiconductor capital equipment,… Read More

Posted on

A Historical Case for Precision – or How a Gun Made in a Dungeon Changed the World

A Historical Case for Precision – or How a Gun Made in a Dungeon Changed the World
by Lee Vick on 08-26-2020 at 10:00 am
Categories: IP, Moortec

Flintlock Mechanism Wikipedia

We take for granted today the staggering precision of modern technology. Cars, electronics, robots and medical equipment, all come off the factory floor composed of effortlessly interchangeable parts; but this was not always the case. In the late 18th century most things that required any kind of precision were made by hand, … Read More

Posted on

PCI Express in Depth – Physical Layer

PCI Express in Depth – Physical Layer
by Luigi Filho on 08-23-2020 at 10:00 am
Categories: IP

PCI Express in Depth Physical Layer

In the last article, I wrote about the PCIe basic concepts. This article will reach the physical layer of the PCIe standard.

The lowest PCI Express architectural layer is the Physical Layer. This layer is responsible for actually sending and receiving all the data to be sent across the PCI Express link. The Physical Layer interacts… Read More

Posted on

PCI Express in Depth

PCI Express in Depth
by Luigi Filho on 08-23-2020 at 8:00 am
Categories: IP

PCI Express in Depth

This is another post that was requested by a user, and as always i’ll do my best to put in a few articles the basic information that you’ll need to understand how it works at depth level.

PCI Express (or PCIe) is a high-speed serial computer expansion bus designed to replace the older PCI, PCI-X and AGP standards.

The first… Read More

Posted on

ARC Processor Virtual Summit!

ARC Processor Virtual Summit!
by Daniel Nenni on 08-21-2020 at 6:00 am
Categories: Events, IP, Synopsys

ARC Processor Virtual Summit 2020

The ARC Processor has a rich history. Originally named the Argonaut RISC Processor, it was designed for the Nintendo Game Systems in the 1990s. Argonaut Technologies Limited later became ARC International. My first intimate exposure to ARC was in 2009 when Virage Logic acquired ARC. A year later Virage was acquired by Synopsys… Read More

Posted on

Major Hardware Security Initiative Adds Tortuga Logic

Major Hardware Security Initiative Adds Tortuga Logic
by Bernard Murphy on 08-20-2020 at 6:00 am
Categories: IP, Security, Tortuga Logic

cybersecurity 2 min

You can update ..Generally, I’m a fan of letting market forces figure out best solutions to whatever evolving needs we may have, but I’m enough of a realist to accept that’s not a workable answer to every need. Some problems need a top-down fix. However, we can’t expect policymakers or industry consortia to create compliance demands… Read More

Posted on

Interconnect Basics: Wires to Crossbar to NoC

Interconnect Basics: Wires to Crossbar to NoC
by Bernard Murphy on 08-18-2020 at 6:00 am
Categories: Arteris, IP
2 Comments

rats nest min

To many of us, if we ever think about interconnect on an SoC, we may think delay, power consumption, congestion, that sort of thing. All important points from an implementation point of view, but what about the functional and system implications? In the early days, interconnect was very democratic, all wires more or less equal, … Read More