CEVA Dolphin Weninar SemiWiki 800x100 260419 (1)
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Webinar on Protecting Against Side Channel Attacks

Webinar on Protecting Against Side Channel Attacks
by Tom Simon on 10-21-2021 at 10:00 am

Side channel attack protection

SoC design for security has grown and evolved over time to address numerous potential threat sources. Many countermeasures have arisen to deal with ways hackers can gain control of systems through software or hardware design flaws. The results are things like improved random number generators, secure key storage, crypto, and… Read More


Using PUFs for Random Number Generation

Using PUFs for Random Number Generation
by Kalar Rajendiran on 10-19-2021 at 6:00 am

3 API Functions

In our daily lives, few of us if any, would want randomness to play any role. We look for predictability in order to plan our lives. But reality is that random numbers have been playing a role in our lives for a long time. The more conspicuous use cases of random numbers are with key fobs, and nowadays mobile phones. And then there are a … Read More


Chiplet: Are You Ready For Next Semiconductor Revolution?

Chiplet: Are You Ready For Next Semiconductor Revolution?
by Eric Esteve on 10-17-2021 at 6:00 am

D2D IP market forercast 2020 2025

During the 2010-decade, the benefits of Moore’s law began to fall apart. Moore’s law stated transistor density doubled every two years, the cost of compute would shrink by a corresponding 50%. The change in Moore’s law is due to increased in design complexity the evolution of transistor structure from planar devices, to Finfets.… Read More


Podcast EP43: Navigating the Architecture Exploration Jargons and What Do They Mean to a Chip Architect?

Podcast EP43: Navigating the Architecture Exploration Jargons and What Do They Mean to a Chip Architect?
by Daniel Nenni on 10-15-2021 at 10:00 am

Dan is joined by Deepak Shankar, founder of Mirabilis Design. Dan explores the application and impact of architectural exploration on chip and system design.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group… Read More


Webinar – Comparing ARM and RISC-V Cores

Webinar – Comparing ARM and RISC-V Cores
by Daniel Payne on 10-14-2021 at 10:00 am

Mirabilis Webinar, October 21

Operating systems and Instruction Set Architectures (ISA) can have long lifespans, and I’ve been an engineering user of many ISAs since the 1970s. For mobile devices I’ve followed the rise to popularity of the ARM architecture, and then more recently the RISC-V ISA which has successfully made the leap from university… Read More


On-Device Tensilica AI Platform For AI SoCs

On-Device Tensilica AI Platform For AI SoCs
by Kalar Rajendiran on 10-05-2021 at 6:00 am

Varying On Device AI Requirements 1

During his keynote address at the CadenceLIVE 2021 conference, CEO Lip-Bu Tan made some market trend comments. He observed that most of the data nowadays is generated at the edge but only 20% is processed there. He predicted that by 2030, 80% of data is expected to be processed at the edge. And most of this 80% will be processed on edge… Read More


Synopsys’ ARC® DSP IP for Low-Power Embedded Applications

Synopsys’ ARC® DSP IP for Low-Power Embedded Applications
by Kalar Rajendiran on 09-30-2021 at 10:00 am

Key Applications Driving PPA Optimized Signal Processing

On Sep 20th, Synopsys announced an expansion of its DesignWare® ARC® Processor IP portfolio with new 128-bit ARC VPX2 and 256-bit ARC VPX3 DSP Processors targeting low-power embedded SoCs. In 2019, the company had launched a 512-bit ARC VPX5 DSP processor for high-performance signal processing SoCs. Due to the length, format… Read More


System-Level Modeling using your Web Browser

System-Level Modeling using your Web Browser
by Daniel Payne on 09-27-2021 at 10:00 am

VisualSim example

I’ve simulated IC designs at the transistor-level with SPICE, gate-level, RTL with Verilog, and even used cycle-based functional simulators. Sure, they each worked well, but only for the domain and purpose they were designed for. Industry analyst, Gary Smith predicted that the IC world would soon move to system-level… Read More


Securing Applications: A PUFiot Solution for RISC-V-based IoT Devices

Securing Applications: A PUFiot Solution for RISC-V-based IoT Devices
by Kalar Rajendiran on 09-27-2021 at 6:00 am

PUFiot Supporting Secure Applications

In June 2021, eMemory Technology hosted a webinar titled “PUFiot: A PUFrt-based Secure Coprocessor.” You can read a blog leading up to that webinar here. PUFiot is a novel high-security crypto coprocessor. You can access a recording of that entire webinar from eMemory’s Resources page. While the focus of that webinar was to present… Read More


The Journey of DRAM Continues

The Journey of DRAM Continues
by Arabinda Das on 09-26-2021 at 10:00 am

HBM

The field of DRAM is fascinating as it continues to grow and innovate. For the past ten years, I have often read that DRAM is running out of steam because of its difficulty to scale the capacitor, and yet it continues to evolve since invented by Dr. R. Dennard at IBM. In 1966, he introduced the concept of a transistor memory cell consisting… Read More