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Formal-based RISC-V processor verification gets deeper than simulation

Formal-based RISC-V processor verification gets deeper than simulation
by Don Dingee on 05-01-2023 at 10:00 am

End to end formal-based RISC-V processor verification flow for the Codasip L31

The flexibility of RISC-V processor IP allows much freedom to meet specific requirements – but it also opens the potential for many bugs created during the design process. Advanced processor features are especially prone to errors, increasing the difficulty and time needed for thorough verification. Born out of necessity, … Read More


Podcast EP158: The Benefits of a Unified HW/SW Architecture for AI with Quadric’s Nigel Drego

Podcast EP158: The Benefits of a Unified HW/SW Architecture for AI with Quadric’s Nigel Drego
by Daniel Nenni on 04-28-2023 at 10:00 am

Dan is joined by Nigel Drego, the CTO and Co-founder at Quadric. Nigel brings extensive experience in software and hardware design to his role at Quadric. Nigel is an expert in computer architectures, compiler technology, and software frameworks.

Dan explores the unique and unified HW/SW architecture developed by Quadric with… Read More


CEO Interview: Ravi Thummarukudy of Mobiveil

CEO Interview: Ravi Thummarukudy of Mobiveil
by Daniel Nenni on 04-28-2023 at 6:00 am

Ravi Thummarukudy

Mobiveil Marks 11th Anniversary

Ravi Thummarukudy is Mobiveil’s Chief Executive Officer and a founder. He and I recently spent an enjoyable afternoon getting acquainted as I learned more about Mobiveil. It’s an inspiring story of a technology company in the semiconductor space helping customers and prospering.

Eleven-year-old… Read More


Configurable RISC-V core sidesteps cache misses with 128 fetches

Configurable RISC-V core sidesteps cache misses with 128 fetches
by Don Dingee on 04-25-2023 at 6:00 am

Gazzillion misses 2

Modern CPU performance hinges on keeping a processor’s pipeline fed so it executes operations on every tick of the clock, typically using abundant multi-level caching. However, a crop of cache-busting applications is looming, like AI and high-performance computing (HPC) applications running on big data sets. SemidynamicsRead More


Synopsys Accelerates First-Pass Silicon Success for Banias Labs’ Networking SoC

Synopsys Accelerates First-Pass Silicon Success for Banias Labs’ Networking SoC
by Kalar Rajendiran on 04-24-2023 at 8:00 am

Image to Depict Optical SoC

Banias Labs is a semiconductor company that develops infrastructure solutions for next-generation communications. Its target market is the high-performance computing infrastructure market including hyperscale data center, networking, AI, optical module, and Ethernet switch SoCs for emerging high-performance computing… Read More


Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!

Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
by Eric Esteve on 04-21-2023 at 6:00 am

Top5 Royalty 2022 BIG updated

Design IP revenues had achieved $6.67B in 2022, after $5.56B in 2021, or 20.2% growth after 19.4% in 2021 and 16.7% in 2020. IPnest has released the “Design IP Report” in April 2023, ranking IP vendors by category (CPU, DSP, GPU & ISP, Wired Interface, SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless… Read More


Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization

Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization
by Daniel Nenni on 04-12-2023 at 10:00 am

Updated Speaker Slide

Are you developing or thinking about developing your own RISC-V processor? You’re not alone. The use of the RISC-V ISA to develop processors for SoCs is a growing trend. RISC-V offers a lot of flexibility with the ability to customize or create ISA and microarchitectural extensions to differentiate your design no matter your application… Read More


Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet

Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet
by Madhumita Sanyal on 04-10-2023 at 6:00 am

Picture2

The increasing demands for massive amounts of data are driving high-performance computing (HPC) to advance the pace in the High-speed Ethernet world. This in turn, is increasing the levels of complexity when designing networking SoCs like switches, retimers, and pluggable modules. This growth is accelerating the need for … Read More


Interconnect Under the Spotlight as Core Counts Accelerate

Interconnect Under the Spotlight as Core Counts Accelerate
by Bernard Murphy on 04-06-2023 at 6:00 am

Core counts min

In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware delivered improved performance/area/power metrics every year, allowing software to expand in complexity and deliver more capability… Read More


Mapping SysML to Hardware Architecture

Mapping SysML to Hardware Architecture
by Daniel Payne on 04-03-2023 at 10:00 am

SysML to VisualSim, Media App min

The Systems Modeling Language (SysML) is used by systems engineers that want to specify, analyze, design, verify and validate a specific system. SysML started out as an open-source project, and it’s a subset of the Unified Modeling Language (UML). Mirabilis Design has a tool called VisualSim Architect that imports your… Read More