Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Multi-Vt Device Offerings for Advanced Process Nodes

Multi-Vt Device Offerings for Advanced Process Nodes
by Tom Dillinger on 06-26-2020 at 6:00 am

Ion Ioff

Summary
As a result of extensive focus on the development of workfunction metal (WFM) deposition, lithography, and removal, both FinFET and gate-all-around (GAA) devices will offer a wide range of Vt levels for advanced process nodes below 7nm.

Introduction
Cell library and IP designers rely on the availability of nFET and pFET… Read More


Key Semiconductor Conferences go Virtual

Key Semiconductor Conferences go Virtual
by Scotten Jones on 06-24-2020 at 2:00 pm

IEDM 2020 Logo

This last week the 2020 Symposia on VLSI Technology and Circuits (VLSI Conference) was held as a virtual conference for the first time and it was announced today (June 24th) that this year’s IEDM conference will also be held as a virtual conference.

“The IEDM Executive Committee has decided that in the interest of prioritizing the… Read More


Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes

Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes
by Tom Dillinger on 06-23-2020 at 6:00 am

scaled metal resistance

Summary
Design Technology Co-Optimization (DTCO) analysis was pursued for library cell PPA estimates for gate-all-around (GAA) devices and new metallurgy options.  The cell design and process recommendations are a bit surprising.

Introduction
During the “golden years” of silicon technology evolution that applied Dennard… Read More


Seeing is Believing, the Benefits of Delta’s Low-Resolution Vision Chip

Seeing is Believing, the Benefits of Delta’s Low-Resolution Vision Chip
by Mike Gianfagna on 06-22-2020 at 6:00 am

Screen Shot 2020 06 15 at 10.16.13 AM

Presto Engineering recently held a webinar discussing vision chip technology – what a vision chip is, what are the applications and how can you optimize its use.  Samer Ismail, a design engineer at Presto Engineering with deep domain expertise in vision chip technology was the presenter.  Samer takes you on a very informative … Read More


Embedded MRAM for High-Performance Applications

Embedded MRAM for High-Performance Applications
by Tom Dillinger on 06-21-2020 at 10:00 am

embedded memory requirements

Summary
A novel spin-transfer torque magnetoresistive memory (STT-MRAM) IP offering provides an attractive alternative for demanding high-performance embedded applications.

Introduction
There is a strong need for embedded non-volatile memory IP across a wide range of applications, as depicted in the figure below.

The… Read More


DVCon 2020 Virtual Follow-Up Conference!

DVCon 2020 Virtual Follow-Up Conference!
by Daniel Nenni on 06-19-2020 at 6:00 am

DVCon 2020 Logo SemiWiki

As most of you know DVCon 2020 was our first conference to be cut short by the Pandemic. SemiWiki bloggers Bernard Murphy, Mike Gianfagna, and I were there with full schedules but at the last minute it was called off. It really was an eerie feeling, the emptiness of it all.

The rest of our EDA live events followed suit and went virtual … Read More


Fractal CEO Update 2020

Fractal CEO Update 2020
by Daniel Nenni on 06-16-2020 at 10:00 am

Fractal Technologies SemiWiki

Rene Donkers, the company’s Co-founder and CEO, started his EDA career at Sagantec where he became responsible for world wide customer support and operations management. Ten years ago, Rene and a handful of people noticed a need in the design community for a standardized (portable) IP Validation approach to replace internal… Read More


Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Mike Gianfagna on 06-16-2020 at 6:00 am

Screen Shot 2020 06 15 at 6.59.34 PM

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More


Webinar on Methods for Monte Carlo and High Sigma Analysis

Webinar on Methods for Monte Carlo and High Sigma Analysis
by Tom Simon on 06-12-2020 at 6:00 am

Advanced Monte Carlo Methods

There is an old saying popularized by Mark Twain that goes “There are three kinds of lies: lies, damned lies, and statistics.” It turns out that no one can say who originated this saying, yet despite however you might feel about statistics, they play an important role in verifying analog designs. The truth is that there are large numbers… Read More


CEO Interview: Johnny Shen of Alchip

CEO Interview: Johnny Shen of Alchip
by Daniel Nenni on 06-10-2020 at 10:00 am

Alchip IPO Johhny Shen Kinying Kwan 1

Alchip was founded in 2003 by a group of Silicon Valley veterans that followed a similar path of working for semiconductor companies then moving to the EDA/IP/ASIC ecosystem. In fact, I used to play basketball with the Alchip co-founder/chairman during that time and can tell you he is a fierce competitor. Good thing too because … Read More