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As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.
Please take this anonymous 16 question survey to identify critical Design for Manufacturability (DFM) issues facing… Read More
This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More
Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More
Always in motion is the future. ~Yoda
For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More
For the greater good of the semiconductor ecosystem, SemiWiki and Mentor Graphics present SemiWiki Seminars, a free seminar and software demonstration series addressing the latest innovations in IC design. SemiWiki Seminars discuss interesting new challenges and potential solutions aimed at increased circuit density … Read More
3D and 2.5D (silicon interposer) designs create new challenges for EDA. Not all of them are in the most obvious areas. Mentor has an interesting presentation on what is required for verification and testing of these types of designs. Obviously it is somewhat Mentor-centric but in laying out the challenges it is pretty much agnostic.… Read More
Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:
But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More
Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.
To meet these new requirements for performance and power, memory… Read More
In my last corporate EDA job I had customers in Korea that were evaluating a new circuit simulator and getting strange results. When I asked, “Could you send me your test case?” the reply was always, “No, we cannot let any of our IC design data leave the building because of security concerns.”… Read More
Joe Sawicki is the VP and General Manager at Mentor Graphics for the Design-to-Silicon Division where the Calibre product line is developed. We met today in Wilsonville, Oregon to review the challenges in IC design, processing and manufacturing.… Read More
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[_relations:protected] => Array
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[_useReplaceInto:protected] =>
[_newValues:protected] => Array
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)
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[navigation_id] =>
[effective_navigation_id] =>
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[_relations:protected] => Array
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)
[_previousValues:protected] => Array
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)
[_options:protected] => Array
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[_deleted:protected] =>
[_readOnly:protected] =>
[_writePending:protected] =>
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[_errors:protected] => Array
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)
[_whenSaveable:protected] => Array
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[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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[_previousValues:protected] => Array
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[_options:protected] => Array
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[_deleted:protected] =>
[_readOnly:protected] =>
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[_whenSaveable:protected] => Array
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)
[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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[populated:protected] => 1
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