My wife and I have traveled to Switzerland on vacation and marveled at the natural beauty of the mountains, efficient train system, tasty chocolate, and wonderful foods. I only wished that our American dollar bought more in Swiss currency than it did. Recently I discovered a high-tech IC design company called Microdul that designs… Read More
Electronic Design Automation
Addressing the Challenges of Tomorrow’s SoC Design
For the next few days Atrenta is running a series of 30 minute live webinars to discuss the new solutions and approaches that are required to improve the way SoC designs are created and modified.
The webinars are at the following times:
- Jan 17th, 7-7.30am PST (sorry you missed that one)
- January 18th 7.30-8pm PST (and January 19th in
Chip-Package-System workshops
Chips, packages and circuit boards (systems, hence CPS) used to be three separate domains with their own tools that barely interacted at all. If you were lucky, reassigning a pin on a package wouldn’t have to be done manually in all 3 places. But now, from a signal integrity, noise, power point of view these three domains must… Read More
#49 Design Automation Conference Deadlines
Note that there are several DAC deadlines coming up in the next couple of weeks.
The deadline for user track submissions is January 17th (next Tuesday). Submission requires an extended abstract. See here for details.
The deadline for DAC workshops is January 19th (next Thursday). A proposal is required. See here for details.
The… Read More
Needham growth conference
One of the fun things when a company gets big but is still private, like Atrenta, is that you start to get invited to events like the Needham Growth Conference that took place earlier this week in New York. When I ran Compass Design Automation, which at the time was about $55M in revenue, I remember going to a couple of these events. At … Read More
EDAC reports Q3
EDAC (EDA consortium) market statistics service announced the data for Q3 of 2011. Revenue increased 18.1% (versus 2010) to $1543.9 million. Sequentially (versus Q2) revenue increase 7.4%. Annualized, that puts EDA at over $6B for, I belive, the first time ever. Wally Rhines, who is EDAC chair (and CEO of Mentor) commented that… Read More
Advanced Memory Cell Characterization with Calibre xACT 3D
Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.
To meet these new requirements for performance and power, memory… Read More
Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More
Speeding SoC timing closure
As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded.… Read More
Imera Virtual Fabric
Virtual fabric sounds like something that would be good for making the emperor’s new clothes. I talked today to Les Spruiell of Imera to find out what it really is.
Anyone who has worked as either a designer or as an EDA engineer has had the problem of a customer who has a problem but can’t send you the design since it is (a)… Read More


Podcast EP357: How Gonka is Changing the Way AI is Accessed with David Liberman