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EDA

Electronic Design Automation

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Efficient Handling of Timing ECOs

Efficient Handling of Timing ECOs
by Daniel Nenni on 05-29-2013 at 8:00 pm
Categories: EDA

Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancing… Read More

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The Hot Zone: Do Good While Having Fun

The Hot Zone: Do Good While Having Fun
by Paul McLellan on 05-29-2013 at 12:39 pm
Categories: EDA, Events


The big 50th Anniversary party for DAC is on Monday night at the home of Austin City Limits. However, you can do good while enjoying yourself and also get into “The Hot Zone”, an exclusive area within the party in the penthouse Jack and Jim Gallery. The Gallery features 30 original photographs from the godfather of music… Read More

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BDA Takes on FinFET-based Memories with AFS Mega

BDA Takes on FinFET-based Memories with AFS Mega
by Daniel Nenni on 05-29-2013 at 12:00 pm
Categories: EDA

Berkeley Design Automation today announced the first silicon-accurate circuit simulation for mega-scale arrays like memories and CMOS image sensors. If this tool lives up to its claims, it is going to be a big deal for FinFET-based circuits, Memory designers are rightly worried about having the accuracy necessary to include… Read More

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RTL Signoff Theater

RTL Signoff Theater
by Paul McLellan on 05-29-2013 at 11:00 am
Categories: EDA

We have talked for years about RTL signoff, the idea that a design could be finalized at the RTL level and then most of the signoff would take place there. Then the design would be passed to a physical implementation team who would not expect to run into any problems (such as routing congestion, missing the power budget or similar problems).… Read More

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Transistor, Gate and RTL Debug Update at DAC

Transistor, Gate and RTL Debug Update at DAC
by Daniel Payne on 05-29-2013 at 10:53 am
Categories: Concept Engineering, EDA

Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor,… Read More

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The never-ending quest to kill metastability

The never-ending quest to kill metastability
by Don Dingee on 05-28-2013 at 4:00 pm
Categories: Aldec, EDA

The difficulty of an engineering problem can be gauged by two things:
1) The number of attempts to generate a solution.
2) The degree of hyperbole used to describe the effectiveness of the latest solution.

The problem many folks in the EDA industry are after right now is clock domain crossings (CDCs) and the resulting metastability… Read More

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Jasper’s DAC Program

Jasper’s DAC Program
by Paul McLellan on 05-28-2013 at 3:52 pm
Categories: EDA

Jasper’s booth is 2346 where you can see demos of the JasperGold Apps and attend seminars on the experiences of ST and Broadcom, and others:

  • The Broadcom presentation on making formal an integral part of chip design is Tuesday at 10am.
  • The ST presentation on adapting formal methods in ARM subsystems is Monday at 1.30pm and
… Read More
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Barbecue at DAC

Barbecue at DAC
by Paul McLellan on 05-28-2013 at 1:55 pm
Categories: EDA, Events

I already wrote about Franklin Barbecue, by some rankings the best in the whole country. If you want to go there you must be there early. They start serving at 11am and run out of food around 1pm. Closed on Monday.

But there are other barbecue and similar places near the convention center. Since I’m not an Austin native (we’ll… Read More

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Enabling 14nm FinFET Design

Enabling 14nm FinFET Design
by Daniel Payne on 05-28-2013 at 12:54 pm
Categories: EDA, Samsung Foundry, Synopsys

There’s never a dull moment in the foundry race to offer FinFET processes that enable leading-edge SoC design. Today I attended a webinar hosted by Samsung and Synopsys on how to enable 14nm FinFET design. The two speakers were Dr. Kuang-Kuo Lin from Samsung and Dr. Henry Sheng from Synopsys.


Dr. Kuang-Kuo Lin, Samsung


Dr.… Read More

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Calypto AMD Renesas and #50DAC

Calypto AMD Renesas and #50DAC
by Daniel Nenni on 05-28-2013 at 10:00 am
Categories: EDA

This year for DAC, Calypto has assembled an impressive lineup of customer presentation, suite sessions and Designer Tracks. To start with customer presentation, Steve Kommrusch, Fellow Design Engineer from AMD will be giving a talk in the Calypto Suite on AMD’s methodology for low power and will show how AMD was able to get further… Read More