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3D ESD verification: Tackling new challenges in advanced IC design

3D ESD verification: Tackling new challenges in advanced IC design
by Admin on 12-17-2025 at 10:00 am

fig1 3d structures

By Dina Medhat

Three key takeaways

  • 3D ICs require fundamentally new ESD verification strategies. Traditional 2D approaches cannot address the complexity and unique connections in stacked-die architectures.
  • Classifying external and internal IOs is essential for robust and cost-efficient ESD protection. Proper differentiation
Read More

Reimagining Architectural Exploration in the Age of AI

Reimagining Architectural Exploration in the Age of AI
by Bernard Murphy on 12-17-2025 at 6:00 am

Rise and Precision flow

This is not about architecting a full SoC from scratch. You already have a competitive platform, now you want to add some kind of accelerator, maybe video, audio, ML, and need to explore architectural options for how accelerator and software should be partitioned, and to optimize PPA. Now we have AI to help us optimize you’d like … Read More


S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development
by Daniel Nenni on 12-16-2025 at 10:00 am

cover image(1)

MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ high-performance… Read More


A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design

A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design
by Mike Gianfagna on 12-16-2025 at 6:00 am

A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design

Electrical rule checking (ERC) is a standard part of any design flow. There is a hidden problem with the traditional approach, however. As designs grow in complexity, whether full-custom analog, mixed-signal, or advanced-node digital, the limitations of traditional ERC tools are becoming more problematic. This can lead to… Read More


Signal Integrity Verification Using SPICE and IBIS-AMI

Signal Integrity Verification Using SPICE and IBIS-AMI
by Daniel Payne on 12-15-2025 at 10:00 am

IBIS AMI min

High-speed signals enable electronic systems by using memory interfaces, SerDes channels, data center backplanes and connectivity in automobiles.  Challenges arise from signal distortions like inter-symbol interference, channel loss and dispersion effects. Multi-gigabit data transfer rates in High-Bandwidth Memory… Read More


MZ Technologies Launches Advanced Packaging Design Video Series

MZ Technologies Launches Advanced Packaging Design Video Series
by Daniel Nenni on 12-12-2025 at 6:00 am

MZ Technologies Video Series SemiWiki

In a significant move aimed at empowering semiconductor and systems-design engineers, MZ Technologies has announced the launch of a new video series focused on advanced packaging design. This initiative comes at a time when the semiconductor industry is rapidly shifting toward multi-die, 2.5D/3D integration, heterogeneous… Read More


Superhuman AI for Design Verification, Delivered at Scale

Superhuman AI for Design Verification, Delivered at Scale
by Mike Gianfagna on 12-11-2025 at 10:00 am

Superhuman AI for Design Verification, Delivered at Scale

There is a new breed of EDA emerging. Until recently, EDA tools were focused on building better chips, faster and with superior quality of results. Part of that process is verifying and debugging the resultant design. Thanks to ubiquitous AI workloads and multi-chip architectures, the data to be verified and debugged is exploding,… Read More


Radio Frequency Integrated Circuits (RFICs) Generated by AI Based Design Automation

Radio Frequency Integrated Circuits (RFICs) Generated by AI Based Design Automation
by Admin on 12-10-2025 at 10:00 am

Figure1

By Jason Liu, RFIC-GPT Inc.

Radio frequency integrated circuits (RFICs) have become increasingly critical in modern electronic systems, driven by the rapid growth of wireless communication technologies (5G/6G), the Internet of Things (IoT), and advanced radar systems. With the desire for lower power consumption, higher… Read More


Propelling DFT to New Levels of Coverage

Propelling DFT to New Levels of Coverage
by Bernard Murphy on 12-10-2025 at 6:00 am

Increase DFT coverage

Siemens recently released a white paper on a methodology to enhance test coverage for designs with tight DPPM requirements. I confess when I first skimmed the paper, I thought this was another spin on fault simulation for ASIL A-D qualification, but I was corrected and now agree that while there are some conceptual similarities… Read More


AI-Driven DRC Productivity Optimization: Insights from Siemens EDA’s 2025 TSMC OIP Presentation

AI-Driven DRC Productivity Optimization: Insights from Siemens EDA’s 2025 TSMC OIP Presentation
by Daniel Nenni on 12-09-2025 at 10:00 am

AI Driven DRC Productivity Optimization Siemens AMD TSMC

 

In the rapidly evolving semiconductor industry, Design Rule Checking (DRC) remains a critical bottleneck in chip design workflows. Siemens EDA’s presentation at the 2025 TSMC Open Innovation Platform Forum, titled “AI-Driven DRC Productivity Optimization,” showcases how artificial intelligence … Read More