Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancing process technology. Since ECO handling is mostly a manual process. Hence it is time consuming and error-prone. When most chip design cycles are a year or less, if timing closure takes up to two months, it becomes an expensive process. The trend is that ECO handling is expected to grow more complex with each new process node, and hence become more expensive.
Achieving design closure in the world of SoC design is becoming more and more difficult with each new process node. With increasing design densities/complexities, the interaction of process parameters on design and the inability of design tools to efficiently handle a large number of multi-mode, multi-corner timing scenarios exacerbate the issue.
While it is natural to expect ECO scripts generated using a sign-off STA to be accurate, it is not true for most SoC designs today. Why? Delays are layout dependent and STA tools are not physically-aware. First and foremost, the ECO scripts generated by such non-physically aware tools are not accurate. Second, the scripts are actually implemented using a P&R tool. The inherent lack of correlation between the timing engines within the STA and P&R tools lead to inaccurate estimations of the size and locations for buffers added to the design. In addition, the common challenges faced by designers are:
- Handling multi-mode, multi-corner (MCMM) is practically impossible when manually generating ECOs. Without MCMM, non-linear process variation effects lead to several thousand hold violations.
- STA being not physically-aware, leads to inaccurate ECO fixes and often over use of buffers, thereby increasing chip power.
- Designers are forced to run several long and time-consuming iterations through P&R tools since, a) P&R tools can handle few scenarios only at a time, and b) STA-generated ECO scripts are poor predictors of timing convergence.
- Sometimes, driven by time to market pressures, it is not uncommon to tape-out a chip for a lower than intended performance target.Current ECO Methodologies
In the traditional timing ECO methodology (Figure1), designers start the ECO process after completing routing. Three common approaches currently used to address timing ECOs and the challenges they present are:
Script-based ECO handling is a common approach. Based on violation report or partial STA graph, and using easy ways to fix those violations, designers develop and apply an ECO script. Being mostly manual in nature, it is practically impossible to handle multi-mode, multi-corner (MCMM) issues in one shot. In addition, neither the STA tool nor the designers are layout-aware, leading to both timing and layout correlation issues, and hence poor results.
Another method is to use an optimizer on top of the STA tool. Since the STA tool is not physically-aware, layout correlation issues lead to poor results.
The third approach is to build an optimizer on top of place and route software. The difference between the built-in timing engine and the sign-off STA engine creates timing correlation issues, leading to over compensation and too many buffers, thereby increasing routing congestion and power. In addition, P&R tools are inherently limited to handling only a few scenarios at a time. This leads to extra iterations and longer time to closure.
During the post-route optimization phase, designers typically try to reduce the number of violations to within a few hundred such that they can be addressed manually. Since P&R tools can handle only few scenarios at a time, the number and duration per iteration typically increases, resulting in longer time to a) reduce violation count and b) time to closure.
From the above discussion it is clear that in order to effectively address timing ECOs and closure, the required solution must combine the capabilities of static timing analysis and physical design to effectively and efficiently handle ECO optimization. In essence, such a solution must be:
- Placement and most importantly routing-aware
- Highly correlated with respect to layout and timing
- Able to handle a large number of MCMM scenariosCorrelation and routing awareness would ensure a) accurate buffer estimation, b) their legalized placement and c) most efficient handling of transition timing violations. The ability to handle large number of MCMM scenarios would transform into greater accuracy, and significant reduction in the number of ECO iterations.
TimingExplorer™, a unique, placement and routing-aware timing closure solution for all MCMM timing scenarios provided the capabilities we were looking for.
TimingExplorer provided us the following benefits:
- Saved 2-4 iterations and 1-2 weeks at the post-route optimization stage. This equated to 50% savings in the post-route optimization phase.
- Saved 2-3 iterations and 0.5-1 day per iteration (total 1-2 weeks) in ECO phase. This was a 60% to 70% reduction in the duration of timing ECO phase.
- Most effective and highest efficiency in fixing violations
- Saved area by using 25-30% fewer buffers than a P&R tool based methodology After successfully taping-out dozens of designs, this tool is now part of our standard design closure flow.
ECOs are the biggest reason why design closure is increasingly complex and time consuming. Effectively and efficiently addressing ECOs call for a product that is architected to be placement and routing-aware, and is capable of handling any number of MCMM sign-off scenarios.
About the Author
Timothy Yinghas been working as an ASIC design engineer for 12 years. In his current position as Staff Design Engineer at Marvell’s Storage Group, he is focused on timing ECO closure using Static Timing Analysis. He primarily works on 28nm designs with complex clock structures, multi-voltage domains and hierarchy. Timothy holds a bachelor’s degree in Computer Science from Fudan University in Shanghai, China, and a master’s degree in Electrical Engineering from San Jose State University in California.