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Electronic Design Automation
Back in the microprocessor stone age, government procurement agencies fell in love with the idea of radiation hardened parts that might survive catastrophic events. In those days, before rad-hard versions of PowerPC and SPARC arrived, there were few choices for processors in defense and space programs.
One of the first rad-hard… Read More
Years ago I thought that chip design companies would embrace the latest technology and be eager to adopt new tools. What I learned was that the people implementing and managing design projects were taking a lot of risks with almost every aspect of their projects. What they most wanted is to minimize risk from the design process – especially… Read More
Software-centric Emulation environment takes the forefront in modern SoC verification. As more and more devices are IoT enabled, the SoCs have to make special provisions to factor many things including communication, power usage, and network switching, and so on. Also, the demand for an SoC (specifically for smartphone which… Read More
At the Cadence front-end summit last week, Jay Roy presented the Cadence Joules solution for RTL (and gate-level) power estimation. Jay is ex-Apache, so knows his way around RTL power estimation which should make Joules a product to watch. Joules connects very natively to Palladium for power characterization for realistic software… Read More
So far in my blog series on low power we’ve looked broadly at what’s changing in the low power verification landscape and focused on a new methodology developed by Mentor Graphics and ARM called successive refinement, which is now included in the UPF standard. Power management techniques create their own brand of clock domain crossing… Read More
I was at the Cadence front-end summit this week; good conference with lots of interesting information. I’ll start with a panel on optimizing power for wearables. Panelists were Anthony Hill from TI, Fred Jen from Qualcomm, Leah Clark from Broadcom and Jay Roy from Cadence. Panels are generally most entertaining when the panelists… Read More
In a balancing global economy, it’s a common phenomenon that at certain times a few sectors or segments within the sectors grow much faster compared to others. And a few companies within the growing sectors lead those sectors. Both the growing sectors and the leading companies in those sectors become the centers of attraction. … Read More
Designing Analog IP is often referred to as a “black art”, something that only highly experienced craftsmen can produce using transistor-level techniques that aren’t shared outside of their closely held group of trusted co-workers. I’d like to suggest that Analog IP can be designed and optimized … Read More
It often seems that semiconductor industry coverage focuses on large digital markets like microprocessors or high frequency analog designs for RF applications. Yes, these are large markets, but power transistors like IBGT and VFETS make up a large and crucial sector. Not only do they make their way into discretes, but they are… Read More
On my first trip to Austria for EDA business I traveled by car from Germany, and I couldn’t wait to see how fast we would travel on the fabled Autobahn. Oddly enough it was summertime and the Autobahn was filled with vacationing families driving cars with shiny, aluminum campers in tow, so our car only traveled about 60 mph, nothing… Read More
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A Century of Miracles: From the FET’s Inception to the Horizons Ahead