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IEEE S3S Rump Session: “What Does IoT Mean for Si Technology?”

IEEE S3S Rump Session: “What Does IoT Mean for Si Technology?”
by khaki on 09-20-2015 at 12:00 pm

For the second year in the row, Gartner’s Emerging Technologies Hype Cycle puts Internet of Things (IoT) at the Peak of Inflated Expectations. Not only many online forums are inflated with debates on IoT-related topics, but more importantly virtually all semiconductor companies made announcement pertaining their plans to address this potentially massive market. With the internet of people reaching a plateau, IoT is considered by many as a new wave for the continued growth of the semiconductor industry.

However, apart from vague discussions related to the system cost or long battery-life requirements, little is discussed on the implications of IoT on wafer manufacturing and chip design. The fact that legacy CMOS technologies in fully amortized fabs are advertised as the solution to IoT market to lower the leakage current at the same time that leading edge technologies, mainly 28nm, are being tweaked to lower the cost and active power, is a testimony to the existence of a wide range of opinion regarding IoT requirement. This is in part due to the extremely wide range of complexity that one can imagine for IoT: from a simple egg-counter in the fridge to a system that understands human emotions.

A smartphone plus its user (even a toddler) can be viewed as a smart IoT node where the user provides a very wide range of computing capability. However, this smart computing power is beyond the capability of many classical IoT nodes being discussed today. The ultimate application of IoT can be unlocked once such level of smartness is implemented either on the server side or better yet at each node.

At the 2015 edition ofIEEE S3S Conference, we are fortunate to have a diverse panel of experts to cover “What does IoT mean for Si technology” at the Rump Session. The open atmosphere of the session and the participation of an audience that drives the semiconductor technology in R&D, manufacturing, and design as well as academia provide a unique opportunity for debate. I am chairing this year’s panel session and the panelists are:

  • Christophe Chevallier, Ambiq Micro
  • Stanley S.C. Song, Qualcomm Technologies Inc.
  • Ali Niknejad, University of California, Berkeley
  • Norikatsu Takaura, Hitachi

The conference is held Oct. 5-8, 2015 at The DoubleTree by Hilton Sonoma Wine Country. The Rump Session will be held in the evening of Wednesday, Oct. 7th after the conference cook-out. I hope I see many of you at the conference, but if you cannot make it, I am soliciting questions for the panelists. Please feel free to drop me an email or post your questions as a comment.

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