Banner Electrical Verification The invisible bottleneck in IC design updated 1
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4327
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4327
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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Process Development, CAD and Circuit Design

Process Development, CAD and Circuit Design
by Daniel Payne on 04-29-2016 at 7:00 am
Categories: EDA, Primarius

Working at Intel as a circuit designer I clearly remember how there were three distinct groups: Process Development, CAD and Circuit Design. Each of the groups sat in a different part of the building in Aloha Oregon, we had different job titles, different degrees, spoke with different acronyms and yet we all had to work together … Read More

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Webinar alert – VHDL guru says its time to move up

Webinar alert – VHDL guru says its time to move up
by Don Dingee on 04-28-2016 at 4:00 pm
Categories: Aldec, EDA

Many years ago when I worked for Ed Staiano at Motorola, I learned never to use the word “comfortable” in a career context. I’m comfortable being with family and friends. This new high-back chair I sit in at my new faux-cocobolo desk (slightly distressed chalk-painted wood and industrial piping, awesome) is comfortable,… Read More

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Software-Driven Verification Drives Tight Links between Emulation and Prototyping

Software-Driven Verification Drives Tight Links between Emulation and Prototyping
by Bernard Murphy on 04-28-2016 at 12:00 pm
Categories: Cadence, EDA, Prototyping

I’ve mentioned many times what has become a very common theme in SoC and system verification – it has to be driven by the software because any concept of exhaustively verifying “everything” is neither feasible nor meaningful. Emulation has become a critical component of this flow in validating and regressing… Read More

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Bringing Formal Verification into Mainstream

Bringing Formal Verification into Mainstream
by Pawan Fangaria on 04-28-2016 at 7:00 am
Categories: EDA, Synopsys

Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More

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Tcl scripts and managing messages in ASIC & FPGA debug

Tcl scripts and managing messages in ASIC & FPGA debug
by Don Dingee on 04-27-2016 at 4:00 pm
Categories: Blue Pearl Software, EDA, FPGA

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects… Read More

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Metric-Driven Verification for System Signoff

Metric-Driven Verification for System Signoff
by Bernard Murphy on 04-27-2016 at 12:00 pm
Categories: Cadence, EDA

Everyone knows that verification is hard and is consuming an increasing percentage of verification time and effort. And everyone should know that system-level verification (SoC plus at least some software and maybe models for other components on a board) is even harder—which is why you see hand-wringing over how incompletely… Read More

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SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar

SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar
by Bernard Murphy on 04-26-2016 at 12:00 pm
Categories: EDA, Synopsys, Xilinx

Fed up with ECOing your way out of test problems? You might want to register for this webinar.When you’re building monster SoC FPGAs, you have all the same problems you have with any other SoC. That includes getting to very high test coverage as quickly as you can with a design targeted to the most advanced processes. We’re not just … Read More

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Enterprise Design Management Engineered for SoCs

Enterprise Design Management Engineered for SoCs
by Don Dingee on 04-22-2016 at 4:00 pm
Categories: Cliosoft, EDA

In my initial look at ClioSoft’s design management system created from the ground up for the semiconductor industry, I made the opening case for managing and reusing IP across an ASIC design organization. Let’s for a moment say we agree on the need for an enterprise software package to do design management… Read More

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Static Timing Analysis Keeps Pace with FinFET

Static Timing Analysis Keeps Pace with FinFET
by Daniel Payne on 04-22-2016 at 12:00 pm
Categories: EDA, FinFET, Synopsys

At SemiWiki we’ve been blogging for several years now on the semiconductor design challenges of FinFET technology and how it requires new software approaches to help chip designers answer fundamental questions about timing, power, area and design closure. When you mention the phrase Static Timing Analysis (STA) probably… Read More

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Webinar: How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology

Webinar: How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology
by Daniel Nenni on 04-22-2016 at 7:00 am
Categories: Arm, EDA, FD-SOI, Foundries, GlobalFoundries, IP

Who’s doesn’t like a good webinar? I certainly do as it is one of the most time efficient ways to interact with the fabless semiconductor ecosystem, absolutely. Especially when it addresses two of the top trending topics on SemiWiki and they are ARM and FD-SOI. Here is a quick summary of what you will learn:

GLOBALFOUNDRIES… Read More