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New Transistor Sizing Company at #53DAC

New Transistor Sizing Company at #53DAC
by Daniel Payne on 07-18-2016 at 12:00 pm

I first met Herve Guegan at Mentor Graphics back in the late 90’s when he managed a group of developers for the SPICE circuit simulator called Eldo in Grenoble, France. We’ve kept in touch over the years and he asked to meet me at DAC in Austin this year, so I caught up with him to get an update on his latest start-up company called Intento Design.

Q: What problem are you helping engineers to solve?

Instead of doing manual transistor-sizing, we are offering an automated approach to transistor sizing that is simulation based.

Q: How would a circuit designer use this approach?

The circuit design adds circuit intentions to their schematic and then validates the intentions. They use Virtuoso for schematic capture and then add circuit intents like vias voltages, currents, etc. Engineers can even add devices constraints on certain transistors like make the current 1/2 the value of an adjacent transistor, or match these two transistors.

Q: What happens next, after you specify the intentions?

Next, the circuit design would load their circuit, choose a technology file, specify constraints, review the intents, choose their circuit simulator (Spectre, HSPICE, etc.), and run the simulations to optimize device sizes.

Q: How long does device sizing take to run?

For a typical OpAmp circuit the CPU time is about 6-7 minutes to perform device sizing, where our tool finds a global solution to meet all of your design intents. The user can view any of the possible solutions produced and pick the one that they prefer. Here’s the results of running our tool on an amplifier circuit where you can see the target specifications, what Intento predicted the performance to be, and the actual simulated results:

Q: How is your device sizing different from other approaches offered in the past?

A: With our new approach we find a solution with much fewer circuit simulations, typically only hundreds of simulations instead of requiring thousands of simulations.

Q: Are their techniques that a user can try that will reduce the run times?

Yes, the circuit designer can specify smaller W/L bounds in order to reduce the number of simulations required.

Q: What process technologies does your circuit sizing tool support?

It’s really technology independent, so you could be designing with CMOS, FD-SOI or FinFET processes.

Q: Where would you use this automated circuit sizing tool?

You could optimize an existing library of cells to get better performance or smaller layout size, or event migrate a cell from one technology to another one, accurately.

Q: How can a company evaluate your technology?

We encourage interested companies to start an evaluation of our ID-XPLORE tool, or we can do an evaluation using their existing libraries to do a migration.

Q: Where should people go to find out more about Intento Design?

Please visit our web site at www.intento-design.com.

There’s a new start-up in the circuit sizing segment and they’ve integrated into the popular Cadence Virtuoso design environment their ID-XPLORE tool, using your favorite circuit simulator and providing both graphical and numerical feedback on optimized results, running in much less time than conventional simulation-based approaches. Transistor-level design engineers should be interested in these capabilities for optimizing existing cells or migrating cell libraries to new technologies.

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