In every chip, power is a progressive problem to be solved. Designers have long had to rely on a combination of experience and knowledge to tackle this dilemma, typically having to wait until after silicon availability to perform power analysis with realistic software workloads. However, this is too late in the game, as it becomes… Read More
Electronic Design Automation
Instrumenting Post-Silicon Validation. Innovation in Verification
Instrumenting post-silicon validation is not a new idea but here’s a twist. Using (pre-silicon) emulation to choose debug observation structures to instrument in-silicon. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research… Read More
EDA in the Cloud – Now More Than Ever
A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More
Ansys Multiphysics Platform
Background
Traditionally, the interface between chip designers and system power, packaging, reliability, and mechanical engineering teams was a relatively straightforward exchange of specifications. Chip designers developed preliminary power dissipation estimates, often based on a simplifying power/mm**2 value. … Read More
A Custom Layout Environment for SOC Design Closure
Throughout the process of physical design and verification there are many groups working on the design. Most often these groups are working independently or in parallel but separately, using their own specialized tools, such as P&R, DRC, custom layout, DFM, etc. At the end of the process there is an inevitable requirement… Read More
EDA Flows for 3D Die Integration
Background
The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures. The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More
Cadence Tensilica FloatingPoint DSPs
Being engrossed in the digital information world, it is easy to forget that the real world is comprised of mostly analog signals and data. Digital Signal Processors (DSP) take digitized forms of these worldly signals and manipulate them mathematically. Although floating-point is a more relevant and accurate way of representing… Read More
Fully Modeling the Semiconductor Manufacturing Process
A lot of folks in the semiconductor business are familiar with Dassault Systèmes because of their product life cycle management (PLM) products for IC design. They are, of course well known in other industries as well for their 3D modeling and simulation software. Over the years they have added capabilities and intelligence to … Read More
StarFive Surpasses Development Goal with the Prodigy Rapid Prototyping System from S2C
Faced with the challenge of developing a high-performance hardware platform with critical software components, what choices do companies have in rapidly moving their development forward with modest budgets and resources?
That was the challenge faced by StarFive Technology, a leading IP and semiconductor SoC platform solution… Read More
Obtaining Early Analog Block Area Estimates
I’ve written before about Pulsic’s Animate Preview software, which is extremely helpful in completing placement in analog blocks so that they are ready for routing. Analog design automation has always been a tough proposition, but Animate Preview looks like a promising tool, with practical benefits. Obtaining DRC clean placement… Read More


Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools