You may know that up until now NAND flash has been a planar technology. But just as with SoC processes where we have had to go vertical to FinFETs, NAND flash has reached the limitations of scaling in the 20nm nodes and is also going vertical. It is not just a lithography issue but there are also reliability and voltage scaling issues.… Read More
Author: Paul McLellan
Silvaco Swallows Invarian
Yesterday, Silvaco announced that it has acquired Invarian Inc. Details of the transaction were not disclosed.
Who is Invarian? They are a recognized leader in block-level to full-chip sign-off analysis for complex, high-performance ICs. Their unique methodology utilizes a parallel architecture and concurrent power-voltage-thermal… Read More
SystemC Co-Simulation of NoCs and IP Blocks
Verification in general suffers from a couple of fundamental problems. Availability of models and performance of different levels of representation.
The first problem, availability of models, is that you would like to start verification as soon as possible but all the representations are not ready early enough. Obviously … Read More
SEMI: All This and Breakfast Too
Are you interested in any of these?
- Internet of Things
- Trends and Forecast for Fabs
- Inflections Points
- Semiconductor CAPEX
- Cost Effective Scaling
- Prospects for 450mm
- Future of EUV
- Mobile Machine Learning
- Robotics/Drones
- Cybersecurity
- Used Equipment Markets
- World Fab Databases
- Free breakfast
No? Then I think you got the wrong… Read More
Exploring IP You Didn’t Design Yourself
Starvision Pro from Concept Engineering is a bit like one of those Leatherman multi-tools, it has a huge number of different functions, some of them fairly specialized but nonetheless incredibly useful. Many of these functions are unique to Starvision Pro, with nothing else like it on the market. Some new videos, produced by EDA… Read More
FD-SOI Foundry
At the end of last month during ISSCC there was a forum organized by the SOI Consortium. It took place in San Francisco at the Palace Hotel (which, if you have never been there, is famous for converting its old entryway for carriages into an amazing dining room, and for a bar with a huge painting by Maxfield Parrish of the Pied Piper valued… Read More
RF on SOI at GF
Unless you have been living under a rock for the last decade, you can’t help but notice the increased importance of RF: bluetooth, WiFi, 3G, LTE, NFC, RFID and more. There is a lot of digital design associated with these standards, especially the highest bandwidth ones, but they also all contain a radio, often called a modem.… Read More
Getting a Grip on the Internet of Things
QuickLogic’s CTO Tim Saxe gave a keynote Getting a Grip on the Internet of Things at the IoT Summit last week.
He started by relating how things have changed over the last 3 years when he talks to customers.
- Three years ago it was sensor hubs in smartphones and the power budget was 3mW (so one day between re-charging, something
Innovus: Cadence’s Next Generation Implementation System
Yesterday was the first day of CDNLive. There were three keynotes. The first was by Lip-Bu Tan, Cadence’s CEO (and the Chairman of Walden International that he will be the first to remind you). The most interesting tidbit was that Cadence now has over 1000 people working on IP and that it represents 11% of their revenue. Then… Read More
2015, the Year of the Sheep…And the 16nm FPGA
If you live in California anyway, with its large Asian population, you can’t have helped noticing that it was the Lunar New Year a couple of weeks ago, the start of the year of the sheep. A couple of days after the New Year, Xilinx announced their new families of what they now call FPGAs, 3D ICs and MPSoCs. But which the rest of us … Read More
Rethinking Multipatterning for 2nm Node