Cliosoft Webinar: What’s Needed for Next Generation IP-Based Digital Design

Cliosoft Webinar: What’s Needed for Next Generation IP-Based Digital Design
by Mike Gianfagna on 11-04-2021 at 10:00 am

Cliosoft Webinar Whats Needed for Next Generation IP Based Digital Design

There’s plenty of talk about requirements for IP data management. The fundamental methods to prevent chaos, waste or worse are popular topics. I’ve covered webinars from Cliosoft on the topic on SemiWiki. But what about the future? What’s really needed to set up a path that scales, addressing the challenges of today and the new … Read More


Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum

Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum
by Mike Gianfagna on 11-03-2021 at 10:00 am

Alchip Reveals How to Extend Moores Law at TSMC OIP Ecosystem Forum

The TSMC Open Innovation Platform (OIP) event brings together a wide array of companies reporting cutting edge work that are part of TSMC’s rather substantial ecosystem. The event covers everything from high-performance computing to mobile, automotive, IoT, RF and 3D IC design. Of particular interest for this post is a presentation… Read More


Latest Updates to Altair Accelerator, the Industry’s Fastest Enterprise Job Scheduler

Latest Updates to Altair Accelerator, the Industry’s Fastest Enterprise Job Scheduler
by Mike Gianfagna on 11-01-2021 at 10:00 am

Latest Updates to Altair Accelerator the Industrys Fastest Enterprise Job Scheduler

Altair is a broad-based company that delivers critical enabling technology across many disciplines that will be familiar to SemiWiki readers. According to its website, Altair delivers open-architecture solutions for data analytics & AI, computer-aided engineering, and high-performance computing (HPC). You can learn… Read More


Webinar: A Practical Approach to FinFET Layout Automation That Really Works

Webinar: A Practical Approach to FinFET Layout Automation That Really Works
by Mike Gianfagna on 10-27-2021 at 10:00 am

Webina A Practical Approach to FinFET Layout Automation That Really Works

There are certain tasks that have been the holy grail of EDA for some time. A real silicon compiler – high level language as input and an optimal, correct layout as output is one. Fully automated analog design – objectives as input, optimal circuit as output is another. With the increased layout times, due to the ever-increasing design… Read More


Samtec, Otava and Avnet Team Up to Tame 5G Deployment Hurdles

Samtec, Otava and Avnet Team Up to Tame 5G Deployment Hurdles
by Mike Gianfagna on 10-20-2021 at 10:00 am

Samtec Otava and Avnet Team Up to Tame 5G Deployment Hurdles

Everyone is talking about 5G deployment. The promises and the hype are finally turning into reality and products. While excitement is appropriate, victory is not yet in hand. There are still technical hurdles to conquer before the full potential of 5G is realized. In this post, I’ll explore one such challenge – the reliable use … Read More


Take the Achronix Speedster7t FPGA for a Test Drive in the Lab

Take the Achronix Speedster7t FPGA for a Test Drive in the Lab
by Mike Gianfagna on 10-19-2021 at 10:00 am

Take the Achronix Speedster7t FPGA for a Test Drive in the Lab

Achronix is known for its high-performance FPGA solutions. In this post, I’ll explore the Speedster7T FPGA. This FPGA family is optimized for high-bandwidth workloads and eliminates performance bottlenecks with an innovative architecture. Built on TSMC’s 7nm FinFET process, the family delivers ASIC-level performance … Read More


Webinar – SoC Planning for a Modern, Component-Based Approach

Webinar – SoC Planning for a Modern, Component-Based Approach
by Mike Gianfagna on 10-13-2021 at 10:00 am

Webinar – SoC Planning for a Modern Component Based Approach

We all know that project planning and tracking are critical for any complex undertaking, especially a complex SoC design project. We also know that IP management is critical for these same kinds of projects – there is lots of IP from many sources being integrated in any SoC these days. If you don’t keep track of what you’re using and… Read More


ESD Alliance Reports Double-Digit Growth – The Hits Just Keep Coming

ESD Alliance Reports Double-Digit Growth – The Hits Just Keep Coming
by Mike Gianfagna on 10-12-2021 at 6:00 am

ESD Alliance Reports Double Digit Growth – The Hits Just Keep Coming

The latest Electronic Design Market Data report was just published. The headline announces continued substantial growth for the sector: Electronic System Design Industry Logs Double-Digit Q2 2021 Year-Over-Year Revenue Growth, ESD Alliance Reports. While not quite the record-breaking growth reported last quarter, the… Read More


Webinar: PICMG COM-HPC® – New Open Standard for High Performance Compute Modules

Webinar: PICMG COM-HPC® – New Open Standard for High Performance Compute Modules
by Mike Gianfagna on 09-22-2021 at 10:00 am

Webinar PICMG COM HPC® New Open Standard for High Performance Compute Modules

The subject of this webinar is focused on the new COM-HPC standard from PICMG, a nonprofit consortium of companies and organizations that collaboratively develop open standards for high performance telecommunications, military, industrial, and general-purpose embedded computing applications. A computer-on-module … Read More


Build a Sophisticated Edge Processing ASIC FAST and EASY with Sondrel

Build a Sophisticated Edge Processing ASIC FAST and EASY with Sondrel
by Mike Gianfagna on 09-16-2021 at 6:00 am

Build a Sophisticated Edge Processing ASIC FAST and EASY with Sondrel

Building a custom chip for edge computing applications can be quite daunting. For starters, there is very little power available at the edge, so energy efficiency will be top of mind. The whole point of edge processing is to off-load the time-consuming and costly process of sending data to the cloud, so substantial processing capability… Read More