Alphawave IP is a new member of the SemiWiki community. You can learn about the company and their CEO, Tony Pialis in this interview by Dan Nenni. Design & Reuse did a virtual IP-SOC Conference recently and Tony presented. The D&R event had a very strong lineup of presenters. They supplemented the prepared video presentations… Read More
Author: Mike Gianfagna
Alphawave IP is Enabling 224Gbps Serial Links with DSP
Altair Expands Its Technology Footprint with I/O Profiling from Ellexus
Altair is a broad-based technology company with an ambitious vision. As stated on their website: Our comprehensive, open-architecture solutions for data analytics, computer-aided engineering, and high-performance computing (HPC), enable design and optimization for high performance, innovative, and sustainable products… Read More
The Practitioners View of DAC – Design, IP and Embedded
Next year will mark the 58th year for the Design Automation Conference. It’s hard to wrap your head around the fact this event dates back to 1964, when rock ‘n roll was new, cars were big and computers were even bigger. In its early days, the event was called the Design Automation Workshop. Pictured above is the cover of the very first… Read More
Chip Startups are Succeeding with Silicon Catalyst and Partners Like Arm
Earlier this year I wrote about Silicon Catalyst and a potent new addition to their In-Kind and Strategic Partner Programs, Arm. Fast-forward to today and there are real results to report. As I mentioned in the prior post, Silicon Catalyst provides a unique incubator environment which includes deeply discounted technology … Read More
Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
The industry recently concluded a series of technology events for the all the major foundries. Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More
PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers
A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™. The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum… Read More
Cadence is Making Floorplanning Easier by Changing the Rules
SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run… Read More
Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP
Menta is a unique embedded FPGA (eFPGA) company. Their eFPGA IP is based completely on standard cells provided by the foundry, the customer or a third party – no custom cells or custom cell characterization is needed. They also don’t require any specific library, process step or metal stack. All this makes Menta’s eFPGA IP easy to… Read More
Silicon Catalyst Hosts Semiconductor Industry Forum – A View to the Future … it’s about what’s next®
Silicon Catalyst Hosts Semiconductor Industry Forum – A View to the Future … it’s about what’s next®
Silicon Catalyst has been hosting semiconductor forums since 2018. At these events, a group of industry leaders gathers to discuss trends in the semiconductor industry and what the future may hold as a result. I recently had an opportunity to speak with Pete Rodriguez, CEO at Silicon Catalyst. Pete explained that these forums … Read More
Achieving 112Gbps PAM4 Channels with Achronix FPGAs and Samtec Interconnect
They say that getting there is half the fun. On December 1, Achronix and Samtec will present a webinar on this topic in the context of high-performance front panel to midplane and midplane to backplane channel design. Technology, materials and system design will all be discussed with a focus on achieving 112Gbps PAM4 channels with… Read More
Intel High NA Adoption