Author: Don Dingee

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FPGA tools for more predictive needs in critical

FPGA tools for more predictive needs in critical
by Don Dingee on 02-29-2016 at 4:00 pm
Categories: Blue Pearl Software, EDA, FPGA

“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when?… Read More

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Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA, Prototyping

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping.… Read More

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Mentor ARM subscription signals ecosystem shift

Mentor ARM subscription signals ecosystem shift
by Don Dingee on 02-25-2016 at 4:00 pm
Categories: Arm, EDA, IoT, IP, Siemens EDA

Since creating the landmark “all-you-can-eat” license with Samsung in 2002, ARM has inked several subscription deals with chipmakers and EDA firms. The latest ARM subscriber license deal just announced is for Mentor Graphics. What makes their strategy unique?… Read More

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tinyAVR in 8 and 14 pin SOIC now self-programming

tinyAVR in 8 and 14 pin SOIC now self-programming
by Don Dingee on 02-24-2016 at 4:00 pm
Categories: Foundries

At this week’s Embedded World 2016, Atmel is heading back to 8-bit old school with their news, straight to the low pin count end of their MCU portfolio with a significant upgrade to the tinyAVR family.

According to Atmel’s briefing package, development of the ATtiny102 and ATtiny104 has been in progress for some time.… Read More

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S2C opens up FPGA prototyping for PCIe fabrics

S2C opens up FPGA prototyping for PCIe fabrics
by Don Dingee on 02-23-2016 at 4:00 pm
Categories: EDA, FPGA, S2C EDA

Reconfigurable computing began with FPGA cards dropped into expansion slots in workstations. FPGA-based prototyping vendors tended away from that model as interconnect speeds rose and cabling complexity between modules increased. Much faster PCIe interfacing and bigger FPGAs mean revisiting the concept.… Read More

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SoC power management a study in transition latency

SoC power management a study in transition latency
by Don Dingee on 02-22-2016 at 4:00 pm
Categories: IP, Sonics

Apple’s recent bout with ‘Batterygate’ highlighted just how important dynamic power management can be. Our last Sonics update looked at using their NoC to manage power islands; this time, we look at their research progress on architectural measures for power management.… Read More

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New CEVA X baseband architecture takes on multi-RAT

New CEVA X baseband architecture takes on multi-RAT
by Don Dingee on 02-18-2016 at 4:00 pm
Categories: Ceva, IP, Mobile

What we think of as a “baseband processor” for cellular networks is often comprised of multiple cores. Anecdotes suggest to handle the different signal processing requirements for 2G, 3G, and 4G networks, some SoC designs use three different DSPs plus a control processor such as an ARM core. That’s nuts. What is the point of having… Read More

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Reconfigurable redefined with embedded FPGA core IP

Reconfigurable redefined with embedded FPGA core IP
by Don Dingee on 02-12-2016 at 7:00 am
Categories: eFPGA, Flex Logix, FPGA, IP

On November 1, 1985, before anyone had heard the phrase field programmable gate array, Xilinx introduced what they called a “new class of ASIC” – the XC2064, with a whopping 1200 gates. Reconfigurable computing was born and thrived around the RAM-based FPGA, whose logic and input/output pins could be architected into a variety… Read More

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Fastest SoC time-to-success: emulators, or FPGA-based prototypes?

Fastest SoC time-to-success: emulators, or FPGA-based prototypes?
by Don Dingee on 02-11-2016 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

Hardware emulators and FPGA-based prototyping systems are descendants of the same ancestor. The Quickturn Systems Rapid Prototype Machine (RPM) introduced in May 1988 brought an array of Xilinx XC3090 FPGAs to emulate designs with hundreds of thousands of gates. From there, hardware emulators and FPGA-based prototyping … Read More

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Low end LTE UE categories seeing more action

Low end LTE UE categories seeing more action
by Don Dingee on 02-08-2016 at 4:00 pm
Categories: Ceva, IoT, IP, Mobile

Most of our attention goes toward the higher end of the LTE UE categories – ones designed for moving large amounts of multimedia data from smartphones and tablets concurrently with voice traffic. An equally interesting discussion is taking shape at the low end of the LTE UE categories targeting M2M and IoT devices with power-efficient,… Read More