Author: Daniel Payne

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Electromigration (EM) with an Electrically-Aware IC Design Flow

Electromigration (EM) with an Electrically-Aware IC Design Flow
by Daniel Payne on 11-03-2012 at 4:05 pm
Categories: Cadence, EDA

fig2a

Electromigration (EM) is a reliability concern for IC designers because a failure in the field could spell disaster as in lost human life or even bankruptcy for a consumer electronics company. In the old days of IC design we would follow a sequential and iterative design process of:… Read More

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Improving FPGA Prototype Debugging

Improving FPGA Prototype Debugging
by Daniel Payne on 10-30-2012 at 10:00 am
Categories: EDA

FPGA Prototyping is growing in popularity as a method to get an SoC design into hardware running at clock speeds up to 100MHz or so. One downside during traditional FPGA prototyping debug is the limited number of internal signals that you can observe while trying to chase down bugs in the hardware design in the presence of running … Read More

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An AMS Reference Flow for Power Management Designs

An AMS Reference Flow for Power Management Designs
by Daniel Payne on 10-26-2012 at 5:42 pm
Categories: Cadence, EDA

At DAC in June I visited and blogged about 30+ EDA and Semi IP companies, however I didn’t have time to watch the TowerJazz presentation in the Cadence Theater entitled: AMS Flow for Power Management Designs. Today I watched the 26 minute video and have summarized what I learned in this blog post.… Read More

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Learning about MEMS in Israel from: EDA companies, Foundry, University, Users

Learning about MEMS in Israel from: EDA companies, Foundry, University, Users
by Daniel Payne on 10-23-2012 at 12:24 pm
Categories: EDA, Synopsys

In April I attended and blogged about a webinar on MEMS and IC co-design hosted by two EDA companies: SoftMEMS and Tanner EDA. On October 30th you can attend a full-day event in Israel that is more comprehensive than the webinar that I attended.… Read More

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A Brief History of Aldec

A Brief History of Aldec
by Daniel Payne on 10-20-2012 at 5:31 pm
Categories: Aldec, EDA

Dr. Stanley Hyduke founded Aldecin 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Aldec maintains… Read More

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Designing with FinFETs

Designing with FinFETs
by Daniel Payne on 10-08-2012 at 6:13 pm
Categories: EDA, Synopsys
30 Comments

Intel is the number one semiconductor company in the world and has taken the lead in bringing FinFET (aka Tri-Gate) silicon to market at the 22nm node starting in May 2011, so now we see the pure play foundries playing catch-up and start talking about their own FinFET roadmaps. IC designers and layout engineers want to know how their… Read More

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EDA User: Rafaela Novais from TowerJazz Semi

EDA User: Rafaela Novais from TowerJazz Semi
by Daniel Payne on 10-04-2012 at 8:10 pm
Categories: Cliosoft, EDA
2 Comments

While reading an article on DeepChip I found an interesting comment from Rafaela Novais, a Design Support Manager at TowerJazz Semi and decided to interview her to learn more about her experience as an IC designer and EDA tool user.

… Read More

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EDA Solutions at Ultra Low Power Developer Forum Demonstrates Mixed-Signal Flow including Tools from Tanner EDA, Incentia and Aldec

EDA Solutions at Ultra Low Power Developer Forum Demonstrates Mixed-Signal Flow including Tools from Tanner EDA, Incentia and Aldec
by Daniel Payne on 10-04-2012 at 4:49 pm
Categories: Aldec, EDA, Tanner EDA

EDA Solutions, sole representative in Europe for Tanner EDA and Incentia Design Systems, is exhibiting at the ‘Design & Elektronik’ Developer Forum on Ultra Low Power in Munich, Germany, on October 10, 2012, at the Holiday Inn (Munich – City Centre).

EDA Solutions will be presenting its complete analog, digital and… Read More