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An AMS Reference Flow for Power Management Designs

An AMS Reference Flow for Power Management Designs
by Daniel Payne on 10-26-2012 at 5:42 pm

At DAC in June I visited and blogged about 30+ EDA and Semi IP companies, however I didn’t have time to watch the TowerJazz presentation in the Cadence Theater entitled: AMS Flow for Power Management Designs. Today I watched the 26 minute video and have summarized what I learned in this blog post.

Ofer Tamir
is the Director of Design Environment & Support at TowerJazz and he was the presenter. TowerJazz and Cadence built and tested a Power Management IC Reference Flow version 2.0.

They have four fabs (Israel, US, Japan), all focused on specialty AMS design of: CMOS, Power, RF, SiGE, CMOS Image Sensors, RFID, MEMs. As a pure-play foundry they are number 5 in the world offering nodes down to 130nm, which is adequate for AMS chip design. TowerJazz grew some 499% in the past 5 years.

OpenAccess is the IC database of choice in this reference flow between TowerJazz and Cadence. The PDK from TowerJazz has everything that an AMS designer needs:

Power management users can design from 20 to 80 Volts for LED backlighting, 1.8V CMOS with high voltage, >2 amp applications, and support up to 700V for AC to DC conversion or industrial LED lighting.

Cadence Environment
The custom and digital tools work together, Virtuoso and Encounter:

Their methodology removes conflicts between technology files used by Virtuoso and Encounter. TowerJazz supplies Analog blocks, memory library, standard cell library and an IO library.

Simulation of AMS designs is done with UltraSim (Fast SPICE), APS Spectre (SPICE) and NC-Sim (Verilog). For highest analog accuracy use APS Spectre, for faster simulation times UltraSim, and for mixed-mode simulation use NC-Sim.

This reference flow is supplied to customers of both Cadence and TowerJazz.

Both Digital and Analog Waveforms from a mixed-mode Simulati

Constraints were used in the reference design with Modgen to automate the process, allowing the circuit and layout designers to communicate precisely. Constraints include: Electrical, Placement and Routing.

For Power Management the reference design was done in Virtuoso on top, then Encounter only for digital blocks.

This big Analog, little Digital design was floor planned, Placed & Routed and assembled in Virtuoso. Modgen placed the analog elements (devices, guard rings, etc.) automatically, saving time over a manual methodology. The Digital block used Encounter for standard cell place & route. The implementation flow using OA is shown below:

In this methodology there is no use of LEF/DEF, because OA handles the bi-directional data flow between Virtuoso and Encounter.

The Mixed-mode Reference Flow version 2.0 uses the 6.1.5 release of Cadence tools. It’s easy to start with this reference flow in your specific IC designs, so that you’re not setting up your own scripts and methodology. There’s even written documentation on how to use this reference flow.

When you design an AMS chip with TowerJazz as the foundry and use Cadence tools, then consider using the pre-built reference flow version 2.0 to minimize your CAD support and maximize your IC design productivity. This reference design flow is silicon-proven down to the 130nm node.