Webinar on Multi-voltage/VT/Channel Length Libraries

Webinar on Multi-voltage/VT/Channel Length Libraries
by Daniel Payne on 08-02-2012 at 8:10 pm

ken brock

Ken Brockof Synopsys presented on how to optimize your SoC design for low power at 40nm, 28nm and 20nm nodes in a webinar today. Ken and I both worked together at Silicon Compilers back in the late 1980’s, the best EDA/IP company that I’ve had the pleasure to join.

The webinar made a brief mention of 14nm and FinFETS but … Read More


Schematic Capture and SPICE Simulation in the Cloud

Schematic Capture and SPICE Simulation in the Cloud
by Daniel Payne on 07-31-2012 at 8:10 pm

In April I blogged about using the iPad for schematic capture and SPICE circuit simulation. My conclusion was that the technology was interesting but not quite ready for commercial use. Today I tried out the web-based version using my Google Chrome browser instead of the iPad. Install the Chrome app here or visit www.ischematic.comRead More


Synopsys Acquires Ciranova

Synopsys Acquires Ciranova
by Daniel Payne on 07-30-2012 at 6:00 pm

Consolidation continues in the EDA industry with Synopsys announcing today that they acquired Ciranova, a provider of software to automate custom IC layout. Remember that Synopsys invested in Ciranova back in March 2008 and September 2010 (along with Intel Capital, Mentor Graphics and Alloy Ventures), so this deal has some … Read More


Parasitic-Aware Design Flow with Virtuoso

Parasitic-Aware Design Flow with Virtuoso
by Daniel Payne on 07-27-2012 at 12:01 pm

I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More


Libraries Make a Power Difference in SoC Design

Libraries Make a Power Difference in SoC Design
by Daniel Payne on 07-23-2012 at 4:37 pm

ken brock

At Intel we used to hand-craft every single transistor size to eek out the ultimate in IC performance for DRAM and graphic chips. Today, there are many libraries that you can choose from for an SoC design in order to reach your power, speed and area trade-offs. I’m going to attend a Synopsys webinar on August 2nd to learn more Read More


How Do You Extract 3D IC Structures?

How Do You Extract 3D IC Structures?
by Daniel Payne on 07-18-2012 at 2:01 pm

The press has been buzzing about 3D everything for the past few years, so when it comes to IC design it’s a fair question to ask how would you actually extract 3D IC structures for use by analysis tools like a circuit simulator. I read a white paper by Christen Decoin and Vassilis Kourkoulos of Mentor Graphics this week and became… Read More


An Approach to 20nm IC Design

An Approach to 20nm IC Design
by Daniel Payne on 07-17-2012 at 10:10 am

Last month at DAC I learned how IBM, Cadence, ARM, GLOBALFOUNDRIES and Samsung approach the challenges of SoC design, EDA design and fabrication at the 20nm node. Today I followed up by reading a white paper on 20nm IC design challenges authored by Cadence, a welcome relief to the previous marketing mantra of EDA 360.

Here’s… Read More


Using Synopsys Analysis Tools for AMS Design

Using Synopsys Analysis Tools for AMS Design
by Daniel Payne on 07-11-2012 at 12:05 pm

I attended the Synopsys webinar today for a tool called Custom Explorer Ultra (CXU). Product details on the Synopsys web site are here. The CXU tool would be used by AMS designers that want to setup, control and view results from simulators like HSPICE, CustomSim or VCS on transistor-level and AMS designs.… Read More


SPICE Timing Correlation for IC Place and Route

SPICE Timing Correlation for IC Place and Route
by Daniel Payne on 07-10-2012 at 10:35 am

SPICE circuit simulation is used for transistor-level analysis while Place and Route tools are typically used to connect cells and blocks of an SoC, so why would there be a connection between these two EDA tools?

I read a press release today from ATopTech and Berkeley Design Automation that talked about how SPICE and P&R are … Read More


IC Design at Novocell Semiconductor

IC Design at Novocell Semiconductor
by Daniel Payne on 07-05-2012 at 12:09 pm

In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More