FineSIM adds RF Analysis plus new Tcl Circuit Checks

FineSIM adds RF Analysis plus new Tcl Circuit Checks
by Daniel Payne on 06-13-2011 at 4:58 pm

At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

Greg Curtis – Product Director, Custom Design Business Unit

– Talus for Digital Design
– FineSim does: SPICE, FastSPICE, Characterization
– Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
– What’s New in FineSim?o… Read More


Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop

Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop
by Daniel Payne on 06-13-2011 at 12:57 pm

I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.

Intro

Physware – served the package and board markets, co-design challenges (can add IC noise sources).… Read More


Magma, ARM, GLOBALFOUNDRIES

Magma, ARM, GLOBALFOUNDRIES
by Daniel Payne on 06-06-2011 at 11:07 am

Introduction
Monday morning at DAC I attended the breakfast presentation from Magma, ARM and GLOBALFOUNDRIES. The 28nm node is ready for business using Magma tools and ARM libraries.

During breakfast I met Karim Arabi, Ph.D. from QualComm. He’s a senior director of engineering in San Diego and wanted to learn more about… Read More


Sunday Night at DAC

Sunday Night at DAC
by Daniel Payne on 06-05-2011 at 7:23 pm

San Diego Arrival
It’s another picture perfect day in San Diego as I arrived and checked into the Hyatt. The view from the 40th floor looked magnificent, with the Convention Center just a few minutes away in the distance:

Registration

Check in at DAC is quite automated and it took only a minute to receive my official badge with… Read More


Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review

Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review
by Daniel Payne on 05-19-2011 at 5:33 pm

Introduction
Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.

What’s New from Cadence in Virtuoso 6.1.5

  • Back2Basics (28nm rule integration, Skill improved with object-oriented, OASIS support, HTML Publisher, Waveform re-written for better Analog support, smaller Waveform
Read More

A New Hierarchical 3D Field Solver

A New Hierarchical 3D Field Solver
by Daniel Payne on 05-19-2011 at 2:04 pm

Introduction
3D field solvers produce the most accurate netlists of RC values of your IC layout that can then be used in SPICE circuit simulators however most of these solvers produce a flat netlist which tends to simulate rather slowly. Thankfully several years ago the first hierarchical SPICE tools were offered by Nassda (HSIMRead More


Shakeup at Mentor Graphics

Shakeup at Mentor Graphics
by Daniel Payne on 05-12-2011 at 12:22 pm

Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:

  • José Maria Alapont, chief executive of the auto parts maker Federal-Mogul
  • Gary Meyers, a director of the chip maker Exar
  • David Schechter, an executive at Mr. Icahn’s investment firm
Read More

Two New Platforms for Systems Designers

Two New Platforms for Systems Designers
by Daniel Payne on 05-03-2011 at 7:03 pm

Introduction
Today Cadence announced at the Embedded Systems Conference something of interest to systems designers.

What’s New?
The Rapid Prototyping Platform and Virtual System Platform are what’s new, and they intend to enable and automate concurrent hardware and software development. I can remember Mentor… Read More


Graphical DRC vs Text-based DRC

Graphical DRC vs Text-based DRC
by Daniel Payne on 05-01-2011 at 11:42 am

Introduction
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.

At the 28nm node a typical DRC (Design Rule Check) deck will… Read More