Power-Aware Debug to Find Low-Power Simulation Bugs

Power-Aware Debug to Find Low-Power Simulation Bugs
by Daniel Payne on 09-09-2016 at 12:00 pm

When I worked at Intel designing custom chips my management would often ask me, “Will first silicon work?” My typical response was, “Yes, but only for the functions that we could afford to simulate before tape-out.” This snarky response would always cause a look of alarm, quickly followed by a second … Read More


Five Things To See at DVCon India 2016

Five Things To See at DVCon India 2016
by Daniel Payne on 09-02-2016 at 12:00 pm

DVCon is an annual Design and Verification Conference that started out in Silicon Valley, then expanded by adding India as a new location. Our semiconductor design and verification world is global in stature, so if you’re living in the region then consider registering for this event held Thursday and Friday, September Read More


Three Steps for Custom IC Design Migration and Optimization

Three Steps for Custom IC Design Migration and Optimization
by Daniel Payne on 08-31-2016 at 7:00 am

Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one?… Read More


Low Frequency Noise Challenges IC Designs

Low Frequency Noise Challenges IC Designs
by Daniel Payne on 08-28-2016 at 7:00 am

AMS and RF IC designers have known for years that their circuits are sensitive to noise, because if you amplify noise on an input source to an amplifier circuit then your chip can start to produce wrong answers. Even digital SoC designers need to start taking notice because every SoC is filled with SRAM IP blocks, and at each shrinking… Read More


Did My FPGA Just Fail?

Did My FPGA Just Fail?
by Daniel Payne on 08-22-2016 at 12:00 pm

Designing DRAMs at Intel back in the 1970s I first learned about Soft Errors and the curious effect of higher failure rates of DRAM chips in Denver, Colorado with a higher altitude than Aloha, OR. With the rapid growth of FPGA-based designs in 2016, we are still asking the same questions about the reliability of our chips used for safety-critical… Read More


Are Your Transistor Models Good Enough?

Are Your Transistor Models Good Enough?
by Daniel Payne on 08-16-2016 at 12:00 pm

SoC designers can now capture their design ideas with high-level languages like C and SystemC, then synthesize those abstractions down into RTL code or gates, however in the end the physical IC is implemented using cell libraries made up of transistors. Circuit designers use simulation tools like SPICE on these transistor-level… Read More


Catching low-power simulation bugs earlier and faster

Catching low-power simulation bugs earlier and faster
by Daniel Payne on 08-15-2016 at 7:00 am

I’ve owned and used many generations of cell phones, starting back in the 1980’s with the Motorola DynaTAC phone and the biggest usability factor has always been the battery life, just how many hours of standby time will this phone provide and how many minutes of actual talk time before the battery needs to be recharged… Read More


A Software Company Making Hardware

A Software Company Making Hardware
by Daniel Payne on 08-08-2016 at 12:00 pm

I’ve been a daily Facebook user for many years now and it keeps me in touch with family, friends, some business contacts and even a handful of high-tech companies. My first impression is that Facebook is a very successful, cloud-based, social platform staffed with software developers and a few marketing mavens. On closer… Read More


At What Point Does Transistor Gate Length Stop Getting Smaller?

At What Point Does Transistor Gate Length Stop Getting Smaller?
by Daniel Payne on 08-03-2016 at 12:00 pm

When I started doing IC design back in 1978 we had 6,000 nm channel gate lengths, and today you can buy a smart phone with 16 nm or 14 nm technology, although the gate lengths in those phones are more like 34 nm. The International Technology Roadmap for Semiconductors (ITRS) makes predictions about emerging trends in our industry and… Read More


Reducing Data Centre Cooling by 40%

Reducing Data Centre Cooling by 40%
by Daniel Payne on 07-22-2016 at 12:00 pm

Living in Oregon has many benefits, including access to cheap electricity thanks to the plentiful river systems that provide hydro power and a growing green power business fueled by wind and sun. Many of the world’s largest data centers are located in Oregon for access to this cheap electricity, and Google has a sizable investment… Read More