There’s been an interesting trend emerging the past couple of years; a gentrification, if you will, of the ASIC business. What was thought to be a dying supply chain model has re-emerged as a health and growing segment of the semiconductor industry. Recent figures from Gartner place 2012 ASIC revenue at around $24.4 billion… Read More
Author: Daniel Nenni
Why Blog on SemiWiki.com?
The Semiconductor Wiki Project, the premier semiconductor collaboration site, is a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem. Since going online January 1st, 2011 more than 400,000 unique visitors have landed at www.SemiWiki.com viewing more than 3M pages… Read More
TSMC OIP Forum 2012 Trip Report!
The second annual TSMC Open Integration Platform Ecosystem Forum was last week and let me tell you it was excellent. Great update on the TSMC process technology road maps, great for networking within the fabless semiconductor ecosystem, great for seeing what’s new in EDA and IP, and great for SemiWiki. It was time well spent for … Read More
Current Timing Closure Techniques Can’t Scale – Requires New Solution
There’s a nice article on timing closure by Dr. Jason Xing, Vice President of Engineering at ICScape Inc. on the Chip Design website. Not familiar with ICScape? Paul McLellan called ICScape the The Biggest EDA Company You’ve Never Heard Ofand Daniel Payne did Schematic, IC Layout, Clock and Timing Closure from ICScape at… Read More
Oct. 18 Non-Volatile Memory Webinar, IBM validates OTP for Foundry program, & New Low-Risk Evaluation License
As the temperature drops and the bright red maple leaves have begun to pile up, so has the stack of projects at Novocell. If you are expecting to utilize their high reliability, easy-to-integrate OTP in a project taping out in late Q4 or early Q1, NOW is the time to contact them.
Novocell and global … Read More
Power Integrity Challenges for High Speed and High Frequency Designs
There is an interesting discussion on the LinkedIn SoC Power Integrity Group in regards to the power integrity challenges for high speed and high frequency designs. More specifically, the additional attention an on-chip power delivery network (PDN) requires as the operating frequency of ICs and SoCs increases.
The PDN has to… Read More
Advanced Node Design Webinar Series
At advanced process nodes, variation and its effects on the design become a huge challenge. Join Cadence® Virtuoso® experts for a series of technical webinars on variation-aware design. Learn how to use advanced technologies and tools to analyze and understand the affects of variation. We’ll introduce you to the latest Virtuoso… Read More
Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design Paper
Silicon Creations will be presenting a paper with Berkeley Design Automation at the TSMC Open Innovation Platform (OIP) Ecosystem Forum next week where TSMC’s design ecosystem member companies and customers share real-case solutions for design challenges within TSMC’s design ecosystem:
This presentation will describe … Read More
Challenges in Managing Power Consumption of Mobile SoC Chipsets: And What Lies Ahead When Your Hand-Held Is Your Compute Device!
Qualcomm VP of Engineering, Charlie Matar, will be keynoting the Apache/ANSYS seminar in Santa Clara next Thursday. Charlie is a great guy and a great speaker so you won’t want to miss this and it’s FREE! I spoke to Charlie, he will be speaking on:
Today’s complex SOC design is driven by the constant demand for high performance… Read More
Silicon Correlation, Not EDA Marketing Sparkles!
It’s all about the silicon. It’s all about silicon correlation. TSMC Open Integration Platform should be renamed TSMC Silicon Correlation Platform or TSMC SCP. One of the problems I have with EDA technical papers today is that they are not silicon based. Anybody can put up slides with marketing sparkles on them but if you want qualified… Read More
Weebit Nano Brings ReRAM Benefits to the Automotive Market