TSMC Updates: 20nm, 16nm, and 10nm!

TSMC Updates: 20nm, 16nm, and 10nm!
by Daniel Nenni on 05-05-2014 at 2:30 pm

*Spoiler Alert: The Sky is Not Falling*
The TSMC Technology Symposium last month provided a much needed technology refresh to counter aging industry experts (they make their living selling reports) who have been somewhat negative on the future of the fabless semiconductor ecosystem. If the sky wasn’t falling who would… Read More


The Number One ASIC Racing Team!

The Number One ASIC Racing Team!
by Daniel Nenni on 05-04-2014 at 9:45 am

This weekend I was in the pits for the Flying Lizard Motorsports team at the Monterey Grand Prix. It was an auction item (donated by eSilicon) at EDA’s 50[SUP]th[/SUP] Anniversary party last year, and let me tell you it was an amazing experience and a very interesting story, absolutely. But first let me tell you that if you get a “Hot… Read More


Aldec is Celebrating 30 Years @ #51DAC!

Aldec is Celebrating 30 Years @ #51DAC!
by Daniel Nenni on 05-02-2014 at 8:00 am

Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec … Read More


Kurt Shuler: Arteris Presentation at EDPS 2014

Kurt Shuler: Arteris Presentation at EDPS 2014
by Daniel Nenni on 04-30-2014 at 9:00 am

The Electronic Design Process Symposium is an annual workshop run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. I presented there because it’s devoid of product marketing pitches, and is two days of discussion on technical and process issues in SoC design. My slides are here:… Read More


Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance

Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance
by Daniel Nenni on 04-29-2014 at 10:00 am

Tanner EDA is making waves at their customer’s sites as the mixed-signal design suite from Tanner EDA, Incentia Design Systems, Inc. and Aldec, Inc. helps ASIC Design House lower cost and increase efficiency with no compromise in performance. In today’s ‘always on’, Internet of Things connected world, the demand for high-performance,… Read More


Carey Robertson: Reliability Checks in Advanced Nodes

Carey Robertson: Reliability Checks in Advanced Nodes
by Daniel Nenni on 04-28-2014 at 8:30 pm

Last week I had the pleasure of presenting at the Electronic Design Process Symposium (EDPS) workshop. This was my first time attending and I was very impressed. There were good presentations but I learned as much from the Q&A and the side conversations before/after/breakfast/lunch/etc. If you have the opportunity to attend,… Read More


Dr. Bernard Murphy: My presentation at EDPS 2014

Dr. Bernard Murphy: My presentation at EDPS 2014
by Daniel Nenni on 04-28-2014 at 8:00 am

First, I wish there were more conferences/workshops like this. This is much more about sharing ideas and brainstorming than the stark commercialism of DAC. I presented Atrenta’s role in enabling 3[SUP]rd[/SUP]-party IP qualification for the TSMC soft IP library.

My presentation slides are located here:

http://www.eda.org/edps/Papers/5-3%20Bernard%20Murphy.pdfRead More


TSMC Will Own the Internet of Things!

TSMC Will Own the Internet of Things!
by Daniel Nenni on 04-27-2014 at 8:00 am

In my quest to uncover the future of the semiconductor industry I was quite impressed by the executive presentations at the TSMC Symposium last week. Rick Cassidy opened the 20[SUP]th[/SUP] Annual TSMC Technology Symposium followed by Dr. Mark Liu, Dr. Jack Sun, Dr. Cliff Hou, J.K Wang, Dr. V.J. Wu, and Suk Lee. A variety of topics… Read More


Webinar: Making Design Reuse Work

Webinar: Making Design Reuse Work
by Daniel Nenni on 04-26-2014 at 9:00 pm

Please join me for an IP conversation in collaboration with ClioSoft on Wednesday, April 30th, 2014 @ 11:00 AM PST. At the EDPS Workshop IP day there were two interesting presentations on IP reuse. The first one was by Warren Savage of IPextreme: Top Ten Reasons Why Internal IP Reuse Fails. The second was by Ranjit Adhikary of ClioSoft:… Read More


Dr. Morris Chang: A Conversation with the Chairman

Dr. Morris Chang: A Conversation with the Chairman
by Daniel Nenni on 04-24-2014 at 10:00 pm

There are moments in one’s career that are memorable beyond others, and last night was one of those moments for me, absolutely:

Stanford University President John L. Hennessy will lead a discussion with Stanford Engineering Hero Morris Chang, an innovator and entrepreneur who revolutionized the semiconductor industry by creatingRead More