Sony Endorse FD-SOI to Attack Wearable & IoT

We are writing about FD-SOI technology since the beginning of 2013 in Semiwiki. So far, most of the design experience was related to ST-Microelectronics (even if IBM and GlobalFoundries have been actively working on the technology, probably more on a research mode than pure production). Sony being actively working to develop consumer products on FD-SOI technology (since 2012) is a real indicator about FD-SOI momentum in the SC industry. The paper presented at the SOI forum in Tokyo last month is here.

Sony is playing in the consumer electronic (CE) segment, probably the most crowded after the mobile. An OEM can play different strategies to win in the CE segment, for example developing “me-too” products, cheapest than the original, but with no differentiators. That’s not the way Sony is playing! Sony is an OEM (developing IC internally when it make sense) being recognized as one of the most innovative in the industry, and Sony’s winning strategy is to launch highly differentiated new products. When talking about wearable and IoT, ultra-low power is certainly one of the most important differentiator. If you analyze this well-known formula:

You understand why Sony has heavily invested into FD-SOI to develop IC targeting wearable and IoT. Designing with FD-SOI allow minimizing the two components of power consumption:

• Running the device at a much lower Vdd (0.6V instead of 1.1V) than Bulk CMOS dramatically divides the active power consumption (in V[SUP]2[/SUP][SUB]dd)[/SUB]
• Because FD-SOI active device is by nature built on Insulator, the leakage current is lower, so the related power consumption (I[SUB]leak[/SUB] V[SUB]dd)[/SUB]

I realize that we have mostly write about high complexity (and high performance) logic IC designed in FD-SOI, like Application Processor or IC supporting communication infrastructure. But SOI in general and FD-SOI can be extremely effective for RF design as well: on the above picture Low power RF device exhibits:

• Very high Intrinsic Gain for FD-SOI 28nm, compared to Bulk 28 or 40nm
• Comparable noise

Sony has developed an analog chip in 28nm FD-SOI to explore the possibility to design an extremely low power GPS, opening the door for wearable GPS devices. It’s very exciting to see that FD-SOI analog behavior is very promising, like the pure logic behavior. If you look at Sony presentation here you realize that the assessment process has been extremely stringent: the design team has optimized the libraries, designing various gate length options, verified the minimum Vdd to run SRAM, on top of the analog specific simulation and measurement above described. Designing IC for GPS localization, as I have learned a couple of years ago when consulting for an ASIC customer, requires the availability of: High performance analog front end, relatively large on-chip SRAM, very sophisticated algorithm (the real Intellectual Property in fact)… and obviously the right embedded CPU to run these algorithms.

Sony has demonstrated in this presentation that FD-SOI was a very good choice to support such GPS application (thanks to the availability of high performance ARM CPU core, already demonstrated by ST-Microelectronics on the technology), offering even better analog performances than an equivalent Bulk node. But the true killer is the ultra-low power consumption demonstrated on FD-SOI, allowing developing consumer application, wearable or IoT, with a strong competitive advantage. If the effective power budget is 1/10[SUP]th[/SUP] of the equivalent on Bulk, this means that the “thing” you are wearing will need to be charged a couple of time a month instead of every day. This can make the difference for the end user: are you ready to buy another system that you have to charge every day, on top of your smartphone, your smart-watch, etc…?

Sony sharing about their design experiences with FD-SOI is almost a symbol: FD-SOI penetration in consumer application has started!

Next “rendez vous”: SOI Forum in San Francisco on February 27[SUP]th[/SUP], to register: RF-SOI and FD-SOI Forum San Francisco

From Eric Esteve from IPNEST