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Avoiding layout related variability issues

Avoiding layout related variability issues
by Daniel Nenni on 05-26-2013 at 7:55 am

In advanced process technologies, electrical and timing problems due to variability can become a big issue. Due to various processing effects, a circuit performance (both speed and power) is dependent on specific layout attributes and can vary a lot from instance to instance. The accumulated effects can be severe to the point that it may cause the circuit to fail.

In this blog I will demonstrate how iDRM is used very effectively to measure and analyze millions or even billions of layout instances and determine possible impact on performance. We will focus on two layout dependent effects that affect transistor performance:

  • Well Proximity Effect (WPE). Transistors that are close to the well edge have a different performance (mostly due to modified Vt) than ideally placed transistors. The effect can vary the transistor speed by ±10%.
  • Stress/strain effect. This effect causes the mobility of charge carriers in transistors to change which causes changes in device Idon. The precise quantitative effect is very process dependent and can vary the transistor speed by ± 30%.

There are various situations where such analysis is needed. The context can be one where a legacy design or IP is being integrated or reused by another group, or when a design is sent to be fabricated by a different foundry than the one originally designed for.

The approach we take is to gather general statistics on the above variation effects for every device in the layout and then analyze the value distribution. We want to check if there are any significant outliers from the regular expected data, and also look for general shifts in the distribution that can make the overall average faster or slower than expected.
The specific WPE and stress effects described here apply mostly to the 28nm and 40nm nodes. A similar approach can be used for variability checks in fin-FET designs, for example due to the impact of certain layer density variations.

Defining what to look for using iDRM

Using iDRM, we define two patterns that will be used to gather statistics from a physical design.

  • The first pattern will be used to measure WPE effects:

    • We draw a transistor (crossing Poly and Diffusion edges) of which the W/L is measured and we draw the well edges around the device (see WPE figure). Note that the well edges display a “multiple edge” shading since a single transistor may be enclosed by multiple well edges on each side.
    • We enter a formula to calculate the minimal distance of the well edges to the transistor gate center. This is the minimum of all four side distances as in the expression shown in the picture. We call this variable WPE.
    • A dSpeed variable is created to calculate the speed impact as: (1/0.24 – 1/WPE). The chosen reference distance value 0.24 is an average value for devices in the nominal range. dSpeed represents the speed difference between a nominal transistor and each one being matched. A non-zero dSpeed will indicate a layout irregularity that deviates from the nominally modeled and characterized devices and might present a WPE risk that warrants further analysis.

    Obviously, you can use a more advanced WPE to speed model, but this simple model is already sufficient to reveal valuable information. The purpose is not to exactly predict speed impact, but to identify potentially risky deviations from nominal, well modeled design.


  • The second pattern will detect one of the major stress/strain influencing effects. This is LOD (Length Of Diffusion), the amount of SD diffusion area that extends away from the gate.
  • The pattern is similar to the WPE pattern. Again the transistor is drawn and the relevant distances are measured and a simple formula is used to calculate a dSpeedLOD. The chosen reference value 0.075 is an average distance from the gate centerline to the diffusion edge in nominally drawn and modeled devices. Any dSpeedLOD which deviates from 0 indicates a non-nominal device that requires further inspection.

    Gathering and processing physical data
    Once the patterns have been defined, we can run them on the physical design. Run times will vary from a few minutes for a block to a few hours for a full chip. During the run, iDRM will automatically record the following:

    • all the locations where such patterns were found
    • for each such location (match instance): the actual values of the distances that were defined in the pattern definition
    • all the evaluated expressions

    Interpreting statistical results
    iDRM has powerful features to display results of statistic data collection:

    • Frequency graphs where the occurrence count (how often does a specific value occur in the layout) of a variable (e.g. a distance) is plotted against the value of the variable.
    • 2-D graphs where two variables are used, and occurrence counts are displayed color coded
    • Pareto charts, showing cumulative occurrence of combinations of multiple variable values
    • Plain tables displays
    • Exports to *CSV files that can be used by other tools.

    All statistics views are linked to the layout and it takes one-click to find and view all occurrences of any specific value combination in the design.

    We ran these patterns on a typical test SOC layout and found that both distributions have some interesting characteristics.

    WPE Statistics
    (see occurrence graph below)
    Looking at the WPE occurrence graph, we find the largest group of occurrences around rule value zero, which is expected. But there is also a peak at rule value= -9.5 (remember, the actual value is not that important, we are mostly checking if this is a normal distribution) which indicates a large number of devices that were laid out in a special way. After inspecting the layout for this value, which is just one mouse-click away from the statistics view, we could see that these are all long-L small-W devices close to a well edge in a special standard cell (a power down retention circuit). We did find a special circuit, which might be variation and yield sensitive by just looking at statistics, and without knowing the design. We can now focus on these circuits and further analyze their impact.

    LOD Statistics(see occurrence graph below)
    Looking at the LOD distribution we see a big peak in occurrence count at value -2.8. After inspecting these instances they turned out to be special transistors in a memory array. Assuming that the memory cells are properly characterized, we can ignore these.


    iDRM enables an easy to use and yet very powerful mechanism to analyze legacy or otherwise not fully familiar designs; sort through a huge amount of physical design data, and quickly identify specific design objects that may impact performance or yield and thus require further analysis.

    Defining the patterns and measurements is done graphically and takes less than an hour and requires no programming skills.

    In addition to the above examples, iDRM can be used to search, measure and analyze many other physical design objects and phenomena that can have an impact on design integrity, performance and yield.

    Further information can be found at Sage’s white paper here.

    Sign up for a demo at DAC booth #2233 here.

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