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iDRM Brings Design Rules to Life!

iDRM Brings Design Rules to Life!
by Pawan Fangaria on 05-11-2013 at 8:00 pm

Much awaited, automatic tool for DRM (Design Rule Manual) and DRC (Design Rule Check) deck creation is here now! I am particularly excited to know about this because I had been hearing for its need (in different context) from the designers with whom I was working to improve their design productivity through the use of our EDA tools (in my past company). Considering ever growing size and complexity of DRM (in terms of number of complex rules with multiple variables and conditions associated with them) as we go down on process node, it’s natural to expect an automated tool to ease the process.

Traditionally, DRM is written manually by process engineers without any standards; these are secret rules (or limitations in other words) of fabs at a particular process node, available in hard copy or at best, PDF. Programmers or CAD engineers are at mercy of that description to understand it in right manner and develop DRC (Design Rule Check) deck which is software code to implement checks for those rules and flag violations. The whole process is very rigid, manual, unidirectional, time consuming and error prone. Ironically, the designers who actually have to verify their designs against these rules have no say in this whole process. For any change in any of the rule, they have to wait for long sacrificing on the window of opportunity for their design. The DRM and DRC deck, at the very first instance, take years (going through several iterations) before they become available to designers and others with reasonable confidence of correctness.

I am impressed with Sage Design Automation who could visualise this process bottleneck in the overall value chain of semiconductor industry, changed the paradigm and came up with an innovative concept and tool called iDRM (Integrated Design Rule Management).

iDRM is a essentially a design rule compiler integrated with a graphical editor which can capture design rules in terms of layout patters, arrows marking limitations between different shapes such as width, separation etc. and expressions defining the rules; like the example above.

Once the rule is captured, iDRM automatically transforms it into an executable program which can be run on any production layout to validate that against the rule. This delights the process engineer who can then run it on a particular layout, obtain pass/fail report and compare with the actual process induced issues such as litho hotspots. In case of any mismatch, he/she can quickly modify the rule description to match it accurately with the process.

[Correlating iDRM rule with imported fabrication/litho failure data]

iDRM can automatically generate QA pass/fail test patterns for each captured rule. This can be used to generate large sets of QA test structures with maximum coverage, which used to be a much time consuming process otherwise. Moreover, it is consistent and accurate with respect to the captured rule. These can be used to verify correctness and completeness of any third party tool DRC deck.

[DRC deck QA test patterns generated by iDRM]

iDRM can also generate statistical graph (in various formats such as bar chart) of all occurrences of any particular pattern (matching to the captured rule) in the design and its integrated layout viewer can locate the exact position of a pattern. This provides a good way to scan and analyze the overall layout.

Overall concept is very novel which bridges the gap between process and design by automating the design rule generation and verification. The tool, iDRM is very user friendly, flexible, easy-to-use and provides a graphical platform for formal, clear, unambiguous depiction of design rules, thus eliminating any communication gap or error for faster closure. It takes order of magnitude lesser time to create a complete and correct DRM and DRC deck together. Any change can easily be accommodated. Definitely, it provides competitive advantage to those who are using it. Designers too can cheer up on using this tool in their design flow to create specific, robust and optimum layout structures that can provide high yield and performance; of course design rule correct. That can provide them a differentiated edge!!

Further information can be found at Sage’s white paper here.

Sign up for a demo at DAC booth #2233 here.


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