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Fault Sim on Multi-Core Arm Platform in China. Innovation in Verification

Fault Sim on Multi-Core Arm Platform in China. Innovation in Verification
by Bernard Murphy on 04-24-2024 at 6:00 am
Categories: Cadence, EDA

Innovation New

How much can running on a multi-core (Arm) CPU speed up fault simulation? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Fault Simulation Acceleration Based on ARM Multi-core CPU Architecture. This article was published in the 2023 IEEE Asian Test Symposium. The authors are from HiSilicon and Huawei.

This paper on fault simulation throughput exploits parallelism on a multi-core CPU. Curiously there is no mention of safety applications in this or in a recent reference they cite, suggesting an enduring interest in China for fault sim for regular test grading, here I would imagine for communications systems? The authors mention GPU-based and distributed compute as acceleration alternatives but note these suffer from multiple drawbacks. In contrast, they claim their proposed solution using 128 cores is much easier to program and offers meaningful acceleration.

Paul’s view

Verification of test patterns is an N x M style problem where N is the number of patterns and M is the set of possible faults (stuck-at-1, stuck-at-0, …). Each pattern-fault pair can be simulated in parallel, but for commercial scale designs N x M is in the billions so there is still a massive amount of serialization of sims even if thousands of CPU cores can be allocated.

This paper shares 3 insights parallelizing pattern-fault sims on modern high core-count Arm servers to maximize throughput. Results are presented on a 128-core Huawei Kunpeng 920 server.

The first insight relates to vectorizing faults, what commercial EDA tools call “concurrent fault simulation”. A 64-bit word can be used to represent the value on a wire across 64 different fault simulations. The authors observes that the SIMD capabilities in the Arm NEON unit can be used to increase the number of concurrent fault sims per core from 64 to 128. This gives a ~1.6x speed-up.

The second insight relates assigning pattern-fault pairs to cores. The authors observe that it’s better to parallelize patterns across cores rather than faults across cores. This gives an impressive 2.2x speed-up.

Lastly the authors observe that the 128 cores are split across 4 dies, each die with a direct link to “local” DRAM memory. Any core in any die can access DRAM from any die, but the latency for local DRAM access is 3-4x faster. By replicating the design data (which is constant and shared across all sims) in local DRAM for each die they get a 1.2x speed-up.

Overall, tight paper with clear insights and real benefits directly applicable to commercial EDA use today. Nice.

Raúl’s view

Fault simulation can be accelerated by simulating faults or test patterns in parallel; faults are independent of each other as are test patterns. This paper evaluates simulating faults and test patterns in parallel on a specific non-uniform memory access (NUMA) architecture, Kunpeng 920. It consists of 2 CPUs with two nodes each, each node having 32 ARM cores. The local node memories have varying access times depending on which node is accessing them.

The paper explains all the methods used to accelerate simulations: As usual many bits are packed into a word; using a particular data type in the ARM NEON architecture, 64 or 128 patterns can be simulated simultaneously; Execution threads are bound to cores and memory based on the memory access delay (binding optimization). The simulated netlist is replicated to optimize cross-node memory access; Fault data is segmented and allocated to the four memories.

The experimental results for 5 circuits (ITC99 and IWLS2005 benchmarks and industrial circuits, presumably their own) show that, as expected, pattern parallelism is faster than fault parallelism by a factor of 1.11-3.74, around 2 on average. This is because in pattern parallelism fault simulations can be started right after each pattern is simulated correctly (on the faultless design), while in fault parallelism first all patterns must be simulated correctly. However, pattern parallelism consumes more memory. Other results reported are: Parallel simulation of 128 patterns is about 1.6 times quicker than 64; Binding optimization gives 1.06x to 1.29x speedup; Lastly, cross-node memory access optimization gives 1.13x to 1.52x speedup.

The paper does not review or compare the state of the art, does not contextualize the work, and makes unsupported claims such as “Compared with the previous technical scheme, the ARM multi-core CPU used in this paper has the advantages of low cost and low energy consumption…”. I found the paper a valuable report that contains many details of the implementation, and a helpful insight into how to speed up fault simulation.

Also Read:

Anirudh Keynote at CadenceLIVE 2024. Big Advances, Big Goals

Fault Sim on Multi-Core Arm Platform in China. Innovation in Verification

Cadence Debuts Dynamic Duo III with a Basket of Goodies

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Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity

Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity
by Fred Chen on 04-23-2024 at 10:00 am
Categories: Lithography
3 Comments

Self aligned blocking scheme

There has been much interest in Huawei’s and SMIC’s plans for 5nm production in the near future. Since there is no use of EUV in China, immersion DUV lithography (with a 76 nm pitch resolution) is expected to be used along with pitch quartering to achieve pitches in the 20-30 nm range expected for the 5nm and 3nm nodes [1].

However, Samsung and TSMC were early adopters of EUV technology, and had not demonstrated the use of immersion lithography with pitch quartering in their metal layers, for 7nm onwards. Intel used pitch quartering with an extended effort to bring 10nm (now Intel 7) to production. This effort spanned years, with Intel subsequently adopting EUV. One thing in common with all these 7nm developments was that they all had been disclosed in the 2017-2018 timeframe. Hence, all three companies have not had the chance to digest the latest improvements in multipatterning productivity at the time. In this article, we will cover how these developments can be used to eliminate the expected burden of multipatterning involving pitch quartering, as expected for 7nm, 5nm, and 3nm nodes.

Self-Aligned Blocks

The first key development to highlight is the use of self-aligned blocking. This was published in 2017 [2-4]. The motivation here is that in order to cut lines with pitches between 20 and 40 nm into interconnect patterns, many (4 or more) additional block masks would be needed [2]. Moreover, the tight placement control for the individual patterns for blocking the trench etch due to rounding [5] is still thwarted by stochastic behavior. To alleviate this, self-aligned blocking arranges the lines to be alternately divided into two groups, each consisting of a different material to be etched (Figure 1). The two materials may be silicon dioxide and silicon nitride, for example. This division into two etch material groups naturally occurs with pitch quartering by self-aligned quadruple patterning (SAQP) [2].

Figure 1. Self-aligned blocking scheme. Left: original block arrangement has four separate cut masks (each indicated by different color). Right: self-aligned blocking allows two cut masks for the block arrangement.

By ensuring that the adjacent line material is not etched, the blocking pattern can be elongated, merging aligned cuts on every other line, as well as circumventing rounding consequences. As shown in Figure 1, four cut masks can be reduced to two. As EUV also needs to avoid the effects of stochastic rounding and edge placement error, self-aligned blocking has been incorporated into the well-known SALELE scheme [6].

Block/Cut Redistribution/Expansion

The second key development to highlight was disclosed even earlier [7-9]. The idea here is to redistribute cut locations by extending and/or shifting line segments (wires) as needed. Figure 2 shows an M0 (lowest metal layer) example [8].

Figure 2. Left: Original M0 layout requiring six cut masks. Center: Wire shifts and extension applied. Right: Self-aligned blocking applied, resulting in only two cut masks.

The extension and shifting of wires is effectively imposing a lower limit on wire length, allowing the minimization of cut mask cost, becoming two cut masks for either DUV or EUV case. Wire lengths going lower than this limit would entail two cut masks per etch material. Note that a single cut mask exposure using EUV is still at least 20% more expensive than two exposures using DUV [10-12]. Also, the cost of two EUV exposures for generating sub-40 nm pitch lines is more than 30% higher than that of SAQP with a single DUV immersion exposure [10,13].

For the longer lines on higher metal layers, like M2, the extra capacitance from extending the lines can be a concern [9]. An alternative to the cut approach may be letting the lines stagger with extended gaps between line ends (Figure 3) [9].

Figure 3. Left: M2 lines with assigned etch material in different colors. Center top: line extension applied for blue cut distribution. Center bottom: Without extension, an expanded block is used. Right: Expanded block for red cut.

The line end gaps are naturally filled by expanding the block patterns instead of extending the affected lines. Perhaps the final shapes of the expanded block patterns can be fine-tuned by computational lithography such as NVIDIA’s cuLitho.

Vias in Self-Aligned Blocking Scheme

As a third key development, the patterning of self-aligned vias [14] in the self-aligned blocking scheme should follow the splitting into two etch materials, and can also take advantage of the doubling of the etch mask pitch (Figure 4). This leads to two via lithography masks corresponding to the two etch materials.

Figure 4. Self-aligned via with self-aligned blocking. Left: Block mask (green) for red etch material. Center left: Via photoresist mask (gray) for red etch material. Center right: Partial etch for via (brown) in red etch material, and removal of via mask. Right: Removal of block mask, revealing previously patterned blue etch material and via.

What If…?

If the start of 7nm development happened after 2017, most likely DUV immersion lithography would have been used not with brute-force multipatterning but with self-aligned blocking and block redistribution / expansion. There would be a maximum of two cut masks per metal layer (with an additional two in worst case for M0) and two masks per via layer (with an additional two in worst case for V0), corresponding to the two etch materials.

Once in use, the 5nm and 3nm nodes would also have been covered. EUV development would of course still be continuing to keep pace, and perhaps the NA would have been increased earlier. It would have been an interesting alternative history but now, going forward, it appears only new semiconductor players at advanced nodes can exploit the full benefit of 20-20 hindsight.

References

[1] F. Chen, 2023 https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen

[2] F. Lazzarino et al., Proc. SPIE 10149, 1014908 (2017)

[3] A. Raley et al., Proc. SPIE 10149, 101490O (2017).

[4] Y. Chen, US Patent 9679771.

[5] W. Gao et al., Proc. SPIE 9426, 942606 (2015).

[6] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[7] Z. Xiao et al., Proc. SPIE 8880, 888017 (2013).

[8] S. Sakhare et al., Proc. SPIE 9427, 94270O (2015).

[9] W. Gillijns et al., Proc. SPIE 9427, 942709 (2015).

[10] L. Liebmann et al., Proc. SPIE 9427, 942702 (2015).

[11] S. Snyder et al., 2021 EUVL Workshop, https://www.euvlitho.com/2021/P2.pdf

[12] J. van Schoot et al., 2021 https://conference-indico.kek.jp/event/125/contributions/2304/attachments/1711/1951/Presentation_Jan_van_Schoot_et_al.ASML.pdf

[13] L-A. Ragnarsson et al., “The Environmental Impact of CMOS Logic Technologies,” 2022 EDTM.

[14] J-H. Franke et al., Proc. SPIE 10145, 1014529 (2017).

This article first appeared in LinkedIn Pulse: Self-Aligned Block Redistribution and Expansion for Improving Multipatterning Productivity

Also Read:

ASML- Soft revenues & Orders – But…China 49% – Memory Improving

TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production

Measuring Local EUV Resist Blur with Machine Learning

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How Secure-IC is Making the Cyber World a Safer Place

How Secure-IC is Making the Cyber World a Safer Place
by Mike Gianfagna on 04-23-2024 at 6:00 am
Categories: Secure-IC, Security

How Secure IC is Making the Cyber World a Safer Place

Securing the data and all the associated transactions that comprise our hyper-connected world is a daunting task. Security touches the hardware, software and all the channels connecting every device and every transaction. Threats can be embedded in software, hardware or systems can be compromised externally using a large array of active and passive technologies. The breadth of this problem can be overwhelming, and the coming maturity of quantum computers promises to make it a lot easier to break current state-of-the-art encryption. Fortunately, there is growing focus on holistic security and some companies are dedicated to this cause. Secure-IC is one such company that brings a wide array of technologies to bear on this problem. Recently, I had the opportunity to speak with a couple of veteran technologists at Secure-IC to explore some of the company’s capabilities and impact. Let’s explore how Secure-IC is making the cyber world a safer place.

An Overview

Secure-IC is a unique company that provides a wide range of hardware and software security technologies. The company also provides tools and services to analyze existing systems for potential security holes. As an introduction, you can learn about the company’s rugged security solutions here, and what Secure-IC is doing about the quantum computing threat here.

Stepping back a bit, the collection of hardware and software tools and technologies from Secure-IC are offered under the Securyzr™ brand. Capabilities to evaluate the robustness of a system are offered under the Laboryzr™ brand. Let’s explore each of these offerings through the eyes of my contacts at the company.

Securyzr

Brice Moreau

Brice Moreau is a Product Management Engineer at Secure-IC. He has been with the company for over 11 years. His focus for our discission was Securyzr. Brice began with an overview of the architecture of Secure-IC’s hardware, including the RISC processor, the various system interfaces, monitors, accelerators and memories. There are many dimensions to the technology, and I began to see how everything fits together.

Brice took me through a demo for the boot-up of a system, all the safeguards required, and a view of the data transactions monitored. In-system operation was then shown with many of the safeguards active. This includes sensing an externally driven temperature overload intended to put the system in a non-standard state. This event is logged, and appropriate action is taken. In this short demo, I got a feeling for the robustness of the Secure-IC solution. An overview of the wide range of applications supported was also provided, which paved the way for our next discission.

Next, Brice discussed the Securyzr S700 Series, which provides capabilities focused on security for the automotive market. Specific capabilities required for automotive applications were reviewed, along with a discussion of how these technologies can be embedded in ECUs in the vehicle, such as telematics, ADAS, gateway, control units, powertrain, V2X, and infotainment. Compliance with associated standards was also discussed.

Fleet management vie the cloud

After that, Brice discussed the Securyzr integrated Security Services Platform, describing how to implement secure device fleet management via the cloud.  The demonstration he provided illustrates the hardware and software required and how the interfaces and monitors are set up. How new devices are provisioned was also shown, as well as checking devices for overall health and managing exceptions.

Our discussion ended with an overview of the PQC Evaluation Kit. This product focuses on implementation of security in the Post-Quantum Cryptography (PQC) era. New algorithms to fortify security against quantum computing capabilities has been defined by the NIST and NSA. The evaluation kit contains the hardware and software required to prototype and test the new NSA algorithms against target system implementations. An important step toward making systems robust in the PQC era.

Brice concluded our discussion by commenting, “From fortifying automotive ECUs to managing device fleets securely in the cloud, Secure-IC’s Securyzr solutions can safeguard devices and networks against emerging threats and vulnerabilities.”

Laboryzr

Valentin Peltier

Valentin Peltier is a Cryptography Engineer at Secure-IC. He has been with the company for over 10 years. His focus for our discission was Laboryzr. Valentin began by discussing how Secure-IC helps its customers verify the robustness of systems with essentially a security evaluation laboratory.  He explained that while cryptographic algorithms are claimed mathematically impossible to attack, the implementation of those algorithms in a physical chip can open up the system to multiple threats, such as side-channel analysis, fault injection attacks, or hardware trojans injected during manufacturing.

First, he described how Laboryzr delivers hardware and software capabilities to analyze the robustness of hardware as it is designed and after it is manufactured. There are also tools to analyze the software that runs on the system, creating a complete view, right down to the line of code that may be causing a problem.

Digging a bit deeper, he discussed the Analyzr™ SCA for Reverse Engineering (SCARE). Here, methods of using side channel analysis to reverse engineer the target system (the memorable acronym SCARE) are used with a particular focus on the robustness of the all-important AES encryption. He detailed the hardware and software technology used to implement target system evaluation, including some unique sensor probes developed by Secure-IC.

Valentin concluded with a review of side-channel analysis on smartphone devices. Here, he presented the details of how to use side channel analysis on a cell phone to examine the robustness of the RSA algorithm. An electromagnetic probe is used to gain access to internal operations on the cell phone. The resultant data then goes through extensive analysis. The adage “you can run, but you can’t hide” came to mind during this part of our discussion.

Valentin concluded our discussion by commenting, “With Laboryzr, we offer a comprehensive solution for evaluating hardware and software security, providing our customers with insights from chip design to post-manufacturing analysis.”

To Learn More

My discussions with Brice and Valentin were quite useful and eye-opening. If security is on your mind, you can also reach out to Secure-IC to discuss your requirements here. And that’s how Secure-IC is making the cyber world a safer place.

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Not all Smartphones are Created Equal

Not all Smartphones are Created Equal
by admin on 04-22-2024 at 10:00 am
Categories: Semiconductor Services, TechInsights

TechnInsights Semiconductor Sustainability

TechInsights recognizes Earth Day 2024 by lifting the screen on smartphone semiconductor sustainability

Smartphones are typically compared based on screen size, processor speed, and camera resolution. But when TechInsights looked at carbon footprints for manufacturing just the semiconductors of three flagship phones, they found a 20% difference in carbon output. Multiply that against TechInsights’s forecast that 1.16 billion new smartphones will be shipped in 2024, and the difference in carbon emissions is similar to what you’d see from a passenger car circling the globe more than 46,000 times.

Semiconductor manufacturing is energy intensive and uses a variety of high Global Warming Potential (GWP) gases to create intricate circuitry patterns on silicon wafers. Yet, despite the growing importance of sustainability considerations to consumers, reviews of mobile phones typically focus on cameras, battery life, cellular connectivity, and overall performance, rather than carbon emissions associated with these mini-super computers.

That’s unfortunate, as not all semiconductor manufacturing processes are created equal when it comes to their impact on the environment. Greenhouse gas (GHG) emissions from semiconductor manufacturing can vary greatly depending on the technology process node being manufactured and the location of the wafer fab.

Whether you favor the a Samsung Galaxy, all smartphones have a sizeable lifecycle carbon emissions footprint, and approximately 80% may come from manufacturing. To better understand what emissions are associated with the manufacture of mobile phones, three processors used by Apple, Huawei, and Samsung in their most advanced phones were evaluated by TechInsights.

One of the most significant impacts on semiconductor carbon emissions is die size. When die size increases, the yields go down, and you end up with higher emissions per good die. Reviewing Scope 1 and Scope 2 emissions per wafer in terms of carbon dioxide equivalents, the Qualcomm SM8650-AB has the lowest emissions per wafer, followed by the A17 and Kirin 9000s. When emissions per die are evaluated, the trend reverses; the largest processor, the Qualcomm SM8650-AB, has the highest emissions per die, while the smallest processor, the Kirin 9000s, has the lowest total emissions.

Now compare the carbon emissions numbers and you can quickly find that there is a 20% difference in the carbon footprint for manufacturing just these three chips. That might not immediately sound like much, but the impact of one versus the other is equivalent to what the US EPA estimates as the carbon footprint of the average gas-powered passenger vehicle. Still not adding up to much? Multiply that against the 1.16 billion smartphones TechInsights forecasts will be shipped in 2024, and you’re looking at the equivalent of driving around the Earth 46,000 times.

Of course there are hundreds of semiconductors in smartphones which have their own carbon footprint. In this preliminary analysis, it was found that process node, fab location, and abatement efficiency have a strong impact on semiconductor emissions from manufacturing. However, die size had the most significant impact on the carbon intensity on the processors evaluated. An opportunity exists for Scope 2 emissions associated with the A17 and Qualcomm SM8650-AB to be significantly lowered by utilizing lower carbon electricity.

For more details and data pulled from TechInsights latest Semiconductor Manufacturing Carbon Model, read Analyst Lara Chamness’ Earth Day article: “A Tale of Three Phone Chips: Eco Version.”

About TechInsights’ Semiconductor Manufacturing Carbon Model
The TechInsights Semiconductor Manufacturing Carbon Model is the first of its kind to detail Scope 1 and Scope 2 carbon emissions at a wafer and die level. This is achieved by bringing together the equipment, processes, and manufacturing steps for Logic, DRAM, and NAND into a single tool for leading 300mm wafers produced by 184 total fabs. Updated in April 2024, the tool allows users to create their own unique analyses of carbon emissions through editable fields like utilization, abatement, and electric carbon intensity.

Also Read:

No! TSMC does not Make 90% of Advanced Silicon

ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability

IEDM 2023 – Imec CFET

IEDM 2023 – Modeling 300mm Wafer Fab Carbon Emissions

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Lifecycle Management, FuSa, Reliability and More for Automotive Electronics

Lifecycle Management, FuSa, Reliability and More for Automotive Electronics
by Bernard Murphy on 04-22-2024 at 6:00 am
Categories: AI, Analytics, Automotive, EDA, Synopsys

Lifecycle Management for Automotive Electronics min

Synopsys recently hosted an information rich-webinar, modestly titled “Improving Quality, FuSa, Reliability, and Security in Automotive Semiconductors”. I think they undersold the event; this was really about managing all of those things through the lifecycle of a car, in line with auto OEMs strategies for the future of the car. The standout message for me was total lifecycle management, from initial semiconductor architecture and design through end-of-lifecycle. I heartily recommend watching this webinar.

Heinz Wagensonner on an OEM perspective

Heinz is Manager of the Audi Progressive Semiconductor Program. He opened with a reminder of how an auto OEM sees the electronics future – advanced driving support, immersive experience and rethinking how to monetize added value options. One interesting set of stats is around mission profiles measured in hours of active operation over the car lifetime. For a traditional ICE car this has been 8000 hours (about 1.5 hours per day over a 15-year life). For an EV the mission profile extends to 55,000 hours, perhaps providing power to the house at night, and during the day charging or operating while supporting more functions than in earlier models. Heinz sees future EV profiles running to 130k hours, supporting multiple always-on functions such as face-id to enter and start the car, always on networks for OTA updates, and security to guard against threats.

Today advanced systems build on advanced processes (TSMC are already offering a 3nm early automotive development kit), very capable but with minimal track record in reliability (automakers used to require 5 years minimum). Domain specific devices with complex mission profiles compound the lack of track record. Mission profiles, advanced processes and advanced designs together point to a potential crisis for OEMs; an NHTSA report cites nearly 5 million ADAS-related recalls in 2022. At $1,000 per car, this is already a very expensive problem.

While mitigating the problem starts with strong design, Heinz also stresses in-service monitoring and compensation as an important part of the solution. On-chip sensors are central to these techniques. Such sensors play a role in preventive maintenance, perhaps warning the driver of an anticipated problem calling for a near term service visit. Or an imminent problem demanding the vehicle be switched to a safe state and the driver take immediate action (pull over to the side of the road).

Those features can prevent or mitigate a hazard in use before it happens. What happens when the car is taken in for a service? Heinz elaborated the highly complex and apparently quite brittle path to diagnose a root cause from initial service down through the value chain. As an example, 80% of ECUs assumed to be a problem root cause (and then replaced) prove on more detailed analysis not to have been the source of the problem! Yet following all diagnostic steps from initial service to a Tier 2 (semi supplier) can take 30 days if the root cause can be isolated. This overhead is unsustainable for managing warranty costs, potential for a recall, or worse.

He sees the path forward as a combination of on-chip sensor data, learning from prior problems through AI, combining in Signature Failure Analysis (SFA). Accumulating learned experience will lead to high confidence fixes which can be applied cost-effectively during a service call and can also provide effective and accurate feedback to Tier 1 and 2 suppliers. Some signatures may not map to a known problem and will still need to follow the long diagnostic path. However once resolved, they too can be added to the training database.

Alessandra Nardi on an EDA perspective

Alessandra is a Distinguished Architect in the Systems Solution group at Synopsys and a guru in automotive IMHO; every Alessandra talk I have attended has given me a better understanding of automotive system design and directions, with little to no product marketing. Her talk called for a holistic view of lifecycle challenges, starting with design then running through ramp, production, and in-field monitoring.

In-design optimizations for PPA and robustness are already well understood though still suggest opportunity for further advances. Here she highlighted need for improved modeling of uncertainty, through refined sensitivity analyses of variations based on different factors (voltage, temperature, etc) rather than blanket margins. Data gathered during ramp and production analyses through in-chip monitors placed during design will drive this learning. In turn that can drive yield and reliability optimizations and improvements to PPA, safety and other metrics. The same monitors can capture data during in-field analysis, feeding back information to the supply chain to drive additional optimizations while also enabling real-time tuning through techniques like adaptive voltage scaling.

The central component of in-chip monitor methods is a machine-learning system, gathering mission feedback from monitors to learn sensitivities/signatures for trends or outlier behaviors. In ramp or production these may suggest need for silicon or process revision fine-tuning. Similarly, an ML model can support in-field diagnoses and tuning.

Alessandra hinted that such lifetime optimization systems are not only important for automotive markets. Everything she and Heinz talked about is likely also important in aerospace and defense, industrial, medical and infrastructure markets though with different thresholds across the various metrics discussed in this webinar. I would imagine that even sustainability may play an increasing role, at least in product lifetimes and power consumption.

Fascinating discussion. Again, you can access the webinar HERE.

Also Read:

Early SoC Dynamic Power Analysis Needs Hardware Emulation

Synopsys Design IP for Modern SoCs and Multi-Die Systems

Synopsys Presents AI-Fueled Innovation at SNUG 2024

Podcast EP219: How Synopsys Addresses Debug and Coverage Closure Challenges with Robert Ruiz

Podcast EP219: How Synopsys Addresses Debug and Coverage Closure Challenges with Robert Ruiz
by Daniel Nenni on 04-19-2024 at 10:00 am

Dan is joined by Robert Ruiz, product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas Software, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing ASICs.

Robert talks about the rising verification challenges for debug and coverage closure for advanced designs with Dan. The time spent on these activities is rising, with data suggesting debug and coverage closure can occupy 75% of the verification cycle.

Robert describes several approaches from Synopsys that can provide a 10X – 60X improvement in productivity for these activities. New software tools, methodologies and the application of AI are all discussed along with an overview of the new UI for Verdi and how it impacts the process.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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ASML- Soft revenues & Orders – But…China 49% – Memory Improving

ASML- Soft revenues & Orders – But…China 49% – Memory Improving
by Robert Maire on 04-19-2024 at 8:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services
2 Comments

Fully assembled TWINSCAN EXE 5000

ASML- better EPS but weaker revenues- 2024 recovery on track
China jumps 10% to 49%- Memory looking better @59% of orders
Order lumpiness increases with ASP- EUV will be up-DUV down
“Passing Bottom” of what has been a long down cycle

Weak revenues & orders but OK EPS

Reported revenue was Euro5.3B and EPS of Euro3.11 versus expectations of Euro5.41B and EPS of Euro2.81.

Guidance was for revenues of between Euro5.7B and Euro6.2B versus street expectation of Euro6.49B.

While reported revenues were less than expected its obvious that Q2 outlook was more of a concern and significantly less than what was expected by the street.

A Lumpy business gets lumpier as ASPs increase

With High NA EUV systems costing many times the cost of an ArF tool, it should be no surprise that EUV and high NA EUV systems ordered or delivered in different quarters will cause significant variation in revenues and guidance. This is obviously exacerbated by the highly cyclical nature of the industry and fickle customers that can turn spending on or off very quickly.

In 2023 we saw some huge order numbers, way above expectations.

It would likely be better for investors to look at averaging orders and revenue over a longer time period.

At the very end of the day, the need for lithography systems is both increasing along with the average selling price.

We have covered ASML since working on its IPO in 1995 (almost 30 years!) and when we look back over the long term trend line of revenue, the story is quite amazing and not likely changing much going forward…

Memory will be up in 2024 and Logic will be down

There have been significant logic orders over the past year or more with very little memory business as memory had significant excess capacity. Going into 2024 we will see memory orders picking up as the memory industry continues to recover while we will go through a digestion period in Logic of all the equipment previously ordered and delivered.

Memory bookings jumped from 47% of orders to 59% in the quarter while logic dropped from 53% to 41%.

We have already heard from several memory makers that their overall Capex will start to recover in 2024. We would caution investors that while memory is getting better we still have strong supply and pricing is still a bit flakey.

High bandwidth memory will be a very bright point but investors still need to remember its only 5% of the overall memory market, although growing very quickly

China is up to 49% in revenues but down in actual amount

On face value 49% of revenue from China seems concerning but we would point out that this represents a smaller actual dollar amount than China’s peak business last year. China has increased as a percentage as the rest of the world has slowed more. The more interesting thing we would point out is that while China was 49%, the US was almost a rounding error at 6%, which continues to show how the US is being outspent by China by a huge margin. This is not something new but is a long term ongoing issue. It will be difficult for the US to catch up spending such a paltry amount.

2024 is second half weighted

Given the long lead times of equipment and production planning, ASML’s 2024 will be back end loaded. Overall we are still looking like 2024 will have similar business levels as 2023.

Essentially what we have is a U shaped curve with the end of 2023/beginning of 2024 being the bottom point of the somewhat symmetrical curve. While 2023 was logic dominated, 2024 will be more memory dominated

EUV will be up while DUV will be down in 2024

It should be no surprise that EUV will be up in 2024 as it is becoming the mainstay of lithography in the semiconductor industry.

Much as “G Line” and “I Line” lithography have become relics of the past that most current industry analysts have never heard of, so will DUV fade into history as EUV takes over.

We would point out that the wavelength to cost ratio of lithography systems is quite exponential when we compare the cost of G Line to I Line and DUV to EUV and finally High NA it is an exponential curve.

We wonder if a “Hyper NA” system could crack a Billion dollars?

Congratulations to Peter Wennink…Mr EUV

Peter Wennink, the CEO of ASML will retire after 10 years at the helm of the company. In our view he will clearly will be most remembered for navigating the company through the transition to EUV which was quite difficult and quite treacherous with many ups and downs. The final product is nothing short of amazing.

While Martin van den Brink was the technology visionary, Peter Wennink made it actually happen and turned ASML into the number one semiconductor equipment company in the world and the technology leader that is driving the industry creating many Billions of dollars in value.

The Stock

Investors will be disappointed with the weaker than expected revenues and the weaker outlook.

The stock looks to be down around 6-7% which we view as a bit of an over reaction and an opportunity for those investors with more of a longer term view past the lumpiness.

We remain positive on the stock and the story overall which has not changed.

We don’t see as much impact on other companies in the semiconductor space as ASML is a significantly different company with much longer lead times .

We expect most semiconductor equipment companies to be down in sympathy to ASML but we would remind investors that we have been saying for quite some time that the stocks had gotten way ahead of themselves with valuations that reflected a recovery that had already happened and quite strong.

The real reality is that we are at the beginning of a recovery that may not be as strong as expected and may take a while. As pointed out by ASML, we are just now passing the bottom of what we view as a “U” shaped downcycle and expect 2024 to be somewhat of a mirror to 2023 and not a significantly up year overall and stocks have to get in line with that thought.

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

ASML moving to U.S.- Nvidia to change name to AISi & acquire PSI Quantum

SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?

AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down

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Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!

Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!
by Eric Esteve on 04-19-2024 at 6:00 am
Categories: Arm, IP, IPnest, Semiconductor Services, Synopsys

Top10 Table 2023

Design IP revenues had achieved $7.04B in 2023, with disparity between license, growing by 14% and royalty decreasing by 6%, and main categories. Processor (CPU, DSP, GPU & ISP) slightly growing by 3.4% when Physical (SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless Interface) slightly decreasing (-1.4%) and Digital (System, Security and Misc. Digital) was slightly growing by 4%. Clearly, wired Interface is still driving Design IP growth with 16% to reach almost $2 billion in 2023 (after growth in the 20% during 2022, 2021 and 2020). IPnest has released the “Design IP Report” in April 2024, ranking IP vendors by category and by nature, license and royalty.

The main trend shaking the Design IP in 2023 is clear to detect in the Top 10, as IP vendors targeting consumer applications, like smartphone, shows decreasing revenues, when those enjoying interface IP products and targeting HPC and AI are growing. There is one exception and not the least, ARM is moderately growing by 5%. In fact, ARM has compensated declining royalty revenues dues to smartphone weakness by a remarkable performance in license revenues growing by 28.6%. After years spent in following phantom IoT market, ARM has realized in 2023 that the real source of growth (and profit) was with HPC and AI, and in a certain extend Automotive to eventually improve their positioning and portfolio. Also to be noticed is a strong increase at the end of 2023 from “revenues from related parties”, we can translate by “ARM China”…

If we look at the #2, #3 and #4, Synopsys, Cadence and Alphawave, the last is 100% focused on Interconnect IP when for Synopsys it’s 71%, and both are strongly growing (by 23% and 17% respectively) when Cadence growth is moderate with 9%. Ceva and Rambus are both declining, in both cases they have re-engineered their portfolio, and stopped supporting product line (Ceva) or sold it, like Rambus did with Interface PHY IP to Cadence.

I have written since more than 10 years in Semiwiki about the importance of PHY IP (“Don’t mess with SerDes”), and you could challenge my position. But remember that I always said, supporting advanced and competitive SerDes product line requires large and talented engineering team, unlike with digital controller IP, where only one excellent architect is needed, completed by young engineers.

In other words, supporting PHY IP requires a consequent investment and being able to support multiples foundries and technology nodes, which is the key condition for high return. Rambus took the decision to move their focus in pure digital (controller for interface protocols) and security.

Synopsys, Alphawave and Cadence growth confirm again in 2023 the importance of the wired interface IP category aligned with the data-centric application, hyper scalar, datacenter, networking or IA.

Looking at the 2016-2023 IP market evolution can bring interesting information about the main trends. Global IP market has grown by 106% when Top 3 vendors have seen unequal growth. The #1 ARM grew by 78% when the #2 Synopsys grew by 245% and Cadence (#3) by 231%. Market share information is even more significant. ARM move from 48.1% in 2016 to 41.8% in 2022 when Synopsys enjoy a growth from 13.1% to 22% and Cadence is passing from 3.4% to 5.6%.

This can be synthetized with the comparison of 2016 to 2023 CAGR:

  • ARM CAGR 8.6%
  • Synopsys CAGR 19.4%
  • Cadence CAGR 18.7%

When the global IP market has seen 2016 to 2022 CAGR of 10.8%.

The strong information is that the Design IP market has enjoyed 10.8% CAGR for 2016-2023! Zooming on the categories (Processor, wired Interface, Physical, Digital), market share 2017 to 2023 evolution clearly shows interface category growth (18% to 28%) at the expense of processor (CPU, DSP, GPU) declining from 58% to 47%. When Physical and Digital are almost stable.

 

IPnest has also calculated IP vendors ranking by License IP revenues:

Synopsys is the clear #1 by IP license revenues with 32% market share in 2023, when ARM is #2 with 29%. Alphawave, created in 2017, is now ranked #4 just behind Cadence, showing how high performance SerDes IP is essential for modern data-centric application and can allow building performant interconnect IP portfolio supporting growth from 0 to over $200 million in 6 years… Reminder: “Don’t mess with SerDes!”

With 6% YoY growth in 2023 when the semiconductor market has declined by 8%, the Design IP industry is simply confirming how incredibly healthy is this niche within the semiconductor market and the 2016 to 2023 CAGR of 10.8% is a good metric!

Eric Esteve from IPnest

To buy this report, or just discuss about IP, contact Eric Esteve (eric.esteve@ip-nest.com)

Also Read:

Semidynamics Shakes Up Embedded World 2024 with All-In-One AI IP to Power Nextgen AI Chips

Silicon Catalyst partners with Arm to launch the Arm Flexible Access for Startups Contest!

Synopsys Design IP for Modern SoCs and Multi-Die Systems

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ECO Demo Update from Easy-Logic

ECO Demo Update from Easy-Logic
by Daniel Payne on 04-18-2024 at 10:00 am
Categories: Easy-Logic, EDA

EasylogicECO Design Flow

I first met Jimmy Chen from Easy-Logic at #60DAC and wrote about their Engineering Change Order (ECO) tool in August 2023. Recently we had a Zoom call so that I could see a live demo of their EDA tool in action. Allen Guo, the AE Manager for Easy-Logic gave me an overview presentation of the company and some history to provide a bit of context.

The company started 10 years ago in Hong Kong by a professor and students, they even won an ICCAD competition for an ECO test case in China, a nice way to get noticed. Their approach addresses making an ECO in four different places:

  • Functional logic changes
  • Low power changes
  • Scan chain changes
  • Metal connection changes

The challenge is to make an ECO with the smallest impact in a design flow to save both time and money. With the EasylogicECO tool you can expect to see the smallest patch size with minimum user effort, getting results in hours not days. Here’s the flow for using their tool.

The tool compares two RTL netlists for differences, finds the modules with differences, and only modifies what is needed. By reading the entire design and only looking for what has changed enables EasylogicECO to be smarter than other ECO approaches, and there’s even formal checking of modules to ensure equivalence.

When making a Metal ECO there are lots of DFM and DRC rules to comply with, and EasylogicECO maintains logic levels in order to keep timing delays in place. There estimates to account for wire effects on delays, and the tool must pinpoint spare cells available to close timing and close routing. Users can run parallel ECO trials, then choose the best result. In the example below, versions 2 and 4 are better choices with the smallest patch sizes and smallest gate count changes.

I asked about the training time for an engineer to learn and become proficient at using EasylogicECO, and was surprised to hear that it only takes 30-40 minutes. Another question I had was about competition with other ECO tools, and they showed me a slide with multiple test cases that compared the patch size, where smaller is always better.

A smaller patch size greatly helps a project team to minimize the layers that need to be changed in metal, directly impacting the cost of mask rework. Each metal layer can cost in the millions for advanced nodes, so it’s important to use the minimum metal layers.

With other ECO tools a team has to add more spare resources to enable metal ECOs, which in turn causes a larger die size and higher silicon costs.

Demo

EasylogicECO is a batch tool run at the command line in a Unix environment. The first step is to generate script templates, then go to the scripts folder and decide which ECO script to run, and there are Readme files to explain the syntax and usage. Running each script will prompt the user for input files, like: Original RTL, revised RTL, module name, etc.

The demo test case took about one minute, running on a laptop computer. The script prompted for Verilog file names, module top, LEF file, DEF file, spare module name for metal ECO, spare cell naming and spare instance names. It then created scripts ready for logic synthesis and back-end tools like Innovus and ICC2.

Summary

All SoC projects experience last-minute changes which are threats to taping out on time and within budget.  Finding bugs in silicon that require another spin will be expensive, so anything that can make this process go faster and cost less is welcomed. If your ECO process is taking weeks or months, then it’s high time to consider a newer approach to save valuable time and money.

Consider an evaluation of EasylogicECO and compare their approach with your previous methods to find out how much quicker an ECO can be done. Their ECO flow works with Cadence and Synopsys tools, so there’s no need for a CAD team to integrate anything as you can get patch results in just hours. Stay tuned for an upcoming webinar and if you’re attending #61DAC in June, then stop by their booth to get all your questions answered in person.

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Cadence Debuts Dynamic Duo III with a Basket of Goodies

Cadence Debuts Dynamic Duo III with a Basket of Goodies
by Bernard Murphy on 04-18-2024 at 6:00 am
Categories: 5G, Cadence, EDA

Dynamic Duo III min

I am a fan of product releases which bundle together multiple high-value advances. That approach reduces the frequency of releases (no bad thing) in exchange for more to offer per release, better proven through solid partner validation. The Dynamic Duo III release falls in this class, offering improvements in performance, capacity, and solution support across this matched set of hardware-assisted verification engines (Palladium for emulation and Protium for prototyping).

Capacity and performance advances

It’s a very worn marketing cliché but still true that design sizes keep growing hence the tools to support verification must continue to grow with them. The new generation Palladium Z3 and Protium X3 systems have increased total supported capacity, to 48 billion usable gates and each offer a 50% boost in performance. The Palladium platform is based on a new generation of the Cadence custom emulation processor and the Protium platform is based on the recently released AMD VP1902 device.

Compile times have improved dramatically on large designs through a new modular compiler, delivering near constant compile times independent of design size. For Palladium this maxes out at 8 hours per compile, making 1-2 verification turns per day a reality in early-stage system verification runs. Protium compile times have also dropped, to under 24 hours, speeding prototyping turns in late-stage hardware/firmware validation. Naturally the signature tight coupling between platforms continues with Z3 and X3, allowing for example a run exhibiting a bug in X3 prototyping to be flipped over to Z3 emulation for detailed debug drill-down.

Both platforms continue to deliver form factor and power optimization suitable to enterprise resources, allowing for maximum utilization whether verifying IP, subsystem/chiplet, or full system scale while packing as many jobs as will fit into available resource given job sizes. Both are also available as cloud-based resources.

Since Nvidia has been a long-time fan, I have to believe hardware development for LLMs is among leading drivers motivating these improvements.

Solution apps

Bigger and faster are always important but what really caught my attention in this release are the apps. First, Cadence have spun a new power estimation/analysis app (DPA 3.0), claiming 95% accuracy compared to implementation-level static power analysis (the pre-silicon power signoff of record). Not a new capability of course but sounds like it is much improved and of course running on a platform which can run very big designs with serious use-cases, always important when teasing out power bugs in big systems.

The 4-state emulation app is particularly interesting. Samsung presented a paper at DVCon this year on how they use this capability (currently unique to Palladium apparently) for low power debug. As an example, when switching power states, there are numerous opportunities for bugs to arise around incorrectly enabled isolation logic. X-propagation tests are a good way to catch such bugs but classic X-prop verification using simulation or formal is limited to relatively small design and test sizes. Emulation has the necessary capacity and speed but has historically only supported 0/1 modeling. Now Palladium Z3 also supports 0/1/X/Z as an option, making X-prop testing a very real option on big designs and tests. Samsung were able to show 100X performance improvement in this analysis over a simulation-based equivalent.

In mixed signal emulation, ADI presented an award-winning poster at the same DVCon on their use of the new Palladium app for digital mixed signal (DMS). I believe DMS emulation will become a must-have for 5G, 6G and beyond, to verify correctness between RF and digital stages as software-dependent coupling between stages increases. ADI say their testing shows the methodology is ready for production use, with some limitations and workarounds. Not surprising when forging a new frontier.

The Palladium safety app brings fault simulation to emulation – now we can talk about fault emulation 😀. Michael Young (Sr. Product Management Group Director, Cadence) tells me that speedup versus heavily parallelized software-based fault sim is typically 10-100X. He adds that a common use model is to do most of the relatively short sims using the software platform and to port longer analyses (1 hour or more) to the emulator. The Xcelium safety app and the Palladium share the same fault campaign model so switching between platforms should be simple.

Good fundamentals and good new features in this release. You can read more HERE.

Also Read:

Fault Simulation for AI Safety. Innovation in Verification

Challenge and Response Automotive Keynote at DVCon

Automotive Electronics Trends are Shaping System Design Constraints