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Analog Design Verification — Traceability is Required

Analog Design Verification — Traceability is Required
by Tom Dillinger on 04-05-2016 at 9:45 am

Digital verification engineers have developed robust, thorough metrics for evaluating design coverage. Numerous tools are available to evaluate testbenches against RTL model descriptions — e.g., confirming that simulation regressions exhaustively exercise signal toggles, RTL statement lines, individual statement sub-expressions, individual conditional paths in a case or if/then/else construct, etc. Hardware description language standards have evolved to include (non-functional) statement definitions that allow verification engineers to add specific, complex measurement tests — e.g., asserts, covergroups.

Digital verification teams have also often deployed methods to track coverage progress throughout the design cycle, to identify areas in the overall design where additional (directed or biased-random) testcases need to be written and added to the verification suite. Increasingly, formal model property verification methods are also being applied to augment coverage. Upon evaluation of this coverage “dashboard”, the verification team lead can signoff for tapeout with high confidence.

To date, the verification of analog IP functionality to specification has typically been much less structured, with various ad hoc methods developed to assess the overall quality of the simulation strategy:

  • specification documentation and testplan reviews
  • schematic and layout reviews, with testcase simulation waveforms
  • signoff documentation reviews

Just what every engineer looks forward to — more meetings. 🙁

Realistically, it is extremely difficult to apply metrics to reflect how the design of analog components and parasitics affect circuit behavior. Nevertheless, a more structured methodology for analog IP verification is definitely needed. This necessity is further advanced by the imposition of quality standard by various organizations, which define requirements for product release information — e.g., ISO 26262 for automotive market products.

To help address this issue, Cadence is announcing a major update to their popular Analog Design Environment (ADE) platform.

I had the opportunity to get a preview of the extensive verification features added to the new ADE product family from Steve Lewis, Product Marketing Director, Custom IC and Packaging Group.

Steve began by highlighting, “This is a new platform, consisting of ADE Explorer, Assembler, and Verifier. The focus is to enable advancements in analog verification methodologies. We will still be maintaining the existing ADE L/XL/GXL products — yet, we anticipate designers will eagerly want to adopt the capabilities of these new applications.”

The following figure illustrates the high-level focus of this announcement, using the ISO 26262 automotive quality standard as an example. The key bullet in this figure is“Traceability”.


Briefly, traceability implies that the product release must include documentation recording:

  • what tests were run
  • what environmental conditions were used
  • the link between tests and design specifications
  • what ran the tests, and when
  • demonstrated success that the design specification was met by all related tests

Ad hoc verification methods to capturing and maintaining this information will not scale with the complexity of analog IP currently in development.

Steve described the new ADE products in some detail, using the diagram appended below:


ADE Explorer
Explorer is the day-to-day environment that the design engineer will typically use. Cadence re-allocated some capabilities from the existing ADE family into the base Explorer feature, recognizing that the advanced features of ADE L/XL/GXL are now de rigueur for all designers — e.g., Monte Carlo simulation support, sensitivity analysis.

Significant usability features for faster iterative design closure were added, as well. For example, the figure below highlights thedesign tuning panel in Explorer, which facilitates rapid updates to schematic and environment parameters dispatched to Spectre or Virtuoso AMS Designer for simulation. Waveform balloons annotated to the schematic show comparative results, to more quickly iterate on design optimizations.


The key is that the simulation test results are maintained by Explorer in a model view used by ADE Assembler and Verifier.

ADE Assembler
Steve associated the Assembler feature with prevalent use by the “block-level” verification team. Complex verification plans can be represented visually, as illustrated in the figure below. Conditional and interdependent testcase relationships (“run plans”) can be identified — for example, one set of test results are to be used in the next testbench set. Using the new ADE Variation feature, the verification team can apply high-sigma statistical, optimized Monte Carlo simulation tests.


ADE Verifier
The verification plan originates and comes together with ADE Verified, an encompassing application that is used throughout the design cycle. Initially, as illustrated below, the correlation between design specification and testcase plan is established, a key facet to the traceability requirements of the product release standards.


During the design, Verifier provides the overall dashboard data that verification project managers will use, as depicted in the figure above.

As the design approaches signoff, Verification can also serve as the batch simulation regression test manager, as well.

Configuration Management
I asked Steve, “These ADE features look great, but they are clearly very dependent upon the configuration and version data management (DM) policies used during design. How is that handled?”

He replied,“Seamlessly. These new ADE features work directly with existing DM tools that ADE teams are using. These features utilize a new model view — maestro — that records and maintains all the traceability information required. The OA data model for the traditional Virtuoso views remains unchanged — e.g., schematic, layout, symbol views. The maestro view is added to the design database for the new Explorer/Assembler/Verifier features. We worked closely with the DM software tool providers to optimize the maestro view for performance. Existing ADE L/XL/GXL products are easily imported into the new ADE features, and the maestro view data accumulated.”

More robust analog IP verification methodologies are needed, to assist with increased IP complexity and the requirements for standards traceability. Yet, to gain rapid deployment, these approaches much be evolutionary, building upon existing tools and interfaces, providing usability features that are intuitive to analog designers and verification teams. With the new capabilities added to ADE — Explorer, Assembler, and Verifier — Cadence has enabled this rigorous transition to be quickly and easily adopted.

For more information on the new ADE product family, and the new Virtuoso product announcement, please follow this link.

-chipguy


Path FX – the Production Proven Answer to Static Timing Analysis with Variation

Path FX – the Production Proven Answer to Static Timing Analysis with Variation
by Isadore Katz on 04-05-2016 at 7:00 am

I want to compliment ChipGuy on a very nice write-up of a complex topic – how to model process variation in static timing.

Continue reading “Path FX – the Production Proven Answer to Static Timing Analysis with Variation”


Optimizing memory scheduling at integration-level

Optimizing memory scheduling at integration-level
by Don Dingee on 04-04-2016 at 4:00 pm

In our previous post on SoC memory resource planning, we shared 4 goals for a solution: optimize utilization and QoS, balance traffic across consumers and channels, eliminate performance loss from ordering dependencies, and analyze and understand tradeoffs. Let’s look at details on how Sonics is achieving this. Continue reading “Optimizing memory scheduling at integration-level”


IoT + Big Data + Cloud + AI Integration Insights from Patents

IoT + Big Data + Cloud + AI Integration Insights from Patents
by Alex G. Lee on 04-04-2016 at 12:00 pm

IoT Big Data Aggregation
US20140297826 illustrates a system for big data aggregation in a sensor network. The most important part of the Internet of Things (IoT) big data analytics is collecting data before storing the data. The Hadoop big data platform supports collecting data in Hadoop Distributed File System (HDFS). HDFS is an open source for storing big data dispersedly, that is, a technology for storing collected data reliably. The big data aggregation system includes a sensor network which comprises many sensor nodes connected to each other over a wired/wireless network and is configured to transfer sensor data generated by each of sensor nodes to a big data management unit by setting a destination address in the sensor data as an address of a big data management unit. The big data management unit configured to distribute and dispersedly store the sensor data based on the set destination address of the sensor data.
IoT Big Data Platform
The Hadoop big data platform is based on the MapReduce framework. US7650331 describes the MapReduce framework. US20110313973 illustrates the MapReduce framework including the shuffle function using the DFS. US20150012502 illustrates a big data central intelligence system for managing, analyzing, and maintaining large scale, connected information systems such as the IoT device networks.

IoT Big Data Real Time Processing

US20150134704 illustrates a system for processing large scale unstructured data in real time. The interconnected IoT sensing devices continuously generate massive information at a very high speed. Thus a technology for effectively processing a huge amount of information in the form of a data stream in real time is very important. The real time big data analysis system includes a receiver for receiving streamed input data from live data sources, a pattern generator for deriving emergent patterns in data subsets, a pattern identifier for identifying a repeating pattern and corresponding data subset within the emergent patterns, a compressor for reducing the identified data subset and identified pattern to a compressed signature and a repository for storing the streamed input data with the compressed signature and without the identified data subset in which the data subset can be rebuilt if necessary using the compressed signature.

IoT Big Data Cloud

US20130227569 illustrates the system that can gather data from thousands of the IoT sensors/devices and analyze the data in the cloud without the massive amount of investment in the server and big data analytics infrastructure. The cloud based IoT big data system provides a virtual IoT sensors/devices cloud as an Infrastructure as a Service (IaaS) and a service cloud as a Software as a Service (SaaS), to provide a flexible and scalable system. The IaaS provides flexibility by handling heterogeneous IoT sensors/devices. The SaaS provides scalability by relieving end users of computational overheads, and enabling on-demand sharing of IoT sensors/devices data to requesting end users. The SaaS also relieves end users from specifying IoT sensors/devices characteristics, locating physical IoT sensors/devices, and provisioning for the physical IoT sensors/devices. The end user, via a device (e.g., smartphone), requests and receives services provided by the system.

IoT Big Data Analytics

US20150179079 illustrates a system and for real time monitoring a patient’s cognitive and motor response to a stimulus. The big data analysis of massive data obtained by the IoT healthcare/medical devices can provide many value-added healthcare services. US20150186972 illustrate a big data analytics system for the business IoT applications. The business IoT devices can collects a large amount of data regarding products, product attributes, prices, and price attributes. To be understood by a person, this large amount of data and analytic output must be summarized, personalized, and organized in relevant terms. The summarization and personalization of such a large and complex set of data presents challenges in the selection and refinement of information as well as with respect to identification of patterns and arrangement of information in a user interface. The big data analytics system provides a user interface to summarize and personalize a large amount of price and product information, to identify patterns therein, and to generate recommendations in relation to the information.

Artificial Intelligence for IoT

Artificial Intelligence (AI) is essential to provide value added IoT services by finding the patterns, correlations and anomalies in user behaviors for autonomous context-aware actions of the IoT system surrounding the user. US20150039105 illustrates the smart home intelligence system to fulfill the special needs of each family member exploiting AI. US20140073486 illustrates a heart rate monitoring system by providing the best type of sensor to use at a given time determined by AI based on the level of motion (e.g., via an accelerometer) and whether the user is asleep (e.g., based on movement input, skin temperature and heart rate). US20140108307 illustrates the AI exploitation in the connected car applications. Base on the profile information and/or contextual information, AI system provides suggestions to the driver. US20140340236 illustrates the AI application for securing the distributed power distribution networks in the IoT smart grids.

IoT+ Big Data + Cloud + AI Integration

US20150227118 illustrates the IoT Cloud Big Data AI system for facilitating automatic control of the smart home devices based on past device behavior, current device events, sensor data, and server-sourced data. Cloud-based big data analytics is accessible via a server system for analyzing data associated with persons or buildings in a geographic region about the building, such as local news and weather information and data pertaining to appliances within the geographic region, such as a neighborhood, zip code, and so on. The analyzed data is used to develop the control rules to control smart home devices automatically.

The automatic control of the smart home devices enable various benefits, such as triggering lights to automatically turn on when a user enters a particular room at a particular time; activating a sprinkler system when server-side data indicates that a fire is nearby; automatically turning on a heater in advance of a home owner’s return at a particular time when the home temperature is below a predetermined level; turning off a sound system and lights in various rooms after data indicates that a user is preparing to sleep; turning off lower priority devices that may conflict with higher priority devices, and so on.

Cloud-based big data analytics also can be used to make a prediction about the future device usage and/or device behavior and/or user behavior exploiting AI. The device usage and/or device behavior and/or user behavior predictions can be used to generate control rules. The prediction can be derived by comparing collected data with a sample table of data to determine whether a correlation exists between the collected data and data in the sample table of data. The prediction can be generated based on a correlation between the collected data and data in the sample table of data. The prediction also can be based on a frequency of occurrence of an instance of data in the collected data (and timing information associated with occurrences of the instances of data) to generate a probability estimate. The probability estimate is employed to determine the prediction.


PCB Design Requires Both Speed and Accuracy of SI/PI Analysis

PCB Design Requires Both Speed and Accuracy of SI/PI Analysis
by Tom Dillinger on 04-04-2016 at 8:00 am

The prevailing industry trends are clear: (1) PCB and die package designs are becoming more complex, across both mobile and high-performance applications; (2) communication interface performance between chips (and their related protocols) is increasingly demanding to verify; (3) signal integrity and power integrity issues are more intricate (e.g., the impact of power distribution noise on nearby signal integrity); and significantly, (4) the design resources with detailed SI and PI expertise are very limited. Project schedules are often adversely impacted by both the available bandwidth of the SI/PI specialists and the long iterative loop between board design, model extraction, SI simulation, and feedback to the physical designers.

The industry requires an integrated design environment, where SI/PI analysis can be launched easily, run quickly, and provide accurate results back to the designer. Although perhaps obvious, the same fast/accurate requirement applies to design rule checking for manufacturability and EMI/EMC compliance.

I recently had the opportunity to speak with Dave Wiens, Business Development Manager, and Dave Kohlmeier, HyperLynx Product Line Director, at Mentor Graphics, on how the HyperLynx development team is addressing these challenges. Indeed, they were excited to convey features in the latest HyperLynx release that offers a significant productivity boost to designers. Here are some of the highlights of our discussion.

Performance
Signal integrity verification consists of setup, simulation runtime, and post-results analysis. Setup involves generation of models (e.g., S-parameters for non-uniform 3D regions) for SI simulation, and is often a time-consuming step.

For this release, the HyperLynx team incorporated unique features to accelerate tool performance — i.e., advanced pattern matching, and cross-section caching — as depicted in the figure below:

The result is that (thousands of) cached structures enable extensive reuse during model build. Performance is further improved through multi-threaded execution.

And, a key feature is the automatic definition of sections of the design model to be directed to specific integrated solvers — e.g., structures that require 3D full-wave analysis are identified and detailed models generated. The judicious application of 2.5D and 3D engines to their respective geometries improves setup performance dramatically.

The tool environment also includes the familiar HyperLynx design wizards. In Dave K.’s words, “The wizards embed domain knowledge to conduct a small interview with the designer to identify model details for analysis, such as the DDRx Wizards. These applications provide both an easy-to-understand design reference, and an overall boost to post-results analysis productivity.”

Accuracy
Performance improvements would be of little value, if model simulation accuracy is compromised.

As mentioned above, 3D full wave field solver methods are applied to appropriate structures, such as differential vias. The ports introduced by this model partitioning are managed automatically, when re-constructing the full model. Full-wave solvers utilize excitation sources and reference planes to analyze the structure, for calculation of EM fields. As these sources/planes do not represent the exact field profile at the ports, there is a source of error. Calibration “de-embedding” of port discontinuity errors from this partitioning is crucial to model accuracy, and is also automatic.

Resulting Touchstone S-parameter files — with potentially very many ports — are analyzed for quality (e.g., passivity, causality, reciprocity). The Touchstone Viewer also provide visual feedback of model characteristics, such as insertion loss deviation, return loss, insertion loss to crosstalk ratio, etc.

Algorithmic support is included for the most advanced trace surface roughness and frequency-dependent dielectric models.

Optimum geometrical meshing of the structures also ensures the appropriate accuracy/runtime tradeoff.

HyperLynx supports the recent power-aware IBIS model standard, to accurately reflect the impact on signal integrity due to coupling through the power distribution network (PDN) — e.g., simultaneous switching noise on a parallel interface, and via-to-via coupling through the PDN.

HyperLynx performance and accuracy are industry-leading for analysis of DC drop in the PDN, and calculation of the PDN frequency-dependent impedance.

In addition, the latest Hyperlynx release environment includes a new capability for advanced SerDes signal integrity analysis.

An emerging approach to validation of channel performance is the Channel Operating Margin, or COM, calculation. (This is the de facto analysis methodology for the 100 Gigabit Ethernet standard.) For SerDes protocols that support the COM method, such as 100GbE, simulation support is provided in HyperLynx to generate the channel pass/fail margin result.

Mentor has been a leading proponent on the definition of COM measurement techniques — for more information on COM and recent recommendations for improving the accuracy of COM simulation to BER measurement, please refer to the following article.

In addition to the SI/PI features mentioned above, HyperLynx DRC performs PCB full-board design rules checks, detecting both irregular physical topologies and EMI/EMC structures of concern, such as interrupted signal return paths.

Usability
HyperLynx is an integrated suite of analysis applications, available in a single user environment, with a unified data model.

Both Dave K. and Dave W. emphasized that the HyperLynx team has focused on usability (and a quick learning ramp), while not compromising accuracy. The theme of our discussion was “the fastest time to accurate results”.

I think these guys are on to something. From an overall project perspective, the SI/PI specialists in the organization are inevitably stretched thin, often supporting multiple board and package designs. An integrated environment for physical designers, with performance optimizations to speed closure while maintaining highest accuracy, is definitely needed.

For more general information on HyperLynx, please follow this link.

-chipguy


CMOS Radio Frequency Image Sensor Process

CMOS Radio Frequency Image Sensor Process
by Students@olemiss.edu on 04-03-2016 at 4:00 pm

Image censoring with radio frequency (RF) in CMOS is a combination of light sensing chips and wireless communication. Typically, we were first engaged in the article, “RF Design Issues and Challenges in a CMOS Image Sensor Process”, because of the circuit design process required to make a functioning Radio Frequency transceiver. Radio Frequency transceivers are electronic devices that receive and demodulate radio frequency signals, and then modulate and transmit new signals. By using these radio frequency signals, it is a way to limit local interference and noise. We thought it would be an interesting concept to grasp for our future benefit if we decide, design and implement these communication devices into CMOS Image Sensors or CIS.

The first type of CMOS pixel circuits created were called passive pixels. They had good fill factors but suffered from very poor signal to noise performance. [2] Modern CMOS designs mostly use active pixels, which put an amplifier in each pixel, typically constructed with three transistors. [2] The more transistors added to CMOS Image Sensor designs the less noise interference, which is a good thing especially for the CIS with RF since the RF will produce noise interferences.

CIS is a relatively simple circuit that involves Photodetectors, these are very light sensitive, when activated they take in how much light each one is being exposed to and stores it by collecting these readings into pixels. Typically, each circuit would form four pixels; two green, one blue, one red. These sensors individual circuits are expanded until a resolution pixel size is met. CIS is very popular among many devices these days for many reasons, the biggest is perhaps how easy they are to produce which makes them cheap. What makes CIS so cheap is there are many manufacturers making CMOS chips at very affordable prices, the other option for digital image capturing is CCD, Charge Coupled Device.

CCD is cheaper to make individually when compared to CMOS but at large scale the CMOS CIS prove to be much cheaper thanks to the large number of foundries that produce various CMOS circuits. Furthermore, other than being very economically efficient they are capable to be very smart. What gives them the capability to be smart is that since the circuit is almost entirely CMOS, calculations can be made without an intense data path and processor carrying out corrections on each individual CIS circuit, the image can be corrected on each individual pixel and then passed on which is beneficial for many reasons such as; low processing consumption, more accurate pixel correction, and quicker image processing.

The article selected makes some notable points relatable to what we have already talked about in class. The circuit being described is 0.18um, in class the transistors are sized at 0.22um. The 0.22um size used in class, for at least a few examples, were never defined as the standard that needed to be used. It is impressive that the circuits designed in the article are that small, furthermore, the circuits in class are strictly transistors but here inductors were involved in the LVS. This is interesting because lecture gave the impression the CMOS would be a circuit and the components, such as the inductors in this article, would be two separate portions. This is not how the circuit is designed, however, the foundry needed to put inductors in the CMOS portion.

This demonstrates that if this same circuit from the article had an issue of overheating and it needed to be monitored constantly then a simple thermistor could be included at the foundry and a CMOS RF Image sensor processing with self-monitoring temperature would be made. Another point this article related to class was that, in class everything is about achieving maximum efficiency from the circuits. An interesting thing here is they have two goals; Wirelessly Communicate and Detect light for the Photodetectors. If they focus on the Photodetectors running as efficiently as possible then the inductors will either not perform or perform poorly, so instead they added a fifth metal at a thickness of 2um at the foundry so that the inductor performs at its absolute best, assuring the wireless communication is solid. In the process of gaining maximum performance for wireless communication, the transistors will have a smaller dopant level thus limiting their performance to lower than what it could have been.

The article extensively mentions one of topics from the CMOS class and that is the idea of power distribution and noise in these circuits. It is always an innovative idea to be able to control the amount of power that is consumed and not carelessly drain it. Hence, you must be able to put into prospective the Energy and Power equations. To find energy, the first thing that needs to happen is define the Instantaneous Power. Instantaneous Power is found by P(t) =I(t)V(t).

Energy is the rate of power consumption, and is defined by equation (1) listed below. Average power is the energy consumed by a circuit over a given period time. It can be found using the equation (2) listed below. The article mentions the chips must be low power due to the small die size. If the chip already has minimal power and is also receiving radio frequencies, that are at extraordinarily high frequencies, it seems that the level of noise in the chip would become a major issue, perhaps severe enough to hamper its communication capability or the behavior of the transistors. Capacitors are always a good source to reduce the amount of noise interference when dealing with AC circuits. Granted the diagram shows a capacitor which filters noise when it leads to ground, this capacitor doesn’t directly lead to ground.

The article mentions the chips must be low power due to the small die size. If the chip already has minimal power and is also receiving radio frequencies that are at extraordinarily high frequencies, it seems that the level of noise in the chip would become a major issue, perhaps severe enough to hamper its communication capability or the behavior of the transistors. Capacitors are always a good source to reduce the amount of noise interference when dealing with AC circuits.

Granted the diagram shows a capacitor which filters noise when it leads to ground, this capacitor doesn’t directly lead to ground. These topics bring up the famous topic of CCD vs. CMOS. Both sensors were created around the same time, but CCD was preferred at the beginning. CMOS required smaller features that could not be attained at the time and CCD operated at a faster speeds. Later, better technology was created to implement CMOS sensors. It was also realized that CCD sensors have higher bandwidth and more noise.

“Students in The University of Mississippi Electrical Engineering’s Digital CMOS/VLSI Design course researched a contemporary issue and wrote a blog article about their findings for presentation on SemiWiki. Your feedback is greatly appreciated.”

References:
[1] L. Truong, D. Zhang, T. Leitner, and B. Mansoorian, “RF Design Issues and Challenges in a CMOS Image Sensor Process,” Image Sensors. [Online]. Available at: http://www.imagesensors.org/past workshops/2013 workshop/2013 papers/07-09_069-truong_paper.pdf. [Accessed: 11-Mar-2016].

[2]“CMOS Fundamentals,” CMOS Fundamentals. [Online]. Available at: http://www.siliconimaging.com/cmos_fundamentals.htm. [Accessed: 11-Mar-2016].

[3] Matthew Morrison. (2016, March 1). CMOS/VLSI-Lecture 11 [Online]. Available at:
https://www.youtube.com/watch?v=V4pvT8FjXEA [Accessed: 11-Mar-2016].

[4]“Teledyne DALSA – A Teledyne Technologies Company,” CCD vs. CMOS. [Online]. Available at: https://www.teledynedalsa.com/imaging/knowledge-center/appnotes/ccd-vs-cmos/. [Accessed: 11-Mar-2016].

[5]“Theory & Definitions,” Voltage, Current, Power & Energy: Definitions. [Online]. Available at: http://meettechniek.info/measurement/theory-definitions.html. [Accessed: 11-Mar-2016].

[6]Mattias Myrman, “De-aggregating and dispersing dry medicament powder into air,” [Online]. U.S. Patent WO 2003086517 A1, October 23, 2003. [Accessed: 11-Mar-2016].


IoT Prototyping Workshop in Monterey CA!

IoT Prototyping Workshop in Monterey CA!
by Daniel Nenni on 04-03-2016 at 12:00 pm

With the coming onslaught of IoT designs from big companies and small, the opportunity for IoT FPGA prototyping deserves a closer look. This session will start off with a keynote “The Internet of Trust and a New Frontier For Exploration” and will be followed by a discussion with industry experts Don Dingee, Frank Schirrmeister, Tom De Schutter, and Toshio Namamo. Frank was kind enough to offer his perspective to open the conversation.

The discussion about the Internet of Things (IoT) and its potential almost always makes me smile think of one of my favorite technology quotes. Science fiction author William Gibson once said that “the future is already here – it’s just not very evenly distributed”. It seems that I am at the early adoption curve because for me the IoT has become part of daily life.

When I wake up my sleep tracker informs we of my sleep score – how long did I sleep, how many deep sleep cycles did I have, how long did it take me to fall asleep and how much snoring did occur last night. It does so by way of a tracker under my sheet (the “thing”), connected to my phone (“the hub”), interacting with the cloud comparing all this to a set of representative previous nights. Then another tracker, always at my wrist, counts my morning workout calories and steps during the day. Just like my sleep tracker, it helps me with health aspects. By the time I dropped my daughter at school and arrived at work, my car has become “the thing” delivering via my phone (“the hub”) my movement to Google/Waze servers (“the cloud”) tracking traffic indirectly and helping me with my optimal path through traffic.

So for me the future of IoT is already here, part of my daily life. At EDPS in Monterey we will talk about prototyping for the age of the IoT. To me the common defining characteristics of the IoT from my examples above include:

  • A connected system of things, hubs, networking and cloud for data processing poses classic system design problems: What are my channel latencies? How much compute power is needed? What bandwidth do my channels have to support?
  • Value being derived across the chain from the “overall system”. Take out a component and it will break down, the value to the end user goes away.
  • “Things” are plentiful and of heavily varying complexity – from wearables through watches and fitness trackers to even cars (although one could argue that the thing for Waze is the phone in the car). The “things” need advanced sensors to pick up all the activities users do, implying needs for analog/mixed signal integration as well as low power given that trackers need to run for days at a time at least.
  • Protocols for communication, networking from and to the hubs in the IoT as well as the compute needs to be carefully verified, all in the context of software.

Looking at the four characteristics above, prototyping will take a central role in the development for applications in the IoT, of course as part of an overall set of connected engines from virtual through RTL simulation, acceleration, emulation, prototyping and even the real silicon. Prototyping allows users to make sure the system of things, hubs, networks and servers interacts correctly and is configured appropriately. It will allow to show the overall system value to make business decisions and prototype what valuable data end users can derive from IoT applications. Prototyping will allow to verify algorithms, protocols and interactions between the digital and analog worlds, and last not least will enable software development of varying complexities, from real time software control software in the “things” to middleware and OS validation in hubs and servers, and of course up to the actual applications that are presented to the end users.

The IoT is most certainly here but not evenly distributed yet. Prototyping will play a key role for its development. Come join the discussion at the EDPS in Monterey on April 21[SUP]st[/SUP]. Use the discount code SemiWiki-EDPS2016 for $50 off.

Also Read: IoT Workshop in Beautiful Monterey California!


How my 17 year old daughter will drive Silicon Photonics into the Mainstream

How my 17 year old daughter will drive Silicon Photonics into the Mainstream
by Mitch Heins on 04-03-2016 at 7:00 am

I read with interest a recent article in the San Jose Mercury News (Live Video) about how the availability of better quality cameras on smartphones and the growing appetite for on-demand content on social media now have Facebook and Twitter competing head to head to encourage more people to stream raw footage. Pre-recorded videos on web pages are the norm now but the growth of live videos is exploding. Twitter recently purchased live-video-streaming app Periscope which already has over 200 million broadcasts. Add to this the recent release of Snapchat’s Chat 2.0 which emulates face-to-face communication while making it easier to switch between video, texting and calling. Upon reading all of this I realized that it will be people like my 17 year old daughter who seem to be forever glued to their smartphone that will push the use of silicon photonics ICs (PICs) into the mainstream. What, you ask do 17 year olds and live video streaming have to do with PICs? Just imagine how much bandwidth will be required within and between our data centers and mobile devices to handle random, bidirectional, live video streaming for Facebook’s 1.6 billion users. It boggles the mind. Layer on top of this the latest ideas about the Internet of Everything where millions of smart devices will be vying for your attention and you will quickly realize that the current 10Gbps connections in today’s data centers will be woefully inadequate to handle the amount of traffic that is coming their way.

Data Center providers are already responding to the increased traffic needs by building mega data centers
(Mega-Datacenters are the Future) but these centers come with their own new challenges. Traditional data centers dealt mainly with independent jobs with only course inter-server interactions. Memory and storage were co-located close to the servers meaning that latency across the data center was not a big concern. This is changing rapidly now with the advent of software configurable mega data centers that use virtualization of processors, memory, long term storage and networks to provide unique and customized services to their customers. Virtualization brings with it the need for scalable lower latency network communications across the data center as decisions about how resources will be combined are held to the last moment and change over time. The new mega data centers are now looking at network requirements across the data center that are much more akin to what would be seen in high performance computing environments using fine grained inter-process communications. Add to this the sheer size of the mega data centers stretching to kilometers and copper wire networking gets very expensive both in terms of latency (including multiple hops through switches to get across the data center) as well as power consumed to drive those switches and cables.

Enter the advent of Silicon Photonics and new network architectures that use modulated laser light through fiber connections to reach across the 2km data center in a fraction of the time required for copper cables and switches and at a fraction of the power. Silicon Photonics will not only enable faster, less power consuming communication but it will also enable more direct communications by integrating the photonics either on die or in-package with the server’s components eliminating the need for multiple levels of power hungry switches. A good example of commercial progress towards this end is the recent product announcement by MACOM for 100G silicon photonics-based communication solutions within the data center using standard QSFP28 optical connectors (MACOM).

Nothing drives invention and paradigm shifts like necessity and I can’t think of too many forces of necessity stronger than my 17 year old daughter needing to communicate with her friends, unless it would be my wife needing me to take out the garbage.


In the Valley & thinking about FD-SOI for your next chip design? Epic (and free) symposium 13 April

In the Valley & thinking about FD-SOI for your next chip design? Epic (and free) symposium 13 April
by Adele Hars on 04-02-2016 at 7:00 am

If you’re in the chip biz in Silicon Valley, check out the SOI Consortium FD-SOI Symposium on April 13th in San Jose. They’ve been running these things since 2009, and I have to say that this one is the most comprehensive to date. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to the see FD-SOI ecosystem in action.

To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.

It’s really a terrific agenda – check it out:

08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM– 10:50AM– Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium

Seriously – this good. Plus during breaks there will be poster sessions with GSS, sureCore, Soitec, SEH and the SOI Consortium.

Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA

If you can’t make it, not to worry – I’ll be there taking notes for a round-up and follow-up articles. Plus I’ll be doing plenty of tweeting and retweeting (follow me @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.

Most of the presentations will also be available on the SOI Consortium website following the event. In the meantime, you can click here to peruse the presentations from previous events.


Managing and Reusing IP in a Build-Borrow-Buy Era

Managing and Reusing IP in a Build-Borrow-Buy Era
by Don Dingee on 04-01-2016 at 4:00 pm

Make-versus-buy inadequately describes what we do now in electronic systems design. We are on a continuum of design IP acquisition and use decisions, often with a portfolio of active projects and future projects depending on the outcome. Properly managing IP means adopting a build-borrow-buy mindset and tools capable of handling all aspects of the process.

In a binary make-versus-buy decision, teams either bought a complete subsystem (say a single board computer or real-time operating system) or made it from scratch. The potential for the buy option to disenfranchise designers often led to resistance. Overcoming that objection meant enabling design teams to add their value while still buying a base platform – such as expansion connectors for daughter boards and libraries and APIs for operating system extensions.

Subsystems became more modular and reusable, if properly defined with some kind of structure. Abstraction of IP eased integration and fostered reuse. Tradeoffs became much more granular. Rather than managing a design as a whole, functional blocks of software code or hardware descriptions could be brought into play quickly and managed as individual pieces integrated into a greater scheme.

Build-borrow-buy is a better term for two reasons. First, it represents what we really do. Second, it recognizes that reuse is manifested in several ways. Build is straightforward, with an IP block made in its entirety by internal or contracted design teams. Borrow suggests use of a block that was built or bought and proven in a previous design, or one that was lifted from an open source community for this design (and presumably proven in some use there). Buy delivers a block either to our exact specifications or commercial source files that can be tuned quickly to meet the needs.

Objectives in managing software and hardware IP are quite similar. Typical needs begin with version control and bug tracking. Once those are under control other uses appear, such as collaboration and access control, royalty tracking, licensing pass-through, artifacts for patent applications and compliance audits, and M&A due diligence. Automation of IP management provides huge benefits as the complexity of individual projects grows and a portfolio develops.

However, dissimilarities between software and hardware quickly emerge when the acquired IP is to be synthesized and integrated into a working product. A software configuration management tool such as Subversion handles source code and metadata needed for compilation in a high-level language such as C or Java. What these tools lack is any knowledge of a hardware design flow or the ability to handle multiple file formats (likely with different EDA tools) and relationships involved when working with hardware IP. Extending these software-centric tools to integrate with typical EDA tools would be a massive undertaking.

Just as it makes sense to evaluate IP on a build-borrow-buy scale, it also makes sense to consider EDA tools in that same context. While borrowing an open source tool like Subversion sounds attractive, buying tools appropriately designed for hardware IP management can rapidly pay for itself in complex environments. The number of IP blocks in designs has swollen, with larger designs now containing 100 or more. A typical large design team is now distributed, drawing on expertise from around the globe.


ClioSoft has built a robust, extensible hardware IP design management system in SOS7. Its focus on collaboration and integration with multiple design flows – including digital, mixed-signal, and RF – means that design teams can start managing IP quickly with a minimum learning curve. Instead of stepping outside a familiar design environment to perform additional steps (such as checking files in and out of Subversion), the SOS platform leverages existing EDA workspaces and optimized network storage. SOS handles the nuances of file and metadata organization without burdening the designer with the need to understand where information resides before attempting to use it. The fault-tolerant architecture handles synchronization, backup, and security of the repository.

The bottom line here is hardware teams should be managing the IP and the design, and not spending a lot of effort on improvising with tools not designed for the job. Knowing where IP has been, where it is and what state it is in right now, and where it is going is a competitive advantage that frees design teams from otherwise manual tracking methods. Selection of IP in a build-borrow-buy approach, including how internal teams have modified IP after obtaining it, is a fundamental element of efficient IP reuse.

We’ll be exploring ClioSoft SOS7 capabilities, how it facilitates IP reuse and collaboration, and how IP management fits in the bigger build-borrow-buy picture in future posts.

Also Read

Reinventing Power Management ICs for Mobile

Evaluating the performance of design data management software

The Case for Data Management Amid the Rise of IP in SoCs