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Is Elon Musk from the Future?

Is Elon Musk from the Future?
by Roger C. Lanctot on 04-17-2016 at 10:00 pm
Categories: Automotive

One of the more annoying (ie. delightful) things about Tesla Motors is the way the company casually disrupts long established auto industry business models. Whether it is vehicle sales and service or overcoming EV range anxiety or using your car to as an extension of the power grid or letting your car drive itself.

The latest twist from Tesla, revealed in Tesla owner posts on Facebook, is a one-month free trial of Autopilot mode. The function is enabled within 30 seconds if you choose to take it.


Tesla began making cars in 2014 with the Autopilot capability built in. The feature was available as part of a convenience package with emergency braking and side collision avoidance. For $2,500 at the time of purchase, the Model S owner could add active cruise control and automatic highway steering.

Tesla buyers not choosing the option at the time of purchase can activate it later for $3,000. But Tesla has gone one step further with the free trial. The simplicity of the offer disguises its mind-blowing possibilities and the tragic implications for traditional auto makers.

Mind-blowing possibilities
With the Autopilot free trial Tesla is demonstrating what advanced driver assist technology analysts have been pointing out for quite some time.

Camera-based sensors on cars can be used for multiple purposes including everything from detecting driver inattention to enabling collision avoidance, lane keeping, blind spot detection, self-parking, all-around views of the vehicle, emergency braking and adaptive cruise control.

Once the sensors, including radar and sonar, have been added to the car at the factory the process of turning on features may not even require a software “download.” It may only require an update to deliver the latest algorithms along with a “switch” to activate the software which is already on-board in the car.

The power of the free trial strategy for safety features lies in the ability to tease and delight customers with safety features that might not normally be selected at the original vehicle purchase. Many of these features require demonstration, something the average car buyer these days simply doesn’t make time for. But as a free trial, Tesla has opened the door to pushing and promoting safety enhancements long after the original sale of the car.

The insurance-related opportunities are endless here. Sponsored safety anyone? “Download or turn on this safety feature and we’ll give you a discount on your insurance.” “Collision avoidance brought to you by State Farm and Mobileye.” “Ten percent off your premium as long as you keep the feature turned on.”

But why stop at safety, what about adding performance features and different suspension setups for days spent at a local race track? What about temporarily turning features on for long trips – yes, that’s right, on-demand safety or safety as a subscription service?

It’s enough to make one wonder: Is Elon Musk from the future?

Tragic implications
For the incumbent car maker community, Tesla’s free trial proposition along with his huge head start on over-the-air (or, really, over Wi-Fi mainly) software updates and now remote function unlock is tragically embarrassing. The highly silo-ed structure of the typical auto maker with its hide-bound engineering practices (ie. “You can’t do that.”) are virtually incapable of responding to the Tesla value proposition and disruption.

For the typical auto maker, safety systems, infotainment systems and communications gateways are managed by different and sometimes competing departments. Even worse, sometimes these departments compete with, resent or otherwise struggle between themselves riven as they are by conflicting technology life-cycles, business models, and marketing priorities.

Like an alien saucering into the automotive market, Tesla’s CEO Elon Musk continually brings news of the future. An Autopilot free trial is only the latest case of aftersales delight from Tesla. But the implications for a car that gets safer and sexier over time is devastating.
What’s next from Tesla? Greater driving range on demand? New cloud services on the fly? Aftermarket hovercraft mode? Next time you run into Elon, don’t forget to say: “Klaatu barada nikto.”

Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

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Dr. Evil and On-Chip "LASERS" for Silicon Photonics

Dr. Evil and On-Chip "LASERS" for Silicon Photonics
by Mitch Heins on 04-17-2016 at 12:00 pm
Categories: Silicon Photonics

In the 1999 comedy, The Spy Who Shagged Me, Dr. Evil laments about why he can’t have sharks with “laser beams” attached to their heads. I get the feeling that silicon photonic designers sometimes feel the same way about why they don’t yet have integrated on-chip laser light sources. While off-chip light sources have good light-emitting efficiency and thermal stability they suffer from relatively large coupling losses between the laser and the photonic IC (PIC) and higher packaging costs. At ITC 2015 W.R. Bottoms presented on ensuring reliability in the era of heterogeneous integration (see paper here). In his presentation he stated that 2015 was the year in which the number of mobile-connected devices first exceeded the number of people on the earth. He went on to project that broadband speeds need to more than double by the year 2019 and that in order to do this our concept of network architectures will need to change. Key to that change will be the movement of network photonics closer to the chip level.

On-chip light sources have the potential for moving photonics onto the chip itself promising higher integration density, compact size and better energy efficiency. Unfortunately, silicon(Si) is an indirect band gap semiconductor and is very inefficient at light generation. This has caused the on-chip light source to be one of the last lagging components of a truly integrated photonics solution. Companies like Luxtera have been successful using off-chip light sources in telecom markets but lack of progress on an on-chip light source is currently limiting the progress of chip level optical interconnect technology. According to an article published in Light Sciences and Applications, an ideal on-chip light source should be able to emit light at 1310 or 1550nm wavelengths to connect directly to the external fiber optical networks, lase under electrical pumping for compact size & high integration density, display high power efficiency for sufficient output power and low energy cost-per-bit transmission and be able to integrate on Si with CMOS compatible fabrication techniques for large scale manufacturing. The paper reviews three most likely solutions for an on-chip light source, those being Erbium (Er) related light sources, Germanium-on-Si lasers and III-V-based hybrid Si lasers. Table 1 from the article lists these light source candidates with their advantages and disadvantages.


While good progress has been made on ER-doped fiber amplifiers and lasers (EDFAs/EDFLs) they have yet to make the jump to electrically pumped lasers, one of the key criteria for an on-chip light source so for now Er is not on the short term horizon.

Germanium (Ge) is an interesting candidate for on-chip lasing in that it is the material most closely matched to Si, to the point that it too is an indirect band gap material. However, Ge is different from Si in that it exhibits a pseudo-direct band gap behavior that enables it to emit light of approximately the magical 1550nm wavelength. Much research exists around what is known as band gap engineering with the idea to modify the band structure of Ge enough to effectively turn it into a direct band gap material. Good progress has been made to this end using strategies such as enhanced n-type doping to fill-up the valence band with electrons used for lasing, and using tensile strain and alloys of Ge and Tin (Sn) to shrink the band gap to enable efficient lasing.


One of the main challenges is to establish a trade-off between these strategies in terms of optimizing the performance of a Ge laser while also avoiding operating wavelength redshift, an artifact of narrowing the bandgap. An additional challenge yet to be overcome is the relatively high threshold current density required for Ge lasers. Challenges notwithstanding, Ge’s large gain spectrum and ability to work at high temperatures makes it very attractive in wavelength division multiplexing (WDM) systems and high-density optical-electrical ICs. Additionally, Ge is also widely used for modulation and detection and therefore could simultaneously address all of these areas in a monolithic integrated SiGe-based photonic platform while maintaining compatibility within a CMOS process flow needed to reduce process complexity and cost.

In the meantime, III-V-based hybrid Si lasers using various bonding techniques currently represent the most practical on-chip silicon photonic light sources. These lasers however suffer from poor heat dissipation due to the high thermal resistance of the bonding layers. Given this, these types of lasers may not be suitable for large-scale dense monolithic integration in terms of yield and cost over the long term. The alternative with growing momentum is high-quality quantum dot (QD) materials that have been successfully grown on Si using direct hetero-epitaxial growth (III-V QDs). These III-V lasers have been demonstrated to maintain lasing operation at up to 120 °C with low threshold current densities of 62.5 A/cm[SUP]2[/SUP]. Monolithically grown on Si, they could be more promising as on-chip lasers, and may satisfy the requirements for low-cost, high-yield, temperature-insensitive, and large-scale high-density monolithic integration.

So what would Dr. Evil have done with an integrated on-chip “laser”? Strapped it onto the head of “Mini-Me” of course!

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Single Electron Transistors; the Single Answer?

Single Electron Transistors; the Single Answer?
by Students@olemiss.edu on 04-17-2016 at 7:00 am
Categories: IoT

According to a press release made last year by Gartner, “the world’s leading information technology research and advisory company,” there is projected to be nearly 21 billion internet connected devices by the year 2020 [1]. With the Internet of Things’ ever growing list of network connected devices, the demand for more compact, more cost effective, and more power efficient microprocessors is at an all time high and will only continue to grow. In order to keep up with this demand, engineers across multiple continents have begun to research the next generation of microscopic transistors. A recent project titled “Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology”(IONS4SET), coordinated by Helmholtz-Zentrum Dresden-Rossendorf, is exploring one possible answer to this demand that comes in the form of single electron transistors.

Single electron transistors, referred to as (SETs), like the more common field effect transistors (FETs) are a “three terminal switching device” [2]. Both SETs and FETs have a source and a drain terminal, whose connection to one another is controlled by a signal on the gate, however, the similarities begin to end there. In addition to gate, source, and drain, SETs also have a quantum dot, called the island, in the center with an insulating barrier known as the tunneling junction on either side, creating a barrier between the island and the source and drain. When a capacitance is created on the gate and thus a capacitance on the island, it raises the electron’s energy above the coulomb blockade energy, allowing the quantum phenomenon known as Tunnel Effect to occur, transferring (as the name suggests) a single electron from the source to the drain through the tunneling junctions [2]. The design is in contrast to the many, many electrons that are simultaneously allowed to flow from source to drain in a field effect transistor.

Because SETs only manipulate one electron at a time, single electron transistors offer two very promising advantages over transistors in use today. The first being, the incredibly small size. Current generation transistors in production today by Intel are 22nm with 14nm arriving in the near future, on the other hand, the SETs being developed by the IONS4SET group using their “bottom-up self assembly process” for fabrication are achieving feature sizes of approximately 2 nm [3]. With a decrease in size there is a decrease in power consumption. SETs with feature sizes of only a few atoms take an astonishing little amount of power to function. SETs small size and low power consumption are what make them so promising, with two-thirds of the holy trinity of transistors(smaller size, lower power consumption, and lower cost), SETs are well on their way to being a favorite of manufacturers to use in their products.

While very promising, SETs do not operate with impunity. SETs are very sensitive to thermal noise, meaning in their current state they are incapable of operating at room temperature requiring a very low temperature operation of 4 to 2 kelvin. Another major obstacle in SET implementation is its incompatibility with current CMOS logic. Current CMOS technology has a voltage threshold that must be met before normal operation is possible and also require, when compared to SETs, a relatively large amount of power. Current SETs are so low power that transfer of energy beyond itself is very difficult and is too weak to interact with CMOS. In order to bridge the gap between SET and MOSFET the signal from the SET must be amplified to a level suitable for MOSFETs, which in itself is difficult, requiring “very sensitive MOSFET transistors” [4]. A way around this amplification process would be to create an all new logic based on the single electron transistor and its quantum functions, but this is still very far from being a viable option and wouldn’t help the compatibility issues already present.

Beyond the limitations of the SET itself is the issue of fabricating SETs on a large scale. The widely used lithographic and photolithographic fabrication methods are difficult to control at the resolution required to create the SETs [4]. A new fabrication method is one of the main goals of the IONS4SET project, potentially resulting in a new, reliable mass fabrication method with the precision needed, but not yet met by current methods.

There are various applications of Single Electron transistors . The primary implementation of SETs is in memory cells, as it utilizes quantum dots to store a large amount of information. Due to its incredibly small size of 2 nm, SETs allow more cells to be used in a small area thus lowering the power usage and making the circuit integration more effective . The SETs are also used as efficient charge sensors meaning it reads the charges of the qubits stored in the Quantum dot. By this process , the charge transition for both high and low conductance can be observed [5]. Due to its sensitive nature ,SETs can also detect infrared radiations; “By exciting electrons over an electrically induced energy barrier, both the range of detectable wavelengths and the sensitivity of the device can be controlled” [6]. Other applications also include SET oscillators which is useful for radio frequency systems

The future of electronics relies on the production of smaller and more efficient transistors. Engineers are working hard to discover the next great advancement in transistor design and fabrication to meet the growing demand. Single electron transistors offer one promising path leading to that advancement, but there is still a long way to go. It has to overcome difficulties in production, as well as, problems with implementation with current technology. Even still, the future is very bright for single electron transistors hopefully leading to new microscopic transistors making it possible to connect the new, vast array of future devices.

By Maisha Sadia and Beau McCarty

Sources cited
[1]R. van der Meulen, “Gartner Says 6.4 Billion Connected ‘Things’ Will Be in Use in 2016, Up 30 Percent From 2015,” “Things” Will Be in Use in 2016, Up 30 Percent From 2015, 10-Nov-2015. [Online]. Available at: http://www.gartner.com/newsroom/id/3165317. [Accessed: 23-Feb-2016].

[2]V. P. Singh, A. Agrawal, and S. B. Singh, “Analytical Discussion of Single Electron Transistor (SET),” International Journal of Soft Computing and Engineering(TM), 03-Jul-2012. [Online]. Available at: http://www.ijsce.org/. [Accessed: 23-Feb-2016].

[3]H.-Z. D.-R., “Ion-irradiation-induced Si Nanodot SelfAssembly for Hybrid SET-CMOS Technology,” Ion-irradiation-induced Si Nanodot SelfAssembly for Hybrid SET-CMOS Technology, 02-Aug-2016. [Online]. Available at: https://www.hzdr.de/db/cms?poid=45667.

[4]D. AGUIAM and O. B. R. E. C. Z. Á. N. Vince, “A Brief Introduction to Single Electron Transistors,” Tecnico Lisboa, 18-Dec-2011. [Online]. Available at: https://fenix.tecnico.ulisboa.pt/downloadfile/3779578912209/aguiam_obreczan__introset_nov2011.pdf. [Accessed: 23-Feb-2016].

[5]E. P. Nordberg, H. L. Stalford, R. Young, G. A. T. Eyck, K. Eng, L. A. Tracy, K. D. Childs, J. R. Wendt, R. K. Grubbs, J. Stevens, M. P. Lilly, M. A. Eriksson, and M. S. Carroll, “Charge sensing in enhancement mode double-top-gated metal-oxide-semiconductor quantum dots,” Appl. Phys. Lett. Applied Physics Letters, vol. 95, no. 20, p. 202102, 2009.

[6]A. Kumar and D. Dubey, “Single Electron Transistor: Applications and Limitations ,” Advance in Electronic and Electric Engineering, vol. 3, no. 1, 2013 pp. 57-62.

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Intel Dinner Keynote – IOT Solutions: System scaling during the convergence of IT and OT

Intel Dinner Keynote – IOT Solutions: System scaling during the convergence of IT and OT
by Daniel Nenni on 04-16-2016 at 7:00 am
Categories: Foundries, Intel Foundry

The Electronic Design Processes (EDP) 2016 Workshop and Symposium, in its 23rd year, has fostered the free exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. It has provided a forum for this cross-section of the design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.

EDPS Symposium: IoT Workshop
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The EDPS was founded by Bill McCallah in 1978 as key activity of the Design Automation Technical Committee (DATC). This annual EDPS Workshop and Symposium takes place each year in Monterey, California, and emphasizes both the here and now and the future.

Attendees of this elite workshop have met each year since 1993. It has attracted some of the most far-seeing people in the electronics industry and academia as speakers. If you need to know where the industry is and where it’s going with respect to the design and development, and especially methodologies and technology of design, you should consider attending this year.

The dinner keynote this year is Ken Caviasca, Intel Vice President and GM of IOT Platform Engineering. Ken has the exciting role of developing a broad range of IOT systems from things to the cloud. The pace of innovation has never been faster with the advent of performance/cost scaling of 3 key attributes. Compute, Connectivity, and Data.

Dinner Keynote – IOT Solutions:
System scaling during the convergence of IT and OT
The multi-fold improvement in the prior attribute has given lift to new IOT solutions. IOT solutions span a wide range of markets, industries, and technologies. There are many real world improvements and problems which can be solved at technology solutions moves from people driven solutions to a “things” driven solutions. As this shift occurs there are several foundational capabilities that must scale across vendors and device performance levels. An additional challenge in these emerging IOT systems is to converge attributes of IT and OT as the systems enter the interface with physical systems. When IT and OT is blended correctly the best of both domains can be applied to solving real world problems in a cost effective, safe and reliable manner. This requires a cloud through edge capabilities that combine in a way to implement new systems. Systems that would have been too cost prohibitive to build only 5 years ago. Today we are building and deploying these IOT innovations which are improving efficiency, driving valued improvements to operations and people lives. It certainly is an exciting industry inflection point we are innovating in today.

Kenneth P. Caviascais vice president in the Internet of Things Group and general manager of platform engineering and development at Intel Corporation. He has overall responsibility for computing platforms targeted to the Internet of Things (IoT) market segment, including planning, architecture, user experience priorities, silicon definition, operating system porting, hardware, firmware, validation and manufacturing test. The IoT platforms developed by his team encompass product offerings based on Intel® Atom™, Intel® Core™ and Intel® Xeon® processors.

Since joining Intel in 1984 as a silicon engineer in automotive controllers, Caviasca has held various technical and management positions in flash microcontrollers, embedded devices, video signal processors, security devices, chipsets, network processors, server processors and manufacturing operation startup. Before assuming his current position, he managed platform development for the Intelligent Systems Group, overseeing hardware, validation and software integration development. Earlier in his Intel career, he managed silicon development for the Communication Infrastructure Group and led a team responsible for delivering system-on-chip, server-class and chipset products for the embedded and communications market segment.

Between 2008 and 2010, Caviasca’s development team won several premier supplier awards from industry-leading communications equipment suppliers. He and his team also won an Intel Achievement Award in 2004 for excellence in network processor development.

Caviasca earned his bachelor’s degree in computer and electrical engineering from the University of Bridgeport in Connecticut and his MBA degree from the W. P. Carey School of Business at Arizona State University. He holds seven patents in circuits, CPU and video systems architecture.

EDPS Symposium: IoT Workshop
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Debugging is the whole point of prototyping

Debugging is the whole point of prototyping
by Don Dingee on 04-15-2016 at 4:00 pm
Categories: EDA, Synopsys

The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem. Continue reading “Debugging is the whole point of prototyping”

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Singularity, Semiconductors and Software

Singularity, Semiconductors and Software
by Daniel Payne on 04-15-2016 at 12:00 pm
Categories: General, Security

One of my all-time favorite movies is 2001 A Space Odyssey where one of the leading roles is an AI-based system aboard a spacecraft named Hal that is designed to be a perfect machine yet makes a mistake and then cascades into assaulting and eliminating the human crew members. The future time when semiconductors and software combine to create a machine intelligence that outpaces humans has become known as “the singularity“, a phrase coined by Ray Kurzweil now the Director of Engineering at Google.

In my lifetime we have seen domain-specific software and hardware systems that defeat humans in many tasks, like:

  • Chess
  • Backgammon
  • Poker
  • Go
  • Jeopardy
  • Blackjack
  • Stock market trading

One very positive life impact with decreasing costs of semiconductors coupled with higher processing speeds has been in the area of sequencing DNA, where the cost per Genome has gone from $100M in 2001 to just about $1K in 2016, a rapid decline in price greater than the improvement in Moore’s Law:

Source: National Human Genome Research Institute

Should we be fearful of AI based systems?

Even Stephen Hawking is cautionary about AI when he endorsed an open letter along with other world influencers:

Autonomous weapons are ideal for tasks such as assassinations, destabilizing nations, subduing populations and selectively killing a particular ethnic group. We therefore believe that a military AI arms race would not be beneficial for humanity. There are many ways in which AI can make battlefields safer for humans, especially civilians, without creating new tools for killing people.
IJCAI 2015 Conference

In health care we certainly want the best diagnosis, which may include scanning our DNA, reviewing our medical history, and analyzing our vital signs using an AI-based system instead of a doctor. The only downside of giving machines and software access to health records is the whole area of data privacy and opening ourselves up to the risks of hacking.

Many industries are undoing fundamental change as automation is used to relieve labor-intensive tasks like: printing, fast-food order taking, etc. Just take a look at the steady decline in number of employees per print shop since 1998 as they use more automated approaches, requiring fewer humans:

Imagine what could happen with the trucking industry where autonomous vehicles could help cut operating costs by 50% during the vehicle’s lifetime of 600K miles, replacing or augmenting human drivers to improve safety, avoid accidents and shorten deliver times.

Leading automotive companies like Tesla are now able to update their electric vehicles wirelessly to add new features like Autopilot. This feature allowed a Tesla owner to drive across the US in under 60 hours by using Autopilot 96% of the trip.

What’s your plan to stay ahead of a machine replacing your job? When I started out doing IC design we did manual DRC (Design Rule Checking), but now that task is quite automated by software, so that freed me up to be more creative on the circuit design decision.

Our society needs to adapt to the coming challenges and prepare our children to do things that AI and machines cannot do. Mr. Kurzweil predicted that the singularity could arrive as soon as 2045, a scant 29 years from now, so make your own plans accordingly.

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A CIA Perspective on Privacy and Security

A CIA Perspective on Privacy and Security
by Bernard Murphy on 04-15-2016 at 7:00 am
Categories: Security

It may seem odd to look to the CIA for viewpoints in this area but in in many ways they are just as concerned as we are. After all, in aggregate, widespread identity theft and hacking both internally and by foreign nationals, theft, electronic ransom and other illicit acts are as much a threat to the security of the country as they are to us personally.

Recently Wired magazine interviewed the chief information security officer at the non-profit venture arm of the CIA. I found the interview a bit directionless and not always helpful in proposed solutions but a number of important points emerged.

One comment was on the dangers of data fusion; I also commented on this in an earlier post on privacy. Small subsets of personal data don’t seem to pose much of a threat and where we feel data is particularly sensitive (medical records for example) we are promised that if data is to be used for wider access, it can be “de-identified”, replacing personal fields with generalized values, for example replacing an address with a zip-code. The problem is that between big-data gathering and simple JOIN operations, it really isn’t difficult to assemble detailed personal profiles on individuals, making current attempts at de-identification (if applied at all) pointless – as a prior governor of Massachusetts discovered.

EDPS Symposium: Cyber Security Workshop
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There was a comment on the EU “Right to be forgotten”. This sounds good on the surface but is difficult to square with freedom of speech standards in many countries and the likely impracticality of imposing country-specific standards on global data searches (which is why Google is at the center of most of these debates). The most useful point from this part of the discussion was a definition of privacy and secrecy: privacy is something others give to you whereas secrecy is something you take for yourself. Which is why there’s so much interest in encryption now – if I can’t be guaranteed privacy, then I want to be able hide what I do not want others to know.

One suggesting on dealing with hacking is to counter with the most efficient machine we know – capitalism. Of course we do this today in one sense – lots of companies selling security products, but this is only one angle of attack. It doesn’t necessarily address security holes in other products and where it might, whatever is or is not corrected often remains a product company secret. The suggestion is that the US government should pay a bounty on vulnerabilities for whoever wants to find them, in whatever products they choose to hack (maybe the government can claim the bounty back from the offending product companies). If the potential impact is high perhaps the problem is widely publicized, otherwise maybe the government gives the product company a few weeks to fix it, then goes public. Either way, product companies are motivated through public embarrassment and possible loss of business unless the hole is plugged.

Finally, the CIA guy made a point I strongly support – over many, many years (going back at least to the Industrial Revolution in my view) we have demonstrated that we are extremely adept at building things we cannot manage without going through a painful learning curve. He thinks this amply applies to Internet technologies, which is why he has no cell phone and only carries a pager. That a senior executive for a CIA venture fund feels this way has to give you pause for thought.

To read the interview, click HERE.

More articles by Bernard…

EDPS Symposium: Cyber Security Workshop
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Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA

Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA
by Herb Reiter on 04-14-2016 at 12:00 pm
Categories: EDA

Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.

However,
– how can you serve applications that don’t require a billion units over their life time and can’t pay back a large NRE?
– how can your company continue to grow if it needs to invest such large sums and “bet the farm” on a single project?
– how can you pack logic, memory, analog, RF, MEMS,… and other functions economically into a 7 nm SoC?

The Electronic Design Process Symposium (EDPS) 2016 will address these and many other questions on Thursday afternoon, April 21.

EDA, IC design and IC packaging experts will present their capabilities in support of packing multiple dies into one IC package, suggest where and how to combine multiple dies in a 2.5 or 3D-IC, or consider wafer-level packing. Half of the 2-hour session is reserved for discussing the benefits as well as answering your questions during the panel discussion.

Herb Reiter, from eda 2 asic, will introduce the session’s subject, outline his new consulting role at the Electronic System Design Alliance (formerly known as EDAC), highlight why our industry needs to complement continued shrinking with multi-die IC technologies, suggest what the represented industry segments need to do to further grow market acceptance of these innovations, introduce the panelists and also moderate the discussion with the audience.

Riko Radojcic, well known for his role as 3D-IC evangelist at Qualcomm, will share his vast expertise in how to determine cost advantages and technical reasons for choosing a multi-die IC technology for a specific application.

Mentor Graphic’s Dusan Petranovic will present and discuss the importance of accurate modeling and thorough verification for cost-effective and reliable multi-die ICs.

For companies who do not have sufficient in-house resources to execute a multi-die IC design and/or want expert advice for engaging the right supply chain partners, plan to develop a multi-die IC design methodology, want assistance to ramp up volume production for such ICs or other reasons, Design Services companies are ready and eager to offer their expertise. Asim Salim will represent Open Silicon, outline the team’s expertise and their important role in the Multi-die IC EcoSystem. See below the EcoSystem’s key segments and their individual roles.


The next speaker, Ivor Barber, has many years of experience in advanced IC packaging and will present why Xilinx chose to pioneer multi-die IC technology several years ago already. He’ll outline technical and business reasons for the success of Xilinx’ “Stacked Silicon Interposer Technology” (SSIT).

Paul Silvestri from Amkor, a leading IP Packaging and Test corporation, will show Amkor’s portfolio of traditional and recently introduced advanced IC packaging technologies, which include a very cost-effective family of Fan-Out Wafer-level packages.

After these brief presentations our experts will be available for an additional hour to answer questions from the audience. Herb will moderate this panel discussion and make sure that every attendee can see that the EcoSystem in support of multi-die ICs has made significant progress in the last few years. Now many partners can offer you viable products and services for your first (or next) multi-die IC design. You also can integrate one of your proven SoCs — in die-form — together with other die-level IP, such as a memory cube, in a multi-die IC package and enjoy the performance, power, form-factor and system cost benefits versus individual, fully packaged ICs on a PC board.

Just in case that you are still hesitant to fit EDPS into your busy schedule, click on the pointers below. The first one leads you to a recent article that describes how NXP/Freescale use their RCP interposer technology for a 77GHz automotive radar application: http://www.systemplus.fr/wp-content/uploads/2016/03/NXP_MR2001_Freescale_Radar-Chipset_Flyer_SPC_v2.pdf

The second pointer directs you to last week’s Nvidia announcement of the Tesla P100 GPU and their DGX-1 GPU server, utilizing four memory cubes surrounding a GPU on an interposer: http://www.eetimes.com/document.asp?doc_id=1329368

For many more articles about concrete applications of multi-die ICs and a lot of other information about the Multi-die IC EcoSystem, please click on this pointer and download the 324 page Multi-die IC Design Guide from the Electronic System Design Alliance’s website: http://www.esd-alliance.org/industry/publications

More about EDPS and other valuable sessions at: http://edpsieee.ieeesiliconvalley.org/edps_program.php

SemiWiki-EDPS2016promo code for a $50 savings.

See you at EDPS in Monterey next week….Herb

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EDAC Name Changing for ESDA, but what about IP ?

EDAC Name Changing for ESDA, but what about IP ?
by Eric Esteve on 04-14-2016 at 7:00 am
Categories: EDA, IP

The EDA Consortium (EDAC) has changed name for Electronic Systems Design Alliance (ESD Alliance). That’s a good reminder that IC are developed (thanks to Design Automation) to be integrated into a System. A wide design ecosystem support system development, including embedded software, design intellectual property (IP), embedded software, advanced packaging (3D, TSV,…) and design service companies.

Let’s focus on the design IP segment, which is now “officially” the largest category according with the results published by EDAC for Q4 2015 with $702.2 million and +9.2% growth (see the picture below).

I decide to focus on design IP for several reasons ; at first because we will see that the growing behavior of the segment monitored on a 20 years timeframe exhibit an amazing vitaly, almost imune to economical crisis. The second point justifying to look at the design IP business more carefully is that this segment is underestimated if you only look at EDAC results. Not because EDAC or ESDA doesn’t do a good job, but simply because the IP revenues reported quarterly by EDAC are generated by IP vendors being part of the organization. By definition, an IP vendor who is not an EDAC member will not report IP revenues to EDAC, and there is no way for EDAC to take these revenues into account.

Thanks to EDAC, we can monitor the revenues generated in the five categories by the members during the last 20 years, or 80 quarters. The dynamism of the Silicon IP (SIP, in clear blue) appears through the strong growth rate, SIP passing from (almost) zero in 1996 to $700 million per quarter in 2015. CAE, the former largest category, has grown from $300 to $650 million on the same timeframe. Or, if you prefer, it took only 5 years for SIP (2010 to 2015) to make a move which took 20 years to CAE (passing from 300 to 700).

Let’s zoom into the 2008 to 2011 period, covering the strongest economic crisis since 1929. SIP category has been impacted, strongly declining in 2009, like the other categories. But, it took only 5 quarters for SIP to come back to the pre-crisis level, when it took 10 or 15 quarters for CAE or IC Physical to recover. Why SIP has recovered much faster than tools categories?

Let’s take an example: a team is developing a SoC in 2009, and R&D cost has to be lowered due to the crisis. The project manager may decide to lower the EDA investment and buy 4 seat licenses instead of 6, for example. But if you need a GPU, or MIPI CSI PHY or PCIe PHY and Controller, taking the decision not to buy these IP and develop it in-house is possible, assuming you have the right design resource, but certainly a lot more risky than buying a Silicon proven IP to a vendor. We can assume that SIP is now a strategic piece of System-on-Chip development and IP outsourcing is clearly growing year after year, with 13% CAGR 2005 to 2015 as extracted from the above picture.

I have no problem with the data collected by EDAC as the result is representative of the IP business. When compared with data collected by IPnest for the Interface IP segment (in the $500 million for 2015) we observe the same growth and CAGR, as you can see on the above picture (issued in 2010, but the 2014 forecast fit with actual data with +/-4% error).

The problem with IP category from EDAC comes from the number of IP vendors reporting their revenue, as only five of them are EDAC members: ARM Ltd., Cadence, Sonics, Synopsys and Mentor Graphics. These five vendors have reported slightly less than $2 billion revenues coming from IP in 2015. It’s easy to guess that the total IP revenues have been higher, but the good question is how much higher.

I have built a non-exhaustive list of missing IP vendors, indicating their 2015 revenue when available from their annual report:

  • Rambus ($300M)
  • Imagination Technologies ($245M)
  • CEVA ($60M)
  • Faraday ($25M)
  • eMemory Technology
  • Kilopass Technology
  • Sidense
  • Aragio
  • Dolphin Technology
  • Andes Technology
  • Cortus
  • GUC
  • Arteris
  • Silicon Image
  • Arasan Chip Systems
  • PLDA
  • CAST
  • Northwest Logic
  • True Circuits
  • Mixel
  • Analog Bits
  • Silicon Creation
  • Silabtech
  • M31
  • Discretix
  • Sarnoff
  • Chips&Media
  • + several dozens

We can observe that four of them are reporting IP revenues for a total in excess of $630 million in 2015 ! I have listed another couple of dozens of IP vendors, either privatly owned, either reporting globally their revenue from IP, design services and NRE. If we assume an average revenue in the $10 million range for these companies, that makes $230 million to be added. If we consider that probably 30 to 50 companies are missing in the above list, we can evaluate the revenue generated by the IP business (not reported to EDAC) is most probably in excess of $1 billion… and this makes $3 billion in 2015.

In conclusion, the SIP category is certainly the most important of the chip design ecosystem, but the figures shared by ESD Alliance are underestimated, the real business figures being in the 40% to 50% higher. What could be done to correct this issue ? Maybe the ESD Alliance could launch a promotion campaign to convince the missing IP vendors to become ESDA members, offering a discounted subscription fee, as most of the missing companies are not as large as the current members… Beeing creative, we certainly could find other options to better know the real size of the Silicon IP market.

Whatever the selected solution, there is a real need to more accurately know the category which is now the most important in the chip design ecosystem !

Eric Esteve from IPNEST –