Bronco Webinar 800x100 1

Webinar: FPGA Prototyping and ASIC Design

Webinar: FPGA Prototyping and ASIC Design
by Bernard Murphy on 02-26-2017 at 4:00 pm

When you think about working with an ASIC service provider like Open-Silicon, you probably think about handling all the architecture, design and verification/validation in your shop, handing over a netlist and some other collateral, then the ASIC services provider takes responsibility for implementation and manufacturing. Plus or minus some options, this is the standard ASIC service model.

REGISTER NOW

Tue, Mar 21, 2017 8:00 AM – 9:00 AM PDT

But this neat division isn’t always ideal. Detailed verification and validation before implementation may require a model of the design than is more accurate than a virtual prototype, close to the detailed design behavior yet much faster than a simulation. In semiconductor companies FPGA-based prototyping is already a popular solution to this need for an accurate, close to real-time performance model and has become indispensable in early driver development, in checking performance, and in simply getting through high volumes of use-case testing.

These needs apply equally even if you are outsourcing back-end design, with an additional constraint that you may also need a working model to loosen up funding for silicon samples. Yet systems design teams often lack the experience to deal with the arcane details of FPGA prototyping, given the high levels of expertise required in partitioning, setup and making sure your prototype implementation will reasonably match the likely ASIC implementation.

Open-Silicon has the answer to your problem. They offer a service to provide, based on your design, configuration to standard prototyping solutions or an option in which they provide custom FPGA boards. Now system design teams can have access to early prototypes to build demonstration systems, start software development and debug in advance of silicon and greatly accelerate RTL verification over large regression and compliance suites. I’ll be moderating a discussion with two experts on why and how customers may want to take advantage of this capability.

REGISTER NOW

This joint Open-Silicon and PRO DESIGN Electronic webinar, moderated by Bernard Murphy of SemiWiki, will address the benefits of FPGA-based prototyping in the ASIC design cycle, and the role it plays in significantly reducing the risk and schedules for specification-to-custom SoC (ASIC) development and the volume production ramp. Early software development and real time system verification, enabled by FPGA prototyping, offers a cost-efficient high-end solution that shortens process cycles, boosts reliability, increases design flexibility, and reduces risk and cost. The panelists will outline best practices to overcome technical design challenges encountered in FPGA prototype development, such as design partitioning, real-time interfaces, debug and design bring-up. They will also discuss the key technical advantages that FPGA-based prototyping offers, such as architectural exploration, IP development, acceleration of RTL verification, pre-silicon firmware and software development, proof of concept and demonstrations. They will also talk about its effect on performance, scalability, flexibility, modularity and connectivity.


Who should attend
This webinar is ideal for hardware system architects, hardware designers, SoC designers, ASIC designers, and SoC firmware and software developers.

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed over 300 designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com


Strong pickup in semiconductors in 2017

Strong pickup in semiconductors in 2017
by Bill Jewell on 02-26-2017 at 12:00 pm

World Semiconductor Trade Statistics (WSTS) is an organization of semiconductor companies created to collect market data. The members of WSTS also meet twice per year to develop forecasts for the semiconductor market. The “forecast by committee” approach of WSTS usually results in conservative forecasts. However, WSTS called it right for 2016. The WSTS forecast released in December 2015 predicted the semiconductor market would grow 1.4% in 2016. The actual growth in 2016 was 1.1%. The chart below shows 2016 forecasts made in the October 2015 to January 2016 period, prior to any 2016 monthly data availability.


After WSTS, the closest was Gartner’s October 2015 prediction of 1.9%. Other forecasts were either higher in the 3.9% to 6.0% range (with our Semiconductor Intelligence forecast the highest) or negative. The 2016 market started out weaker than expected with a 5.3% decline in 1Q 2016 and a weak 0.9% growth in 2Q 2016 – normally a seasonally strong quarter. By mid-2016 basically all the forecasts were negative. Robust 11.6% growth in 3Q 2016 and healthy 5.4% growth in 4Q 2016 turned the year positive.

What is the outlook the semiconductor market in 2017 and 2018? WSTS in November 2016 projected 3.3% growth in 2017 and 2.3% in 2018. WSTS appears conservative for 2017, with other forecasts ranging from 4.4% to 11%. Our latest forecast from Semiconductor Intelligence is for 10% growth in 2017 and 6% in 2018.


What is driving the uptick in the market in 2017? One factor is memory prices. Gartner’s Ganesh Ramamoorthy said increasing memory demand and prices added $10 billion to their 2017 forecast. IC Insight’s Bill McClean expects the memory market to grow 10% in 2017, double the rate of the overall IC market.

Another driving factor is an uptick in the global economic outlook for 2017 and 2018. The International Monetary Fund (IMF) in January projected global GDP will rise 3.4% in 2017, up 0.3 percentage points from 2016. 2018 is expected to add 0.2 points to bring GDP growth to 3.6%. The advanced economies contribute only moderately to 2017 and 2018 GDP acceleration. U.S. GDP growth should pick up from 1.6% in 2016 to 2.5% in 2018, but still below 2015’s 2.6%. The Euro Area and the United Kingdom are project to show flat to decelerating growth over the next two years after the UK voted to withdraw from the European Union. Japan GDP will remain stuck below 1% annual change.


The drivers for global GDP will be the emerging and developing economies, with GDP expansion accelerating from 4.1% in 2016 to 4.5% in 2017 and 4.8% in 2018. China’s GDP growth rate continues to slow, but should remain above a healthy 6%. India and the ASEAN-5 (Indonesia, Malaysia, Philippines, Thailand and Vietnam) offset China with accelerating GDP growth. Latin America will contribute by rebounding from a 0.7% GDP decline in 2016 to a 2.1% increase by 2018.

The electronics markets driving semiconductor market growth will shift from the old standbys of computing (PCs and tablets) and mobile phones (including smartphones). According to Gartner, PCs and tablets will improve from a 9.9% decline in units shipped in 2016, but only to 1.4% growth in 2018 and 2019. Mobile phones units are also expected to increase no better than 1.4% through 2019.


IC Insights expects semiconductor sales for the Internet of Thing (IoT) will show a 13.3% compound annual growth rate (CAGR) from 2015 to 2020. Automotive semiconductors are another key driver with a 2015 to 2020 CAGR of 10.3%.

Our Semiconductor Intelligence forecast of a 10% increase in the semiconductor market in 2017 is based on:
· quarterly market trends driven by a strong second half of 2016
· moderate improvement in the global economy
· increasing memory prices
· modest improvement in the largest applications – PCs, tablets and mobile phones
· continued proliferation in emerging areas such as IoT and automotive
2018 growth will moderate as memory prices stabilize (or decline) but should be a healthy 6%.


OEMs Lead the Way on Self Driving Tech

OEMs Lead the Way on Self Driving Tech
by Roger C. Lanctot on 02-25-2017 at 7:00 am

It’s never a good sign when car makers are called before Congress. It’s almost as bad as being asked to visit the President. But last week the meeting didn’t involve allegations or investigations. It was just an occasion for a friendly chat regarding “Self-Driving Cars: Road to Deployment.”

IEEE Spectrum was kind enough to excerpt notable moments from the Q&A which inadvertently highlighted the confusion prevailing among car makers as to the evolution of automated driving. Links to the full video and the IEEE Spectrum report appear below.

The hearing was held before the U.S. House Subcommittee on Digital Commerce and Consumer Protection and included Gill Pratt from Toyota Research Institute, General Motor’s Vice President of Global Strategy Mike Ableson, and Anders Karrberg, Vice President of Government Affairs at Volvo Car Group, along with Lyft’s Vice President of Public Policy Joseph Okpaku, and Nidhi Kalra, Co-Director and Senior Information Scientist, at the RAND Center for Decision Making Under Uncertainty.

Most notable among the responses elicited by the Congressional representatives were some key contradictions which conveyed the impression that the car makers are still seriously flummoxed by automated driving – and possibly less clear headed regarding the regulatory path forward than you might expect. Two issues, in particular, stand out: Level 3 vs. Level 4 development plans and the role of government.

Frank Pallone (D-N.J.) asked: “Volvo has said that it will skip Levl 3 automation and go from Level 2 to Level 4. Can you explain that decision?

Karrberg of Volvo replied: “At Level 3, the car is doing the driving. The car is doing the monitoring. But the driver is the fallback. So, you could end up in situations where the driver has to take back control, and that could happen within seconds. We are concerned about the Level 3 state, and therefore we are targeting Level 4.”

Kalra of RAND agreed: “There is evidence to suggest that Level 3 may show an increase in traffic crashes, and so it is defensible and plausible for automakers to skip Level 3. I don’t think there’s enough evidence to suggest that it be prohibited at this time, but it does post safety concerns that a lot of automakers are recognizing and trying to avoid.”

Reality is that Volvo has already launched its DriveMe project in Gothenburg, Sweden with drivers monitoring the automated driving in a Level 3 style:

http://www.volvocars.com/intl/about/our-innovation-brands/intellisafe/autonomous-driving/drive-me

Soon GM will be on a similar development path with human drivers monitoring the computer driving. Toyota, too, has adopted this vision. Level 3 automated driving is a critical step in the evolutionary path via which humans will “teach” the machines how to drive.

The greatest strength and weakness of Google/Alphabet/Waymo’s approach to automated driving has been the emphasis on driverlessness – no steering wheel, no pedals. This approach rules out the learning process and appears to be a limiting factor on Waymo’s commercial inroads thus far.

In fact, Pratt of Toyota, cast a bit of shade on Waymo in his testimony (without mentioning the company by name) by noting that the data sharing requirements for tracking driver interventions (in California) seems to favor companies taking a particular approach: “It’s the Federal government that we believe should take the leading role. As you may know, in California there’s a requirement, if you’re doing autonomous car development, that you report to the government what your disconnection rate is—every time that your car has a failure of a certain kind. That’s not such a bad idea, but that information then becomes publicly available, and it creates a perverse incentive, and the incentive is for companies to try to make that figure look good, because the public is watching. And that perverse incentive then causes the company to not try to test the difficult cases, but to test the easy cases, to make their score look good.”

But don’t get the idea that Pratt, or any car company, is prepared to fully embrace government intervention in automated driving development. Debbie Dingell (D-Mich) asked: “Are there specific things that Congress should avoid doing that would stifle the development of autonomous vehicles?”

Both GM and Toyota appear to agree that the government role should be limited. Says Ableson of GM: “We wouldn’t want to see [the] government taking steps to specify a specific technology or specific solution. I think as long as we keep in mind that the goal is to prove that the vehicles are safer than drivers today, the NHTSA guidelines published last year are a very good step in that direction, in that they specify what the expectations are before vehicles are deployed in a driverless fashion.”

Pratt of Toyota agreed: “An evidence based approach is really the best one, where the government sets what the criteria are for performance at the federal level, but does not dictate what the ways are to meet that particular level of performance.”

The message from Toyota and GM is clear. Tell us what to do, not how to do it.

These two perspectives are curious in that they conflict with both Toyota’s and GM’s position on the implementation of vehicle-to-vehicle communications currently facing a potential mandate from the National Highway Traffic Safety Administration. It ws no surprise, then, that Gus Bilirakis (R-Fla.) wanted to know where the respondents stood on V2V tech and how it “fit into the overall blueprint of deploying self-driving cars.”

Pratt took the lead, ultimately calling for preservation of the spectrum set aside for V2V applications: “Vehicle to vehicle as well as vehicle to infrastructure communication is of critical importance to autonomous vehicles. Of course, we drive using our own eyes to see other vehicles, but the potential is there for autonomous vehicles to use not only the sensors on the vehicle itself, but also sensors on neighboring vehicles in order to see the world better. And so, for example if you’re going around a corner, and there’s some trees or a building that’s blocking the view, vehicle to vehicle communication can give you the equivalent of x-ray vision, because you’re seeing not only your view, but also the view from other cars as well… We have to give ourselves every possible tool in the tool chest in order to try and solve this problem. So I think … saving spectrum for that use is also very important.”

In essence, Pratt distills a quite contentious and complex V2V debate into an argument for a government mandate for inter-vehicle communications. Such an argument is only consistent in the context of cellular-based solutions being considered as candidate alternative solutions for connecting cars to each other and infrastructure.

In the end, what emerges is a picture of ongoing confusion regarding the kind of help the automotive industry desires and the roll of Congress or even the U.S. Department of Transportation. It’s worth noting that the Federal Communications Commission is still testing the parameters governing spectrum sharing and an appropriate path forward. Testing of security protocols and standards for V2V are also ongoing.

The lack of a perspective or testimony from either Tesla Motors or Waymo is notable as is the lack of representation from state and local legislators and regulators and organizations advocating (both pro and con) on behalf of consumers – to say nothing of representatives of commercial trucking companies, rental car companies and taxi and limousine associations. In fact, the voices of consumer groups and employers are the ones most missed in this hearing.

If legislators could hear the demand side of the conversation more clearly it would clarify the confusion and contradictions currently ruling the space. Until these voices are heard, car makers will be left to their own aimless devices and regulators and legislators may well go awry creating delays and roadblocks or leading the industry down blind alleys.

Full video of the testimony can be found here: https://www.c-span.org/video/?423974-1/auto-industry-executives-testify-selfdriving-cars


Another Live Event at Samsung!

Another Live Event at Samsung!
by Daniel Nenni on 02-25-2017 at 7:00 am

Last week Samsung hosted the GSA Silicon Valley “State of the Industry” Meet-up which was well attended by the semiconductor elite, myself included. The agenda started with an update on the semiconductor industry outlook followed by deep dives into Automotive, IoT, Artificial Intelligence, and Cybersecurity all of which are tracked quite closely on SemiWiki.com. It was a very informative session with great food and networking. Thank you GSA and special thanks to Samsung for hosting the event at their new HQ in San Jose.

Next week Samsung is hosting another live event with eSilicon and Rambus, space is limited so register now. I’m not acquainted with two of the speakers, Mohit Gupta and Dr. Kang Sung Lee, but I do know Bill Isaacson and can tell you he is an excellent no nonsense speaker. Bill started the first half of his 20 year semiconductor career at LSI Logic and the second half at eSilicon, so Bill knows the ASIC business, absolutely.

Advanced ASICs for the Cloud-Computing Era:
Succeeding with 56G SerDes, HBM2, 2.5D and FinFET

A dramatic increase in network bandwidth and cloud-computing infrastructure is on the way. Fueled by applications such as deep machine learning and massive data volumes from a connected world, the performance demands of ASICs to support these new applications are daunting.

Join eSilicon, Rambus and Samsung Foundry for an overview of the advanced technologies being deployed to address these challenges. We’ll discuss HBM technology and the associated PHY, high-speed SerDes technology, 2.5D integration, high-performance ASIC design, interposer/package design and the manufacturing and packaging technologies available to address this class of FinFET-based designs.
There is no charge for this live event.

Registration closes at noon Pacific time on Friday, March 3, 2017. For security reasons, only those who have pre-registered may attend.

Agenda
3:30 – 4:00Check in at the South Lobby reception area
4:00 – 4:15Welcome, overview of HBM/2.5D market and applications
4:15 – 4:45 Enabling IP
4:45 – 5:15 ASIC, interposer and package design
5:15 – 5:45 Fabrication and packaging
5:45 – 6:00 Panel discussion
6:00 – 7:00 Networking reception; drinks and light hors d’oeuvres

Event Details
Wednesday, March 8, 2017
4:00-7:00 PM
Samsung Semiconductor
3655 N First Street
South Lobby
Palace Auditorium
San Jose, CA 95134

Register>>>

SPEAKERS

eSilicon
Bill Isaacson manages all aspects of strategic account relationships for eSilicon. Previously, he managed advanced development for eSilicon’s custom design initiatives. Prior to this position, he ran the customer solutions engineering function at eSilicon for eight years. Bill was previously at LSI Logic, where he was a design center manager. Bill received his BS/EE degree from the University of Illinois at Urbana-Champaign.

Rambus
Mohit Gupta is currently a senior director of product marketing in the Memory and Interfaces Division at Rambus managing the SerDes IP portfolio. Prior to joining Rambus in 2015, Mohit has led multiple IP development, application engineering and pre-sales teams at Open-Silicon, Infineon Technologies and ST Microelectronics. Mohit holds BE, MS and MBA Degrees from premier universities in India.

Samsung Foundry

Dr. Kang Sung Lee is currently a principal engineer in Samsung Foundry marketing. He is responsible for defining and promoting Samsung Foundry technology offerings for customer product needs. Dr. Lee joined Samsung in 2007 as a customer engineer and supported worldwide customers in multiple market segments, from mobile AP, GPU, FPGA, networking to cognitive computing and etc.


PowerTree — a data repository and simulation platform for PCB power distribution networks

PowerTree — a data repository and simulation platform for PCB power distribution networks
by Tom Dillinger on 02-24-2017 at 12:00 pm

The difficulty of managing the power domains on a complex SoC led to the development of a power format file description, to serve as the repository for data needed for functional and electrical analysis (e.g., CPF, UPF). Yet, what about complex printed circuit boards? How can the power domain information be effectively represented (for one or more boards), and used as the repository for subsequent analysis? How can electrical analysis be pulled “into the design phase”, reducing the PCB optimization effort? How can the PCB power format information be derived automatically, and submitted for simulation?

Specifically, the issues with accelerating power integrity analysis for a complex power distribution network (PDN) include:

  • PDN connectivity is difficult to visualize, as it is embedded in the detailed schematics
  • strong version management of the PDN and component model library is required during the design phase, enabling a quick comparison highlighting differences in the PDN design of successive versions
  • initial pre-layout simulation support is needed, to help identify any gross errors before layout
  • simulation set-up is a pain

Cisco recently shared an example of the magnitude of the power domain topologies from a current product (link below) — e.g., ~20 power rails, ~250 components, and ~500 power nets (including nets around filter components). Specifically, the system-level board design includes a wide diversity of component types, with varied constraints on the allowed I*R (DC) supply voltage drop and component power pin impedance profile versus frequency (AC, with optimized decoupling capacitance sizing and placement).

I recently had the opportunity to chat with Brad Griffin, Product Management Director, Custom IC & PCB Group at Cadence. Brad described how Cadence is helping address the requirement to bring PI analysis forward into the design flow. “With the assistance of customers like Cisco, we have developed an advanced feature in our recent Sigrity Power Integrity and OptimizePI toolset. The PowerTree repository is a unique method to capture and visualize complex board design information and related component model constraints.”

Setup of the PowerTree configuration is straightforward — a screen shot of the “Build Power Tree” dialog is included below.

A screen shot of the PowerTree application representing a complex PDN is included below.


The component bill-of-materials and connectivity netlist is derived from Cadence Allegro. A single view consolidates data across a potentially large number of schematic pages. Component models provide both electrical behavior and verification checking limits. Designers can include additional design constraints and component model data in the PowerTree repository.

Brad highlighted, “From the PowerTree environment, PCB designers can quickly generate and run DC analysis simulations in Sigrity PowerDC, initially from the schematic, and then with detailed layout parasitics. After optimizing the DC profile, the design is then provided to the power integrity expert for decap selection and positioning to optimize the frequency-dependent power impedance profile. The PI expert receives a higher quality design, to start their work with Sigrity OptimizePI. “

Brad and I both acknowledged that power integrity experts are a precious resource, and always overworked. 🙁 The opportunity for board designers to quickly derive and view the power topology and component data using the Sigrity PowerTree feature, then simulate to ensure correct DC margins are provided, will be a tremendous aid to the PI analysis activity.

For more info on the new Sigrity PowerDC and PowerTree features, please follow this link.

For additional insight into the collaboration with Cisco and Cadence on PowerTree, a link to a recent joint presentation at CDNLive is here.

-chipguy


Searching for Extraterrestrials

Searching for Extraterrestrials
by NicolasWilliams on 02-24-2017 at 7:00 am

Since the beginning of time, people on Earth have peered into the night sky, pondering if they were alone in the universe. Today, we have a large group of scientists that are working to answer that question. The precision required for their search often depends on the performance of a key piece of technology – the analog-to-digital converter (ADC).
Continue reading “Searching for Extraterrestrials”


New Protocol (NB- IoT) Requires New DSP IP and New Business Model

New Protocol (NB- IoT) Requires New DSP IP and New Business Model
by Eric Esteve on 02-23-2017 at 12:10 pm

If we agree on the definition of IoT as a distributed set of services based on sensing, sharing and controlling through new nodes, we realize that these nodes are a big hardware opportunity. The chip makers and IP vendors have to create innovative SoC, delivering high performance at low cost and low energy. Moreover, the new systems will have to integrate multiple sensors and stay in Always Alert mode.

The problem comes when you realize that no processor core is ideally suited for all these 3 functions: sensing, computation and communication.

Sensing is going from voice/face trigger to biometric monitoring, indoor navigation to sensor fusion, and probably many more as we can be confident about the creating power of innovators. Computation is linked with maths: Digital Signal Processing, bit manipulation, floating point, encryption, security, etc. when communications is based on protocol standards like NB-IoT, Wi-Fi Halow, GNSS, BLE or Zigbee.

Because every IoT application is different and because the above list is pretty long, no processor cores are ideally suited for all 3 functions, sensing, computing and communicate. Cadence, and more precisely Tensilica team developing the highly configurable DSP IP core, has brainstormed and realize that cost and ease of use are driving the desire for single core for IoT SoCs. The next step has been to develop the new Fusion F1 DSP core, able to compute, support sensing and communication protocols.

The Fusion F1 DSP core is above pictured and the green box is the core basis. Because Tensilica want to address various applications, IoT and even more, the flexibility has been the driver for the architecture definition. The 7 blue boxes (FPU, AVS, AES-128, 16-bit Quad MAC, Viterbi, Soft Bit Demap and Bit Manipulation) are proposed as pre-verified and proven option. A chip maker can really optimize the DSP core definition in respect with the real needs of the application, and minimize the DSP area and power consumption.

This flexibility is added to the natural DSP flexibility, as you can use the same core to support the communication protocol (the modem) when active, then switch to support sensor fusion when needed. This strategy is also good for power consumption optimization, which is key for this type of application.

This Fusion DSP can target technology nodes from 55 nm, 40 nm, 28 nm to 22 FD-SOI (all of these sounding good for IoT applications), and obviously smaller nodes when designing to support very complexes platforms.

If you take a look at the above picture, it’s clear that the Fusion F1 DSP is architecture to efficiently support the modem function in wireless communication, thanks to the selection of Advanced Bits Ops., Viterbi or Soft Bit Demap., but also sensor fusion and audio/voice/speech. When you look at the end products, wearable, smart home or automotive, you can guess that the majority of these applications will integrate one or more wireless communication protocols.

A good way to introduce the very interesting partnership built by Cadence with Commsolid, providing ultra-low power solutions for standardized wide-area networks (WAN) like Cat-NB1 (NB-IoT) and 5G IoT in the future. The NB-IoT protocol should see a large adoption in the applications requiring ultra-low power but low modem bandwidth (< 100 kbps), which fit well with the specification of wearable and most of IoT systems.

Commsolid has built an ultra-low power baseband IP, the CSN130, designed for the new NB-IoT standard specified in 3GPP Release 13. The CSN130 is a complete pre-certified NB-IoT baseband, consisting of hardware and software. In fact, the physical layer implementation, the modem, target the Fusion F1 DSP and this explain why this partnership is beneficial for a customer needing fast TTM at no risk, as the Commsolid NB-IoT baseband IP is pre-certified, using Tensilica DSP.

As such, the Cadence/Commsolid partnership is a very good solution to develop an application supporting NB-IoT wireless protocol, but the story doesn’t stop here, as it goes up to the business model. Commsolid has the right to license the complete solution made of the CSN130 IP AND the Fusion F1 DSP from Cadence to a customer asking for business simplification (only one license agreement make the project manager life easier, as far as legal and business negotiation are concerned).

The adoption of emerging IoT technology and innovative wireless protocol like NB-IoT going together with simplified business model should make the solution more attractive.

Last but not least, the FUSION F1 DSP core can be power conscious AND performant, with 4.61 CoreMark/MHz, a very good figure in this product category.

The following link to more information about the Fusion DSPs: https://ip.cadence.com/ipportfolio/tensilica-ip/fusion

By Eric Esteve fromIPnest

These design-win with ForteMedia, Realtek or CyWeeMotion sensor fusion demonstrate that the Fusion F1 is flexible, appropriate for voice processing solutions and IoT modems:

Realtek

Fortemedia

CyWeeMotions


What You Don’t Know about Parasitic Extraction for IC Design

What You Don’t Know about Parasitic Extraction for IC Design
by Daniel Payne on 02-23-2017 at 7:00 am

Out of college my first job was doing circuit design at the transistor-level with Intel, and to get accurate SPICE netlists for simulation we had to manually count the squares of parasitic interconnect for diffusion, poly-silicon and metal layers. Talk about a burden and chance for mistakes, I’m so thankful that EDA companies have come to our rescue and have automated the extraction of parasitics that directly effect the quality of any digital or analog circuit performance in terms of speed, currents, power, IR drop and even reliability. If you were to just simulate your circuits without parasitic values, then the results are going to be quite a bit different from silicon, so it really makes sense to do SPICE simulations with extracted parasitic values in order to predict how silicon will behave.

Silvaco is an EDA vendor with a growing list of tools for IC design as shown in this tool flow diagram:

To learn more about parasitic extraction from Silvaco you should consider attending their webinar on March 23rd from 10AM – 11AM PST. The three tools shown under Extracted Netlist Analysis & Reduction will also be discussed in the webinar. The presenter for the webinar is Jean-Pierre Goujon, an AE Manager based in France, and he previously worked at Edxact, a company acquired by Silvaco in June 2016.

If you do IC design with SPICE, or support CAD tools in a flow and work with PDKs, then this webinar is sure to answer your questions on what Silvaco has to offer. Registration for the webinar is here.

Parasitic extraction is a mandatory step for physical design sign off, and at advanced nodes, parasitics substantially impact the behavior of circuit design. Any analysis must consider the interconnect parasitic effects to produce meaningful and realistic results. In this webinar, we will review a flow that can qualitatively and quantitatively compare two extraction flavors for the same design. We will then present an in-depth exploration of exactly where the differences are coming from. At the end of this webinar, switching between different layout parasitic extraction tools, calibrating settings to a new technology node, qualifying PDK updates etc will no longer be a bottleneck for CAD teams.

What attendees will learn:

  • Powerful and accurate methods to qualify and quantify different parasitic extraction methods
  • How to recognize traps in the flow and possible work-arounds
  • How to explore parasitics and analyze what is different and where

PRESENTER:
Mr. Jean-Pierre Goujon is Application Manager for Silvaco France. He is responsible for customer technical support for EDA products, with a specific interest in parasitic analysis and reduction products. Prior to this position, he has been AE manager for Edxact for 12 years and had various AE responsibilities at Cadence, Simplex and Snaketech mostly in the field of parasitic extraction.

Mr. Goujon holds a BSc in EEE from Robert Gordon University, Aberdeen, UK and a MS in EEE from Ecole Supérieure de Chimie, Physique, Electronique de Lyon, France.

Related Blogs


Power and Performance Optimization for Embedded FPGA’s

Power and Performance Optimization for Embedded FPGA’s
by Tom Dillinger on 02-22-2017 at 12:00 pm

Last month, I made a “no-brainer” forecast that 2017 would be the year in which embedded FPGA (eFPGA) IP would emerge as a key differentiator for new SoC designs (link to the earlier article here).

The fusion of several technical and market factors are motivating design teams to incorporate programmable logic functionality into their feature set:

  • the NRE and qualification cost of a new SoC design is increasingly significantly, at newer process nodes; a single part number that can adapt to multiple applications is a significant cost savings
  • many algorithms can be more efficiently implemented in logic than using code executing on a processor core; the flexibility of reconfiguring the algorithm logic to specific market requirements enables broader applicability
  • new (on-chip and external) bus interface specifications are emerging, yet final ratification is pending — a programmable logic IP block affords adaptability

Yet, field programmable logic implementations are often associated with higher power dissipation than cell-based logic designs. And, many of the applications for eFPGA technology are power-sensitive.

To better understand how eFPGA IP will address power optimization, and how that compares to logic library design, I reached out to Cheng Wang, Senior VP of Engineering at Flex Logix Technologies Inc., for his insights.

As with conventional logic designs, Cheng indicated that addressing power/performance for eFPGA IP is a multi-faceted task. Architecturally, the programmable logic fabric needs to define the look-up table (LUT) size that best fits the target applications. From a circuit perspective, the LUT array implementation needs to leverage all the available foundry technology features, in a manner similar to standard cell library offerings, but with specific consideration for eFPGA circuits.

Cheng highlighted, “Customers are seeking the low-power and ultra-low power foundry offerings, such as TSMC’s 40LP/ULP. These processes offer a wide supply voltage range and a variety of device threshold voltage variants, such as SVT, HVT, and UHVT (in 40ULP). For an eFPGA block we offer customers the flexibility in device selection for their application, to which we have incorporated additional power optimizations. For example, the eFPGA configuration storage bits always utilize low-leakage devices, which corresponds to ~30-40% of the block area. We have included support for a local body-bias voltage. And, perhaps most significantly, the eFGPA IP block support full power-gated operation.”

The figure below depicts the power gating microarchitecture.

The LUT cell includes state-retention when power gated, also utilizing low-leakage devices to minimize quiescent dissipation. A single block input pin defines the sleep state — the necessary internal turn-on/turn-off signal ramp to control current transients is engineered within the block itself.

In short, power optimization for an eFGPA IP block involves many of the same trade-offs as a cell-based design — e.g., supply and bias conditions, device threshold selection. Some library cell-based logic implementation flows support biasing and power gating, with additional verification and electrical analysis steps. The eFGPA IP includes the additional design engineering within the LUT and configuration circuits for these power optimizations — which are available across the range of eFPGA array sizes.

As an aside, Cheng spoke briefly about the verification of these power optimization features. Shuttle testsites are used to confirm and qualify the silicon eFPGA array implementations. Qualification is performed over the supply voltage ranges supported by the foundry (e.g., 0.6V – 1.0V for TSMC’s 16FFC).

Finally, we chatted about a different class of eFPGA customers, for which performance, not power dissipation, is the key requirement. Chung characterized this market segment as, “We have customers who are strictly seeking the fastest implementation available, for applications such as user-defined networking. The configurability of an eFGPA array enables them to incorporate various packet-processing algorithms. Architecturally, for these designs, the LUT expanded from 4 to 6 logic inputs — ideally, these algorithms can thus be realized in fewer logic stages. In several design examples we’ve reviewed with customers, more than 90% of the LUT’s do utilize more than 4 logic inputs. Correspondingly, the full eFPGA array architecture needed to support a larger number of block I/O’s.”

Cheng continued, “From a technology and circuits perspective, these customers are designing in FinFET technologies, such as TSMC’s 16FF+/FFC. The circuit drivers in the 16nm design are larger. For performance, we have implemented a clock distribution mesh(as opposed to a tree), which is expandable across the range of eFPGA array sizes and aspect ratios. The device selection is available in SVT and LVT variants. As an IP provider, we work with the foundry to utilize the ‘converged PDK’ metal stack, which the foundry’s customers are adopting for the lower metal levels. Within this metal stack definition, our LUT circuits and switch fabric optimize metal linewidth/space dimensions for performance.” (The Flex Logix EFLX-100 utilizes metals M1-M5, the EFLX-2.5K utilizes M1-M6.)

For these performance-driven customers, the tradeoff in area, performance, and power in the eFPGA design suggests a low value for the power gating and body biasing features included in the older process node implementations.

I learned that eFGPA array design is both similar and, in many ways, different than cell library-based logic design, when considering power and performance target optimizations. The synthesis of RTL functionality into the target logic offering is similar, to be sure. And, foundry process technology device offerings are leveraged in the logic circuits. Yet, the eFGPA offering from Flex Logix is more than a logic block with programmable functionality — it has been engineered to integrate specific power/performance features that customers expect from a complex IP offering.

For more information on the power/performance capabilities of the FPGA technology from Flex Logix, here are a couple of links as starting points: TSMC 40LP/ULP offering TSMC 16FF+/FFC offering

-chipguy


Zero Power Sensing

Zero Power Sensing
by Bernard Murphy on 02-22-2017 at 7:00 am

We’ve become pretty good at reducing power in IoT edge devices, to the point that some are expected to run for up to 10 years on a single battery charge. But what if you wanted to go lower still or if, perhaps, your design can’t push power down to a level that would meet that goal? One area in systems where it can be challenging to further reduce power is in sensors, since these need some level of standby current to be able to sense and wake other circuitry.

Some of the lowest standby currents I have seen are ~0.3uA which is impressive (one case I found is able to support a sensor for up to 20 years on a coin cell battery) but maybe not good enough in some applications where you might need to support an array of sensors; even a 3×3 array would reduce that inspiring performance to just over 2 years, which may not be adequate for an infrequent service application.

A team at the University of Bristol in the UK have improved on this by reducing standby current to zero. They have built a voltage detector IC, called UB20M, which can use the intrinsic power generated by the sensor (for certain classes of sensor) to turn on and enable the rest of the system. They mention wireless antennas, infrared diodes, piezoelectric accelerometers, and other voltage-generating sensors as compatible with this device. The sensor must generate a ~650mV signal, but with only a few picowatts of energy to activate the UB20M. The power switch following the UB20M (to turn on power for the rest of the system) will naturally have some level of leakage (they mention 100pA in their test cases) which could perhaps be further optimized in commercial applications but is still 3 orders of magnitude better than commercial alternatives today.

So that array of sensors could become a negligible factor in the battery life of the parent IoT device. Other factors, probably leakage, would dominate. Not bad. The team is understandably cagey about how the device works since the design is patent pending in the UK. They are offering samples for testing. You can read more about the UB20M HERE.

More articles by Bernard…