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MWC 2017: The 5G Emperor’s New Clothes

MWC 2017: The 5G Emperor’s New Clothes
by Roger C. Lanctot on 03-03-2017 at 10:00 pm

A very odd phenomenon is sweeping the automotive and wireless industries and was in full flower at MWC 2017. The onset of 5G connectivity has wireless carriers excited over the high bandwidth, low latency and high availability applications inherent in this new network technology – to say nothing of network slicing for targeted applications. But the application segments promising the greatest growth lie outside the segment garnering the largest increase in connections.

Connected cars are delivering new network connections for carriers such as AT&T and Vodafone, among a few fortunate competitors, beyond the wildest expectations of even the most ardent IoT enthusiasts. Smarthomes and wearables may be hot, but the connected car is at the core of network connection expansion.

The only problem is that connected vehicles remain an elusive source of revenue. After paying the wireless and the cable bill – some of which consumers have been able to combine – there is little patience for a separate bill for the connected car! Most of the diagnostic and remote control (remote start, door unlock) applications for connected cars require minimal bandwidth.

The problem is simple to explain. There is nothing natural about connecting a car and for car makers it’s a nightmare. And, yet, consumer interest in car connectivity is high, according to Strategy Analytics’ own consumer survey and focus group data.

Twenty years ago General Motors created a compelling application in automatic crash notification (ACN) which the company was able to leverage to differentiate its cars, increase sales and drive subscription revenue. In the very earliest days of OnStar, dealers were free to charge extra for the feature – something which was quickly nipped in the bud.

Masked by GM in the deployment of OnStar was the sausage-making ugliness of wireless connections, network reliability, battery consumption, network credentials, and, fundamentally, consumer expectations – to say nothing of the potential privacy violation and cybersecurity implications. Consumers don’t understand the complexities of vehicle connectivity – they just want it to work the way their mobile phone works.

For car makers, introducing a wireless connection in the car with an emergency response responsibility carries heavy liability requirements to this day. Before any consumer has tapped into an embedded modem-based family finder app or Wi-Fi access, the car maker – in partnership with the carrier – must sell its soul as to the reliability of the on-board system in the event of a crash.

The onset of smartphones tamped demand for ACN, but ubiquitous connectivity introduced the concept of apps in the dashboard, streaming audio, Wi-Fi, digital assistants, artificial intelligence and contextual awareness. Car companies quickly came to realize that location itself was a valuable and potentially monetize-able proposition.

Now autonomous driving has usurped the attention of auto makers, shifting the focus to sensors and on-board systems capable of recognizing environmental elements in real time. Carriers are keen to capitalize on the autonomous driving craze and the billions of invested dollars, but the market leaders in self-driving technology have thus far eschewed connectivity.

Waymo, Uber, Tesla and a dozen or more startups have thus far treated wireless connections as irrelevant. In spite of the indifference of self-driving system developers, wireless carriers and infrastructure suppliers have soldiered on with tests and prototypes and proofs of concepts.

The more immediate concern of the wireless industry vis-à-vis auto makers is the emergence of V2V communications via dedicated short range communications (DSRC) technology. DSRC-based V2V promises an alternative form of vehicle connectivity capable of delivering content and safety.

Unfortunately for DSRC, commercial applications for the technology have been few and far between and so it has become almost entirely reliant on government mandates and funding – with the exception of companies such as Veniam that have focused on enterprise applications for the technology. In essence, wireless carriers have been forced into making the case for 5G based on it serving as an alternative to DSRC.

To focus 5G on safety applications is to remove the revenue opportunity. The reality is that 5G will enable new customer service value propositions integrating virtual and augmented reality to the process of building and servicing vehicles and enhancing driving. The first hint of this brave new driving world was exhibited by Audi demonstrations at MWC showing “see through” technology based on streaming video from one vehicle to a following vehicle and the same application shown in the Qualcomm and Orange booths.

Of course, it makes no sense for a driver to observe the video – in real time – projected to his or her following vehicle. The message behind the demonstration was that 5G technology can deliver this level of low latency performance via the embedded connection in the car.

Will 5G enable collision avoidance? It’s possible. 5G connectivity will enable a 5G-equipped car to avoid a collision with another 5G-equipped car via inter-vehicle communications – but that event (momentous indeed!) is years away.

For now, vehicle-to-vehicle connections are solely built around alerts and require driver intervention to prevent a crash. So, sadly, the 5G hype for automotive applications at MWC was somewhat undermined by both solely sensor-based self-driving technology and the current conceptual limitations of V2V.

Where both LTE and 5G can have an impact is in leveraging multiple layers of vehicle connections for a more comprehensive real-time view of vehicle movements in space particularly in urban settings. Collision avoidance and self-driving systems taking advantage of these connections and data processing – including neural networks and machine learning – are only currently deployed in test mules and prototypes too expensive for mass deployment.

The sad truth is that vehicle connections are critical to carrier growth, but revenue growth from automotive comparable to mobile video or online gaming will be elusive in the short-term. General Motors’ Global Connected Consumer division may be on the right track in enabling unlimited wireless data plans (this week). The key to success remains making it as simple and easy as possible for the consumer to add their car to their existing wireless plan. That will be a first good step forward – GM is in the lead here as well.

Strategy Analytics’ perspective on MWC 2017: tinyurl.com/zyejk3c#MWC2017Alters Connections Between Carriers and Car Companies


SPIE 2017: EUV Readiness for High Volume Manufacturing

SPIE 2017: EUV Readiness for High Volume Manufacturing
by Scotten Jones on 03-03-2017 at 12:00 pm

The SPIE Advanced Lithography Conference is the world’s leading conference addressing photolithography. This year on the opening day of the conference, Samsung and Intel presented papers summarizing the readiness of EUV for high volume manufacturing (HVM). In this article, I will begin by summarizing the EUV plans of the four leading logic producers, I will then touch on some general observations over several years of the conference, I will discuss the Samsung and Intel papers, some additional observations and then conclude with the prospects for EUV in HVM.

Continue reading “SPIE 2017: EUV Readiness for High Volume Manufacturing”


TSMC Design Platforms Driving Next-Gen Applications

TSMC Design Platforms Driving Next-Gen Applications
by Daniel Nenni on 03-03-2017 at 7:00 am

Coming up is the 23rd annual TSMC Technology Symposium where you can get first-hand updates on advanced and specialty technologies, advanced backend capabilities, future development plans, and network with hundreds of TSMC’s customers and partners. This year the Silicon Valley event kicks off at the Santa Clara Convention Center. For more information the Symposium landing page is HERE but first lets talk about design platforms.

The semiconductor design ecosystem, semiconductor companies, and TSMC are uniting around new methods to overcome chip design challenges by integrating the right tools and technologies into customized, powerful design platforms.

It is becoming apparent that the next growth driver for the IC industry is “ubiquitous computing” where data is generated, collected, filtered, processed and analyzed not just in the cloud or network, but also locally in smart devices all around us. To help its customers seize these opportunities, TSMC and its Open Innovation Platform® partners have developed four application-specific platforms for the next generation of high-growth applications: Mobile, High-Performance Computing (HPC), Automotive, and Internet of Things.

Smartphones occupied much of the last decade’s engineering resources and continue to grow at a healthy clip – Gartner reports 1.5 billion units sold in 2016 – pushing advanced semiconductor technology and design to new heights. However, it is now clear that mobile was just the beginning of a new silicon revolution as industry focus rapidly shifts to the optimization of advanced technology for automotive, HPC and IoT.

In mobile, growth in silicon content per device is driven by features such as dual camera, fingerprint sensors, AR/VR and migration to 4G, 4G+ and 5G. For HPC, artificial intelligence and deep learning will have significant impacts on many industries including healthcare, media and consumer electronics. On the automotive front, ADAS, night-vision, and smart energy for hybrid and electric vehicles promise to make driving more convenient, safe and green. Finally, IoT opens up a multitude of opportunities for ICs that will transform the way we live and improve how societies can be organized and managed through improved efficiency and pervasive communication.

Dr. Cliff Hou, TSMC Vice President of Research & Development, Design and Technology Platform, has pioneered the evolution of design ecosystems to design platforms and the application-specific design enablement that addresses distinct product requirements of each of these four segments. Dr. Hou asserts that application-specific design platforms deliver greatly enhanced solutions that simplify highly complex design activity, reducing the time and effort needed to bring products to market for these high-growth opportunities.

Each TSMC process and packaging optimized design platform includes reference subsystem designs to facilitate innovation; processor cores (CPU, GPU); standard interfaces, Analog/Mixed Signal IP; foundation IP that includes standard cells, SRAM and I/O; design flow, design guideline and EDA tools; and PDK and Tech Files. The goals and readiness of each platform is summarized below:

If you were lucky enough to get a golden ticket to this event it would be a pleasure to meet you. SemiWiki bloggers Tom Dillinger, Tom Simon, and myself will be there blogging live and I will be giving away signed copies of our book on The History of ARM “Mobile Unleashed” in the Solido booth during the lunch break. If you would like to do a meet and greet and get a free book stop on by and say hello.

About TSMC
TSMC created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 470 customers and manufactured more than 8,900 products for various applications covering a variety of computer, communications and consumer electronics market segments. Total capacity of the manufacturing facilities managed by TSMC, including subsidiaries and joint ventures, reached above 9 million 12-inch equivalent wafers in 2015. TSMC operates three advanced 12-inch wafer GIGAFAB™ facilities (fab 12, 14 and 15), four eight-inch wafer fabs (fab 3, 5, 6, and 8), one six-inch wafer fab (fab 2) and two backend fabs (advanced backend fab 1 and 2). TSMC also manages two eight-inch fabs at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company Limited, In addition, TSMC obtains 8-inch wafer capacity from other companies in which the Company has an equity interest.

TSMC’s 2015 total sales revenue reached a new high at US$26.61 billion. TSMC is headquartered in the Hsinchu Science Park, Taiwan, and has account management and engineering service offices in China, Europe, India, Japan, North America, and, South Korea.


Wireless 5G BTS Need Super DSP core… CEVA XC-12

Wireless 5G BTS Need Super DSP core… CEVA XC-12
by Eric Esteve on 03-02-2017 at 10:00 am

Once upon a time, one wireless base station (BTS) was expected to support one, and only one wireless protocol, like GSM (2G), first deployed in Finland in 1991, or CDMAOne (also 2G) developed by Qualcomm and released through the TIA in 1995. Just a precision: the GSM modem speed was reaching 14.4 Kbps (with only 9.6 Kbps usable by end-user) as well as the CDMAone competing technology…

Such a modem was already supported by a DSP core (Teak from CEVA or TI’ C54x), but you have now to figure out what kind of DSP is needed today to support the following requirements:

Facilitate aggregation of various technologies such as LTE, LTE-A PRO, WiFi 11ac/ax, WiGig…
Reduce Latency (to best support V2X, VR or mobile gaming)
Support huge numbers of users and IoT devices at once (you can translate it into supporting massive MIMO technology)
Enables mission critical usage such as Cellular V2X, eHealth and industrial IoT (reliability and encryption)

supporting modem functions is still part of this DSP charter, but the speed of modems are now ranging from 20 MHz to 800 MHz, depending on the protocol!

In fact, the above description if for such a wireless standard (5G) is so advanced compared to previous generation that it needs a completely new processing approach to ensure its success…

In this picture, the key-word is aggregation, as the CEVA XC-12 targets the base station segment rather than the smartphone irself, where the CEVA XC-4500 is powerfull enough to support 5G modem gigabit requirements. In the BTS, multiple multi-gig technologies are co-existing and some of the protocols to be supported by the DSP are still to be finalized. In this case, the DSP based approach is certainly this providing the highest flexibility to implement the modem baseband. As well, it’s likely that the digital RF will be implemented through FPGA technology.

On top of increased flexibility, another strong benefit going with using the CEVA XC-12 is the reuse capability. Building a BTS is costly, as OEM have to target high performance (IP and technology node) for the highest possible number of end-users. Selecting the XC-12 allows to this OEM to add new H/W while keeping in place the previously installed system.

Let’s take a look at the new computing challenges associated with 5G adoption:

·Computational complexity is very high: higher throughput, reduced latency and massive MIMO usage
·Need for minimum mean square error (MMSE) equalization of huge matrices requiring very efficient matrix operations
·High precision to handle large matrix inversion is essential for Equalization and Beamforming calculation
·Data symbol demodulation as high as 256-QAM if not 1024-QAM!
·The larger bandwidth, modulation and MIMO dimensions automatically leads to much higher bitrates

The CEVA XC-12 architecture has been specifically developed to address all the above listed challenges. Taking the CEVA XC-4500 as a reference, here are some improvments on the symbol plane. 128-MAC used to boost 8×8, 16×16 or 32×32 MMSE-IRC by 4X factor and 20-bit Pseudo-FP to boost Massive-MIMO by more than 20 dB. FFT automatic scaling improving precision by 15 dB enabling 4X performance…

At this stage, I suggest you to attend to the Webinar to be hold on March, 29[SUP]th[/SUP] 2017How CEVA-XC12 solves the daunting computing and latency challenges of 5G NR” (you will find the link at the bottom of this blog).

Each of the four vector engines can run 32 MAC per cycle, for a total of 128 MAC per cycle, and supports 2048-bit load and store, still per cycle. The high precision fixed and floating point arithmetic has been defined for up to 256×256 matrix processing (remember the MMSE equalization requirement). Vector engines are supporting high precision non-linear ISA and 256, or even 1024 QAM demodulation ISA.

The scalar unit, completely new and based on the new CEVA-X framework (CEVA-X1, CEVA-X2), is designed for Multi-RAT systems and management of massive number of users to best support 5G BTS. Each of the four Scalar Processing Unit (SPU) can optionally integrate a Floating Point Unit (FPU).

Compared with the CEVA-XC 4500 scalar unit, the new scalar unit offers 40% EEMBC improvement (the EEMBC CoreMark benchmark reflects real-world applications and tests a processor’s basic pipeline structure, as well as the ability to test basic read/write operations, integer operations, and control operations. It tend to replace the old Dhrystone MIPS benchmark).

As the CEVA-XC 12 counts 4 SPU (and 4 VPU), the CEVA-XC 12 provides a 4X improvment for a complete BTS NR PHY. This SPU provides full RTOS support, offering ultra fast context switch.

The above picture illustrate how the CEVA-XC 12 is implemented. This Cluster Architecture allows the CEVA-X2 to control the complete system. The four processor cores are connected by paires (Core 0 with Core1, Core 2 with Core 3) by using point to point Fast Interconnect busses (FIC Master or Slave). Each paire is processing in parallel the same task and because of the point to point (and fast) interconnect, the latency is greatly improved, which is a condition to efficiently address the Virtual reality (VR) or Vehicule to Everything (V2X) applications.

To conclude, let’s add that the CEVA-XC 12 has been implemented in 10 nm technology and can reach up to 1.8 GHz in this case. For Multi-RAT control plane, the core delivers 4.4 CoreMark/MHz, while consuming 50% less than the CEVA-XC4500.

You will certainly learn and benefit from the webinar to be hold on March, 29[SUP]th[/SUP] 2017:
How CEVA-XC12 solves the daunting computing and latency challenges of 5G NR
Register at:

http://go.ceva-dsp.com/Webinar-XC12-29-3-17_1-LP.html

Product Brief:
http://www.ceva-dsp.com/assets/docs/downloads/CEVA-XC12-Product-Brief.pdf

Landing page url:
http://launch.ceva-dsp.com/CEVA-XC12/

Product page url:
http://www.ceva-dsp.com/CEVA-XC12


By Eric Esteve from IPnest


Something New for Semiconductor Parametric Testing

Something New for Semiconductor Parametric Testing
by Daniel Payne on 03-01-2017 at 7:00 am

The familiar maxim that “time is money” certainly typifies our semiconductor industry where the mass production of chips, boards and systems helps to power our global economy and ever-increasing standard of living. The foundries that manufacture chips have to ensure that the process technology is in fact producing silicon that is within spec, so they have to test the IC products, both parametrically and functionally. One vendor making inroads in this vital parametric test area is called Platform DA, and I’ve just learned about their new FS series of products that include both hardware test instruments and unique software tools to provide some major benefits:

[LIST=1]

  • Speed: faster measurements mean more cost-effective measurements, thereby keeping pace with the effects of increasing process variability and increasing volume of wafers and chips.
  • Integration: comprehensive solution that includes the hardware instruments, test fixtures, test control and data management software, as well as modeling and simulation tools, all from a single vendor.
  • Flexibility: modular and expandable test solution that can be configured for all parametric tests, including IV, CV and noise measurements.
  • Usability: user friendly hardware and software combination that works out of the box with the instruments as a ‘Plug and Play’ solution.

    So what are the components of this FS series of products?

    First up is something called a Source Measure Unit, or SMU, which is the hardware used to test for voltages and currents in semiconductor devices. National Instrument manufactures the SMU hardware and Platform DA optimizes it for sensitivity and speed by leveraging their own proprietary hardware and Artificial Intelligence (AI) algorithms embedded in the proprietary software. There are two types of SMUs depending on the voltage range and current level measurements required:

    • FS380 – high precision SMU with 0.1fA sensitivity, 200V range 1A maximum.
    • FS360– medium precision SMU with 1fA sensitivity, 60V range, 3A maximum.

    Included with the FS380 and FS360 is software called LabExpress that really differentiates the PDA solution, with three useful features:

    • Ease of Test: includes Plug and Play features so that it takes a few mouse clicks to get your DUT measured.
    • Ease of Set Up: includes standard measurement routines for: MOSFET, BJT, C, R, D, Varactors, etc.
    • Optimization – includes proprietary AI algorithms that leverage machine learning to speed up the measurements by 2-10X without compromising the accuracy.

    If you need the most comprehensive and precise test for device characterization , rather than production test for process control, then consider adding the LabExpress Advanced Versionsoftware, which provide you with:

    • Wafer mapping support (compatible with Cascade and other semi-auto wafer probers)
    • Test Matrix support to enable suitable set up switching
    • More comprehensive IV and CV routines

    If you need to measure 1/f noise, either for noise characterization and modeling or for process control,, then just add the FS300 module to the FS380 or FS360 instruments, with the following specs:

    • ~5s measurement time
    • Bandwidth of 100KHz or 10MHz
    • Minimum noise resolution of 1e[SUP]-29[/SUP]A[SUP]2[/SUP]/Hz
    • Maximum output voltage of 100V
    • Maximum input current of 10mA
    • A high roll-off frequency
    • Accurate noise measurements for ultra-low currents
    • Multiple wafer mapping support
    • Optional Random Telegraph Noise (RTN) measurement support

    The final module that can be added on to the FS380 or FS360 is an instrument for measurement of inductance (L), capacitance (C) and resistance (R), or LCR. The LCR module is named the FS336 and the specs are:

    • Frequency range of 4Hz up to 8MHz
    • Internal voltage range from 10mv to 5V
    • Internal current range from 10uA to 100mA
    • External voltage bias range +-40V

    Uniquely, when the test is performed for device modeling you can also obtain a software module called MeQLab to the measurement hardware, and facilitate the extraction of suitable device models used in SPICE simulations. This combination of hardware, AI optimized test and model extraction software is a very differentiated combination.


    Summary
    I’m kind of impressed at how Platform DA has been able to focus on automating the semiconductor parametric test and characterization tasks through high-performance hardware and AI techniques coupled with easy-to-use software. These new products are a powerful combination of hardware and software that addresses a critical need of semiconductor engineers; while still being very cost-effective.

    I remember working at the number one IDM in the world as a circuit designer back in the 70’s and 80’s, and our new IC designs would live or die by the accuracy of the SPICE models and parameters being provided by the technology development group, so I know how critical it is to have accurate semiconductor measurements and to know if your process is staying within spec or drifting around. This is still very much true for modern process technologies and IC products.

    Related Blogs


  • An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes

    An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes
    by Scotten Jones on 02-28-2017 at 12:00 pm

    At the ISS Conference in January, An Steegen EVP of Semiconductor Technology & Systems at imec gave a talk entitled “Patterning Options for Advanced Technology Nodes”. I was present for her talk and had the opportunity to have a follow up interview with An.

    Continue reading “An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes”


    Simulation done Faster

    Simulation done Faster
    by Bernard Murphy on 02-28-2017 at 7:00 am

    When it comes to functional verification of large designs, huge progress is being made in emulation and FPGA-based prototyping (about which I’ll have more to say in follow-on blogs), but simulation still dominates verification activity, all the way from IP verification to gate-level signoff. For many, while it is much slower than hardware-assisted options, it’s easier to setup, easier to debug and easy to parcel out to simulation farms where you can run thousands of regression jobs in parallel.

    So Cadence made a shrewd move in acquiring Rocketick last year to provide acceleration help to the simulation-bound. But designs continue to get bigger and hairier so, according to Adam Sherer (Group Dir Marketing at Cadence), they’ve turned the crank some more, this time to an approach that has significant potential for scaling (tis the season for scalability roadmaps). The big news here is that this solution (Xcelium) is now able to efficiently split an Incisive simulation across multiple cores based on a careful examination of dependencies, and it does this in such a way that it can deliver significant acceleration over single-core simulation.

    This is no small feat. Many attempts have been made at parallel simulation but have struggled to deliver significant improvement because it has been so difficult to decouple activity in one part of a circuit from any other part. Breaking a circuit into pieces might speed up the pieces but you lose most of that gain in heavy inter-piece communication overhead (that’s my technical term for it). According to Adam, it’s the nature of the SoC verification problem that makes multi-core more effective in this case. Subsystem blocks in an SoC commonly operate concurrently, creating a high density of events which would slow down a simulator needing to run in a single core. But RocketSim can figure out intra/inter-block dependencies and partitions the circuit across cores so it can handle those higher event densities with greatly reduced impact (see the first table below). A similar argument applies to running multiple concurrent test scenarios (a common task in SoC verification); run-times are found to grow much more slowly with number of tests on multi-core than on single-core.


    Cadence has done quite a bit to justify a new brand on this creation. First, some applications still work best on single-core, such as IP verification with meaty UVM test-benches. These can’t be partitioned easily, yet Xcelium still offers ~2X speedup for IP sims on that single core over the previous generation. They’ve have also added an improved randomization engine which is both faster and delivers better distributions to help constrained-random reach coverage more quickly. Meanwhile SoC sims are running 5-10x faster on multi-core, again over prior generation performance. This should be of interest in many contexts, for example in DFT sims which tend to be very high activity, also for teams wanting to speed up multi-week gate-level sim signoffs.

    Another important point is that the solution is purely software and requires no special hardware. While RocketSim started with GPUs, it now runs on standard server platforms. Cadence apparently has recommended configurations for servers, but otherwise the solution is available to everyone who has access to datacenter-class servers. Which means it can help all simulation users, not just a privileged few.

    The cool thing about the multi-core part of this solution is that it scales with available cores. I’m sure you’re thinking – “nah, that’s not right – everyone knows that software parallelization improvements tail off as the number of cores increase”. But I think Cadence is onto something. Even as SoC sizes increase, they’re still made from IPs and even the big IPs are made from little IPs. Cadence won’t share the details of the partitioning algorithm (patent pending), so we’re left to speculate. Certainly the speedup they are seeing is significant, so it seems the IP/bus-based nature of SoC design must make the problem tractable if you have the right engine to attack it. Of course, nothing lasts forever; I’m sure performance will tail off at some point, but I think Cadence probably have quite a bit of runway with this solution.

    In the interest of full disclosure, Adam told me that they’re still working on bringing up multi-core support for VHDL. But you SystemVerilog and gate-level users are good to go right now.

    Naturally all of this isn’t just on Cadence’s say-so. They have endorsements from ARM and ST in their Xcelium press release. And I imagine a lot more simulation customers are going to be jumping on this bandwagon – who wouldn’t want faster simulation? You can learn more about the solution HERE.

    More articles by Bernard…


    Prototyping: Sooner, Easier, Congruent

    Prototyping: Sooner, Easier, Congruent
    by Bernard Murphy on 02-28-2017 at 7:00 am

    DVCon 2017 is a big week for Cadence verification announcements. They just released their Xcelium simulation acceleration product (on which I have another blog) and they have also released their latest and greatest prototyping solution in the Protium S1. This is new hardware based on Virtex UltraScale FPGAs on Cadence-designed boards, offering 6x higher capacity and an average 2x increase in performance. You can go from a single board at 25MG to a box at 200MG, and chain these together to get to 600MG. All that is important, but in one sense it’s not the most important aspect of this release. What’s really significant is getting to that power sooner, easier and with more confidence.


    I talked about this in an earlier blog on Aspirational Congruence, based on a discussion with Frank Schirrmeister (Sr. Dir of Marketing at Cadence) on the importance of pipelining software development with hardware development and the importance to that goal of closely coupling emulation and prototyping. The fast version of that discussion is this. Embedded software development needs to start much earlier than late design implementation, yet some development and validation needs more accurate modeling than is available in virtual prototypes. FPGA-based prototyping is the best way to get there, but lengthy (months) and complex prototype setup has discouraged starting before the design is locked down, because there’s no time to do over if the design changes. This doesn’t help accelerate software development.

    The way to cut this Gordian knot is to make prototype setup as fast and as hands-free as possible, while also closely tracking design verification models so you know that that behavior software developers will see on the prototype will be mirrored exactly in the behavior design verification engineers saw when that snapshot was taken. Frank gave me a prelude a few weeks ago to this concept of congruence between emulation and prototyping, meaning closely linked build, behavior and ease of transition between the two. Of course, this was a setup. He told me last week that Cadence are rolling out the solution this week at DVCon. Part of the solution is the Protium S1 but an equally important part is its close linkage with Palladium Z1 emulation.


    Let’s start with compile. The platforms share a common compiler to the point that what you build for the emulator is guaranteed to behave the same way on the prototyper. Which means that you can check behavior in faster-setup emulation before committing to a prototype build, and you can be confident there won’t be surprise mismatches between the two. Even the post-partitioning model can be taken to the emulator for further debug and validation.


    Then there’s place and route in each FPGA. Timing closure in FPGAs can be tricky which is one reason the S1 flow creates clocks locally in each FPGA. The flow automatically generates P&R constraints and guarantees hands-free closure across the design. Of course, you can still break into this flow to hand-tune for even higher performance. But based on stats they have published, out-of-the-box-performance is already pretty decent. And note that’s for a ~10x or more decrease in setup time.

    Accessories such as speed-bridges can be reused between emulation and prototyping, another factor in congruence; your ICE modeling in emulation carries directly over to prototyping. Similarly transaction interfaces can be reused.


    Cadence have also put a lot of work into the debug interface. For hardware, you can view waveforms across the design do force/release signal setting and set monitor probes, but of course the big focus in debug (given the target users) is for software. The S1 release includes a number of advances which should attract software developers and validators. Through a JTAG connection teams can download and upload/overwrite memory, control clocks, start and stop the design and they can write scripts around debug and test, all the features software developers expect in a full-featured debug environment. And naturally they can access the prototype remotely.

    Cadence have a fulsome endorsement from the Xilinx integration and validation team who have validated the value early in product development, and apparently they have other early users in networking, consumer and storage applications.

    You can read the press release HERE and read more about the Protium S1 platform HERE.

    More articles by Bernard…


    EUV is NOT Ready for 7nm!

    EUV is NOT Ready for 7nm!
    by Daniel Nenni on 02-27-2017 at 8:00 am

    The annual SPIE Advanced Lithography Conference kicked off last night with vendor sponsored networking events and such. SPIE is the international society for optics and photonics but this year SPIE Advanced Lithography is all about the highly anticipated EUV technology. Scotten Jones and I are at SPIE so expect more detailed blogs on the keynotes and sessions this week.

    Attend SPIE Advanced Lithography
    Come to the world’s premier lithography event. For over 40 years, SPIE has brought together industry leaders to solve the latest challenges in lithography and patterning in the semiconductor industry.
    Check out the 2017 News & Photo page andStay on top of what is happening before, during, and after the 2017 SPIE Advanced Lithography meeting in San Jose.

    The many BILLION dollar question of course is: When will EUV be ready for high volume manufacturing?

    According to Intel EUV Manager Dr. Britt Turkot, at this point in time, EUV is not ready for HVM and may not be ready for 7nm. Britt has been with Intel for 20+ years and is a regular presenter at SPIE. In fact, Britt did a similar presentation last year which was nicely summarized by Scotten Jones: TSMC and Intel on the Long Road to EUV, by Scotten Jones, Published on 02-23-2016 05:00 AM. You can get a full list of Scotten’s blogs HERE.

    If you look point-for-point, according to Britt, not much has changed. As Scotten pointed out, three years ago the key issues were: Photoresist – line width roughness (LWR) and outgassin, Tools – source power and availability, and Reticle – killer defects and pellicles.

    Photoresist technology continues to improve but no breakthroughs have been reported.

    The current power roadmap is to have 250 watts in the 2016-2017 timeframe, >250 watts in the 2018-2019 timeframe. From what I have heard thus far, power in the field is closer to 100 watts than 200 so we still have a ways to go before HVM.

    One of the most interesting points was particles and pellicles. According to Britt, particles are a much bigger problem than ASML has disclosed so pellicles will be required. I’m sure we will hear more about this during the conference but pellicles are a double edge sword. They do reduce the number of wafer defects caused by particles but they also draw source power which is already a key issue for throughput and machine availability.

    EUV photomask inspection was also discussed. Intel has been pushing for an actinic based inspection tool and that push continues. The question of course is: Who is going to pay for it? My guess is that, as with most semiconductor manufacturing roadblocks, there will be an inspection workaround to get EUV into production before R&D dollars are spent on actinic.

    As we already know TSMC has skipped EUV for 7nm but is planning on exercising EUV at 7nm in preparation for EUV at 5nm. At last year’s SPIE, Intel, Samsung, and GLOBALFOUNDRIES still had EUV planned for 7nm but we have heard some waffling on the subject. It will be interesting to get another EUV update on 7nm and 5nm from the people who are actually using it.

    Later today Intel will again keynote SPIE and present “EUV readiness for HVM” and Samsung will again present “Progress in EUV Lithography toward manufacturing”. Scotten will do thorough blogs on the conference as he has in the past. You can read Scotten’s very technical event related blogsHERE. If you are attending SPIE it would be a pleasure to meet you, absolutely.

    Also read:An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes


    CTO Interview: Jeff Galloway of Silicon Creations

    CTO Interview: Jeff Galloway of Silicon Creations
    by Daniel Nenni on 02-27-2017 at 7:00 am

    It is clear that IP companies play an important role in modern semiconductor design, in fact, I would say that they are imperative. Founded in 2006, Silicon Creations is one of those imperative IP companies that provide silicon proven IP to customers big and small around the world. To follow-up on our conversation with Silicon Creations CEO Randy Caplan, CTO Jeff Galloway provided a closer look at the technology behind their success.

    What sets Silicon Creations apart technically?
    First of all, I believe we’ve architected robust and versatile products. For example, we have a PLL architecture that has scaled from 65nm at company creation in 2006, down to 7nm. Over the last 10 years, it’s been ported all the way back to 180nm. The same robust proven architecture is silicon-proven from 180nm to 10nm and 7nm silicon is due very soon.

    The architecture has scaled not only across geometries but also along a huge power/performance curve. For example, the same PLL architecture that allows our high speed SerDes to achieve a fantastic power/performance ratio with jitter < 400fs also allows us to be the differentiated PLL provider for 10uW PLLs for application processors and other IoT devices.

    Secondly, given a robust architecture, it’s important to have a methodology to port the design from node to node. Typically, an SoC company concentrates product line on a specific geometry. An IP company like us, on the other hand, must have it’s IP available in a wide variety of nodes, or able to do so. We have a robust design flow methodology in place that allows us to port from foundry to foundry and node to node quickly and efficiently.

    We have delivered approximately 300 IP products (from 7nm to 180nm), so we certainly have a very wide range of IP. We have a schematic flow, which allows our core IP to be shared across geometry and foundry, reducing time to market and reducing risk. We also have a layout flow that allows similar flexibility, further reducing risk and providing robust products across variety of nodes.

    Thirdly, we have an automated test lab. We’ve characterized nearly 50 chips at this point (many in the last 5 years) and have generated over 100 test chip reports. This critical ability has allowed us to launch our customers’ 10nm products (and soon 7nm) and multi-protocol SerDes.

    Can you tell us a little more about your IoT PLL product and what makes it different, more appealing to design engineers?
    Low-power and fast lock times are critical metrics for IoT PLL products. Most “low-power” PLLs are on the order of 1mW. The active power is critical for our customers, especially in leading mobile products. Our architecture achieves less than 10uW while keeping area low. Secondly, we have an innovative architecture that frequency locks in fewer than 20 cycles, or just 3 cycles if calibrated. The PLL also phase locks in fewer than 40 cycles. This capability gives us an advantage in addressing the fast lock time requirements that is critically important for IoT where the reference clock is often 32.768KHz and energy shouldn’t be lost waiting on lock.

    You mention the PLL architecture that is in your 10uW IoT PLL is also in your Multi-Protocol SerDes?
    Yes, the same low power architecture is used. But we size the multi-protocol SerDes PLL on a different point on the power/jitter tradeoff curve, obviously . Nevertheless, we still achieve excellent power efficiency. For example, we have a 28nm product with ~5mW/Gb/s for SerDes operation that achieves < 400fs RMS RJ for 10G-KR. The low jitter for TX and RX along with an optimized front-end equalizer (CTLE+DFE) allows the SerDes to communicate over very long backplanes and other difficult channels.

    We think this SerDes product has the most flexibility on the market. Our lead customer for this was an FPGA customer (MicroSemi), so needed the flexibility and functionality. This single PMA can cover a 50:1 range from 250Mb/s to 12.7Gbs, and cover the following standards:

    Your products look differentiated, but have they found commercial success?
    We have a large number of production chips in silicon from 7nm (this month) to 180nm.

    Is the broad adoption because of performance?
    I believe a lot of the early design wins we had were based on performance. For instance, w e have a fractional-N product with long-term jitter low enough to clock AFEs or SerDes. That helps us stand out. But the same PLL, programmed to a different power/performance point, could clock digital logic power efficiently.

    Our customers quickly realized that they could replace many different PLLs with one Silicon Creations PLL.

    Due to the fractional-N capability, the PLL also can perform many frequency and phase functions such as spread-spectrum generation, DPLL/clock recovery and arbitrary phase shifting.

    We put tremendous effort to focus on customer needs, and we think that it greatly differentiates us. This is one of the prominent reasons why our customers keep returning for our PLLs for their next product.

    About Silicon Creations
    Silicon Creations is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), Chip-chip SerDes and high-speed differential I/Os. Silicon Creations’ IP is proven from 7 to 180-nanometer process technologies. With a complete commitment to customer success, its IP has an excellent record of first silicon to mass production in customer designs. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, Ga., and Krakow, Poland, and worldwide sales representation. For more information, visit www.siliconcr.com.

    Also Read:

    CEO Interview: Srinath Anantharaman of ClioSoft

    CEO Interview: Amit Gupta of Solido Design

    CEO Interview: David Dutton of Silvaco