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February 21, 2017June 14, 2019

"Ten-hut!" Attending the Signal Integrity Bootcamp

"Ten-hut!" Attending the Signal Integrity Bootcamp
by Tom Dillinger on 02-21-2017 at 12:00 pm
Categories: EDA, Events, Siemens EDA

The engineering team for the design and analysis of a complex system consists of a diverse set of skills — with the increasing emphasis on both high-speed interface design and multi-domain power management, a critical constituent of the team is the group of signal integrity (SI) and power integrity (PI) engineers.

The training of SI/PI engineers requires both breadth and depth of understanding of:

electromagnetic fields
transmission line theory
current loop analysis
RLCG impedance modeling
decomposition of signal transmission into scattering parameter-based analysis
frequency-dependent loss calculation
stripline and microstrip interconnect topologies
printed circuit board manufacture (including FR-4 glass weave tolerances and line roughness)
PCB stack-ups, via barrels and antipad design, and
the cause of resonant impedance in a set of PCB power planes

In short, the SI/PI engineer must be well-versed in a multitude of technical disciplines.

In recognition of the need to assist new SI/PI engineers gain additional experience, Mentor Graphics recently sponsored a full-day intensive SI Bootcamp at their Fremont CA education facility. The day was filled with a mix of lectures, labs, and in the teaching style of Socrates, numerous technical questions posed to the attendees. The instructor was the “Jedi Knight” of SI/PI practical and theoretical education, Eric Bogatin.

Eric began with a unique perspective, to put the audience in the correct mindset. “You need to be the signal — consider the instantaneous impedance, voltage, and current at each step down an interconnect from a driver’s transient. Consider what occurs at each point where the impedance seen by the instantaneous signal changes, and what reflections must occur. And, consider the propagation delay associated with each signal and each reflected transient.”

The attendees were encouraged to use the software utilities available in Mentor’s HyperLynx platform to analyze how impedance is dependent upon interconnect topology and PCB materials, to optimize impedance and minimize reflections.

The class was also encouraged to explore the time-based simulation superposition of instantaneous transients, continuing with the “be the signal” theme.

The next topic was to explore a complete model of a interconnect lane, with specific attention on the driver/package parasitics. Labs were included to allow the SI engineer to evaluate the high-frequency content of signal rise/fall times seen at the receiver, and how the composite losses in the model impact that transient. HyperLynx allows the ability to simulate a pseudo-random bit sequence (PRBS) serial stream to plot a superimposed signal arrival at the receiver, commonly referred to as the eye diagram.

A brief review of crosstalk analysis was presented, with insights into how crosstalk transients from an aggressor propagates to both the far-end (FEXT) and near-end (NEXT) of the quiet signal. The “snowball effect” of FEXT along the coupled length of the signal traces was emphasized.

The next topic was the representation of insertion losses in the system using scattering parameter models, including the familiar S-parameter matrix, where the S21 element is the primary representation for the attenuation of V_in when observed at V_out.

Eric shifted gears to discuss the characteristics of a differential signaling interface, from the differential driver’s IBIS model to the receiver. The presentation focused on the perspective of differential mode and common mode analysis, rather than as a pair of separate signals. In this manner, it is easier to understand how energy is converted from differential to common mode, and what differential/common termination strategies are the most effective. Eric challenged the bootcamp cadets to “think about what trace and via design decisions impact the differential impedance, and what should be the impact of topology optimizations, before you simulate — tools should be used to confirm your intuition, not simply to submit iterative testcases.”

The final topic focused on frequency-dependent power integrity analysis, how the selection and placement of signal and power planes in the stackup (and multi-layer signal vias through anti-pads in power planes) impact the loop currents of the instantaneous signal. An effective visualization for power integrity analysis is the power impedance plot between planes, highlighting the capactive, inductive, and resonant behavior at different frequency intervals. Eric reminded everyone that decoupling capacitors have their own mounting inductance that needs to be included in a composite model of the power plane cavity and decaps. Via-to-via crosstalk analysis requires a co-simulation of the SI/PI model.

At the end of the day, the attendees at the bootcamp review gave Eric a hearty round of applause. It was clear that all gained a greater appreciation of how to apply their academic knowledge to the practical tasks of SI/PI design, optimization and analysis.

If you have an opportunity to attend an SI Bootcamp session, I would strongly encourage you to “enlist”. Eric maintains a set of instructional materials available to SI/PI engineers, with a tremendous amount of video and written information, including a regular newsletter — the link is http://www.bethesignal.com (Not a surprise. :))

Also, Mentor has provided a free, online HyperLynx SI “virtual lab” with some very interesting applications — additional information is available at this link.

-chipguy

February 21, 2017

Plasmonics Integrates Photonics and Electronics

Plasmonics Integrates Photonics and Electronics
by Mitch Heins on 02-21-2017 at 7:00 am
Categories: Silicon Photonics

In the last year we have seen a marked increase in activity around the integrated photonics space, especially around silicon-based photonics. Last year the American Institute for Manufacturing of Photonics (better known as AIM Photonics) was started to boot-strap U.S. efforts in integrated photonics. We also saw multiple announcements by all three major Electronic Design Automation (EDA) players and a host of smaller Photonic Design Automation (PDA) players who are feverishly working to enter the market as photonics takes off. Pushing all of this is the insatiable demand for greater bandwidth density required by mega data centers who are quickly running out of rack front-panel space needed to satisfy the ever increasing data loads of an ever expanding internet of things (IoT) universe(s). Integrated photonics promises to accelerate us to the next level of bandwidth density and data communication speeds but the move into the data centers means much higher chip volumes and the need to push manufacturing costs down.

While silicon-based photonics is moving forward at a rapid pace, one sticking point for getting better cost-reduction has been that photonics does not scale or shrink in size at the same rate as its electronic counterparts. State-of-the-art electronic transistors are now in the sub 10nm range whereas photonic components are up in the 100’s of microns. Although integrated photonics are thousands of times smaller than using discreet photonic components, the photonics are still too large. Most silicon-based photonic integrated circuits (PICs) require waveguides with cross-sectional dimensions comparable in size to the wavelength of the transmitted light. That translates to waveguides with widths in 100’s of nano-meters.

Last year a new effort called PLASMOfab was started in Europe to tackle the photonics size problem. PLASMOfab is working on new structures known as Surface Plasmon Polariton (SPP) waveguides. These SPP waveguides are capable of guiding light at sub-wavelength scales as they can confine light into a width of a few nano-meters. They do this by using plasmonics which taking advantage of electron plasma oscillations near the metal interface. Plasmonics provides the capability to guide the optical field on a metal surface or between two metal surfaces or dielectric surfaces. This is remarkable on several fronts. First it provides for ultra-fine sensing capabilities that could be using for sensing applications and second, it enhances non-linearity’s such as Pockel’s effects used for polarization control in data communications applications. Additionally, SPP waveguides are unique in that they can be used to send both electronic and photonics signals along the same waveguide at the same time using geometries similar to those of electronic IC interconnect. If the work PLASMOfab is doing is successful they will indeed shrink the photonics down to the size of the electronics. Obviously it’s not that easy else it would have already been done but the jest is that there is a path to get there.

PLASMOfab is actually a 3-year collaborative project that brings together ten leading academic and research institutions and companies. The project was launched in January 2016 and it is funded by the European Union’s Horizon 2020 ICT research and innovation program. PLASMOfab’s goal is to develop CMOS compatible planer processes to shrink photonics and integrate it with electronics using plasmonics. Wafer scale integration will be used to demonstrate low cost, volume manufacturing and high yielding powerful photonic ICs. If successful, this new technology could produce a number of innovations in enhanced light-matter interaction for optical transmitters and biosensors.

In 2016 PLASMOfab worked to advance CMOS-compatible metals for the fabrication of plasmonic structures in commercially available foundries. TiN, Al and Cu were targeted for investigation as an alternative to gold or silver. Additionally, they were to generate a number of low-loss plasmonic waveguides on co-planar photonic substrates including SOI, SiO2 and Si3N4 using CMOS compatible metals. This work included interfacing the plasmonic waveguides to photonic waveguides.

In 2017 PLASMOfab is to work with PhoeniX Software to develop a plasmonic/photonic design automation flow and then use this flow to first, develop functional prototypes of an optical modulator and a biosensor with superior performance and then second, to then integrate the modular with 100 Gb/s SiGe electronics in a monolithic 100 Gb/s serial NRZ transmitter. Lastly in the bio-sensing arena, they are to integrate Si3N4-plasmonic biosensors with micro-fluidics and high-speed techniques in a multi-channel, ultra-sensitive lab-on-chip for medical diagnostics.

In 2018 their goal is to then demonstrate volume manufacturing and cost reduction by complying with large wafer-scale CMOS fabs and establishing a plasmonics/photonics/electronics fab-less integration service eco-system that can be adopted by commercial silicon and silicon nitride foundry services.

These are bold goals to be sure, but the potential is more than exciting as this could be a way to push photonics into the really low cost arena of silicon ICs.

For more information, see:
PLASMOfab website http://www.plasmofab.eu/
PLASMOfab write up in PIC Magazine http://www.publishing.ninja/V2/page/2416/143/168/1
PLASMOfab YouTube video https://youtu.be/0bAszCXUOag

February 20, 2017June 14, 2019

Mentor gets Busy at DVCon

Mentor gets Busy at DVCon
by Bernard Murphy on 02-20-2017 at 12:00 pm
Categories: EDA, Events, Siemens EDA

You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus Models based on the PSS standard. I know verification engineers barely get time to think, much less look ahead but this one stands between you and more effective test generation, coverage and debug so you pretty much must deal with it. Mentor as a leader in defining the standard already has technology in this area so what you learn here can be valuable immediately.

Monday afternoon they have a speaker in a tutorial on SystemC (also featuring speakers from Intel, NXP and Coseda). SystemC is a curious beast – when viewed purely from the perspective of RTL and as a higher-level alternative to RTL, it looks a marginal player (maybe 10% of design). But when viewed from a broader perspective it becomes a lot more interesting. System-level designers (at Google for example) want a fast path from concept to silicon, see no need to fiddle with intermediate RTL and apparently see a high level of success in using this path. Conversely, architectural modelers are finding they can hand off high-level test-benches, including software-driven testbenches, to RTL verification teams thanks to progress in the UVM-SystemC standard. Food for thought – maybe you don’t think you’re ready yet but you might want to find why others have already started.

Tuesday late morning Harry Foster will present on trends in functional verification based on a double-blind survey in 2016. If you didn’t get a chance to see this his summaries last year though Mentor webinars, this is a chance to hear the whole thing in one go. This talk is worth the time for several reasons:

You can see where your team sits relative to industry averages in adoption of major technologies
You can see where you sit relative to others on power verification
Most important (or embarrassing) of all, you can see where you sit relative to others in schedule overrun and reasons for respins
You get to understand that FPGA verification has become just as complex as ASIC verification, using constrained random, coverage and even formal methodologies

On Wednesday, there’s a great panel in the early afternoon asking the hard question – looking back over 15 years, was SystemVerilog really the best answer to our verification needs? Phil Moorby (the guy who created Verilog and played a significant part in SystemVerilog) is on the panel along with participants from Mentor, Cadence, Synopsys and of course Cliff Cummings so this can’t fail to be fun. Panelists will also talk about what they think an ultimate replacement for SV might look like.

Mentor is all over Thursday. They kick off the morning with how to use just formal (no simulation) to verify a drone’s electronics so you can send the thing off with a message to come recuse you from a desert island. Perhaps you’d never go that far with formal, but pushing it to the limit is a good way to understand how to better use formal more broadly. For lunch Harry Foster and Steve Bailey from Mentor are going to discuss the need for a platform to support enterprise verification, looking at trend analyses across IPs and across designs to identify opportunities to reduce risk, spur innovation and introduce new methods.

And in the afternoon, they’re going to reprise a popular topic – how to build a complex testbench quickly when you’re not a UVM expert. While UVM has been widely adopted as the standard for developing testbenches, the fact remains that many engineers still struggle with the complexities of the language and often fail to use it as effectively as they could. Sure, they’ll get up the curve eventually but design schedules wait for no man or woman. There are ways to become more effective quickly without having to first become a UVM back-belt – this tutorial will show you how.

Now for papers. Rich Edelman, a friend from way back, kicks off Tuesday morning with a paper on using the Direct Programming Interface. At the same time (darn), Mentor is presenting on a random directed approach to low power coverage, which sounds like an important one to hear. Wednesday mid-afternoon is a Mediatek/Mentor paper which should get an award for best title – “Ironic but effective; how formal analysis can perfect your simulation constraints”. And again, unfortunately at the same time there’s a paper on making legacy verification suites portable for the PSS standard.

The posters are always well worth checking out. This year they include speeding up functional CDC verification, incrementally refining UPF to manage the complexity of power state tables and (especially interesting to me) using Jenkins continuous integration to improve regression efficiency. If you’re following state of the art methods in continuous build and delivery automation, you’ll know that Jenkins already plays a significant role in software development flow and is starting to make its way into some hardware flows. This poster could be a nice introduction to some of the techniques and benefits.

You can get full details HERE. Make sure you sign up for the conference!

CEO Interview: Srinath Anantharaman of ClioSoft

CEO Interview: Srinath Anantharaman of ClioSoft
by Daniel Nenni on 02-20-2017 at 7:00 am
Categories: CEO Interviews, Cliosoft, EDA

It will soon be 20 years since ClioSoft started its journey of selling design management software for the semiconductor industry. It was a slow start considering that designs were relatively small and only digital front-end designers had begun to realize the importance of version control and design management. With open source solutions available and design management deemed as a nice-to-have feature, it was a tough sell.

Fortunately the steady focus and persistence have paid off with rich dividends for ClioSoft. Today, with over 200+ customers all over the world, ClioSoft is the leader in design management from concept-to-silicon for all types of designs in the semiconductor industry.

I have known ClioSoft since 2011 as they were one of the first companies we worked with on SemiWiki. Srinath is an EDA pioneer with great vision and it is an honor to work with him, absolutely.

20 years is a long time in the industry. What factors do you think have been responsible for this remarkable growth?
We are essentially an engineering company focused on providing quality products. We relate to the pains felt by the engineers and try to solve their data management problems. But there are a number of factors, which have helped us grow. Some of them are:

Our products are reliable, easy to use and built primarily for designers.
Since we do not have any investors, we do not have to worry about meeting growth rates and sales targets. Instead we can focus on delivering a quality product and helping our customers succeed. We believe sales and growth are by products of this goal.
As a company, we are easy to work with and fully committed to providing excellent support. As a result of this EDA vendors prefer to partner with us and we have a lot of word-of-mouth as well as repeat customers..
Trust, credibility and integrity are core values, which form the DNA of ClioSoft. We do not oversell potential or existing customers about the availability or quality of any features. Simply put, we work with design teams to solve their problems.
We support small and big customers with equal urgency. Our goal is to provide quality support to all.
And lastly we play fair. At the end of the day, companies want a partner they can trust and in most cases, ClioSoft is that partner.

Most of ClioSoft customers seem to be doing analog/mixed signal designs. Does ClioSoft also support other types of designs such as digital and RF.
That is a misconception. ClioSoft’s SOS design management platform supports all types of designs – Analog, Digital and RF. We initially started by evangelizing design management to digital designers. Soon thereafter we provided integrated design management for analog flows from Cadence[SUP]®[/SUP], Mentor Graphics and Synopsys[SUP]®[/SUP]. Thereafter Keysight Technologies (then Agilent) approached us to provide design management capabilities for their RF flow. We were the first company and probably still the only company to support RF designs. Since there was more demand from AMS designers, we have been a bit more focused on in this area.

ClioSoft’s SOS® is perceived as a design management platform exclusively for the semiconductor industry. Why is that?
From a data management perspective, the requirement of analog, RF and digital designers is quite varied. Every type of designer uses distinctly different types of tools and has their own flow for designs. The requirements for digital designers and software engineers are somewhat similar since their code is text based. With text, it is easy to manage, check for differences between the versions or merge the differences. As a result, digital designers often use software configuration management systems such as Subversion or Git, which are popular with software engineers. But with analog and RF designs the design database is binary making it more difficult to manage. A number of factors such as the interdependencies between the various cell views and the design hierarchy needs to be considered while managing the various revisions of the design or checking for differences in the schematics or layout views. The size of the design data is also a big factor in managing designs and a company cannot afford to have everyone copying large amounts of project data into their work space due to the relatively high capital and management cost of network storage. The design management platform needs to be flexible and robust enough to manage the diverse needs of the designers without interfering with their complex flows or compromising on performance – remote or local.

Our tools are architected from the ground up to meet the requirements of these engineers and not a layer glued on to third party software configuration systems such as Git, Subversion or Perforce.

Your competition also targets ClioSoft as being a proprietary design management system. Any comments?
Isn’t Perforce proprietary software too? We have always believed in owning the entire system as it enables us to provide solutions which best meet our customer needs. Any enhancement requests from our customers can be easily entertained and done in a timely manner. Owning the entire system also enables our solutions to be very robust and easy to use. We are not limited by the capabilities of a 3[SUP]rd[/SUP] party software that we do not control. If there is an issue the buck stops with us. We will not have to refer to or wait for the 3[SUP]rd[/SUP] party to provide a fix or enhancement. We also do not believe in holding the customer’s data hostage. If for any reason the customer decides to stop using our design management solution we will provide read-only licenses in perpetuity so they can always have access to their data.

With the growing emphasis on IP, what is ClioSoft’s perspective on design reuse and IP Management?
To meet the tight design schedules, design teams try to reuse IPs to the maximum extent possible. The growing use of third party IPs in todays SoCs, provides an additional overhead of managing costs and licensing liabilities. Internal IPs unfortunately do not get reused as much as one would like. This is due to a multitude of reasons. The quality of internal IPs are always suspect. In addition there is always the fear of getting support for these IPs in the event of a problem. We believe that having an ecosystem where one can easily find use internal and third party IPs alike and validate their quality is very important. The usage of internal IPs also needs to be pushed from the top management and needs to be a priority for the company. It is a common misunderstanding that the internal IPs are not reusable. Creating a culture of sharing will lead to significant improvements to productivity in the long run. We hope to help customers realize that goal.

Your competition seems to be providing hardware related solutions but ClioSoft has not bitten the bullet and jumped into the fray by adding hardware based solutions. Why is that?
We are primarily a software company and our focus is to provide solutions which will work with industry standard hardware. Our products are created keeping the following criteria in perspective namely performance, security, robustness and ease of use. We do not require any specialized hardware to make our solutions run fast. I am a veteran of the EDA industry and have seen how early EDA startups like Daisy and Valid failed. They built their own hardware but pretty soon they could not keep up with general purpose workstation manufactures like Apollo and SUN Microsystems and pure software based EDA companies took over. I believe in focusing on our strengths. By building our data management engine and not relying on software configuration system (SCM) we do not have to resort to building specialized hardware or kernel level file system manipulations to overcome the limitations of SCM solutions in managing extremely large design data.

ClioSoft has a very low attrition rate for a company in the Silicon Valley. What would you attribute this to?
We like to have a balance between work and fun. We do not have many levels of hierarchy and like to keep things simple. A strong sense of ethics and values have also helped attract considerable talent who have stayed on in the company. You will notice that we have never had a management team posted on our website. Every member of the team is important and that is not just a slogan.

ClioSoftwas launched in 1997 as a self-funded company, with the SOS design collaboration platform as its first product. The objective was to help manage front end flows for SoC designs. The SOS platform was later extended to incorporate analog and mixed-signal design flows wherever Cadence Virtuoso® was predominantly used. SOS is currently integrated with tools from Cadence®, Synopsys®, Mentor Graphics® and Keysight Technologies®. ClioSoft also provides an enterprise IP management platform for design companies to easily create, publish and reuse their design IPs.

Also Read:

CEO Interview: Amit Gupta of Solido Design

CEO Interview: David Dutton of Silvaco

CEO Interview: Toshio Nakama of S2C

February 18, 2017

Adaptation or Crisis – Will Security Save Technology

Adaptation or Crisis – Will Security Save Technology
by Matthew Rosenquist on 02-18-2017 at 12:00 pm
Categories: Security

The technology landscape is rapidly changing how we interact and live in our world. The variety of Internet of Things is huge and growing at a phenomenal pace. Every kind of device imaginable is becoming ‘smart’ and connected. Entertainment gadgets, industrial sensors, medical devices, household appliances, and personal assistants are being connected and empowered to relieve burdens of our daily living. The number of phones, tablets, and PC’s is fueling the growth of cloud based service environments.

Emerging innovations around semi-autonomous vehicles, artificial intelligence, merged reality, and machine learning is creating vast amounts of data. Next-generation critical infrastructures and communications are enabling greater capacities for connectivity and services. All of these and other elements are ushering in a new era of both connectivity as well as extending the reach of technology to control aspects of our physical world. With such great power, we will become more reliant on the devices and services which make our lives easier, efficient, and more productive. As a consequence, the need for security, safety, and privacy will become immensely important.

Existential Threat

Orion Hindawi recently penned an article in WIRED “Cybersecurity is an existential threat. Here is what we need to do”. In the article, Orion postulates the real emerging threat will not be around social engineering, the increase of ransomware, or nation-state cyberattacks. Rather he states:

“The hardest challenge for cybersecurity in 2017… will be scalability”

I met Orion and his father many years ago, back when they had started BigFix. Both impressed me as very smart people and possessed a keen understanding of the challenges security products faced in large enterprise environments. At the time, big organizations were having great difficulty in understanding what was on their network, how to keep it patched, and what to do when devices no longer conformed to standards. Security products did not have the breadth to understand all the moving parts and even worse did not function well when tasked to support so many endpoints and connections.

The Ante Goes Up

Well the world is about to experience those problems once again, at a global scale. Orion’s article in Wired takes those challenges and the expertise behind solving some of those problems for business, to the next logical step.

The number of users, device, and usages are ramping up. This, combined with devices beginning to extend beyond data and into ‘control’ of the physical world will bring life-safety concerns to light. The technology and security industry will have a choice: adaptation or crisis. As incidents become apparent, the expectations of people will help drive change in regulations, product purchase criteria, vendor selection, and standards. A real risk remains. If the risks of threats aren’t put in check soon enough, a severe backlash could occur.

Safe Technology

Security must rise as we further embrace and empower technology to have insights and control over aspects of our everyday routines. Will security be able to scale? Well, for the benefit of us all, it better adapt quickly. There is far too much is at stake.

Interested in more? Follow me on Twitter (@Matt_Rosenquist), Steemit, and LinkedIn to hear insights and what is going on in cybersecurity.

February 18, 2017

Think your future historical encrypted data is secure? Think again…

Think your future historical encrypted data is secure? Think again…
by Bill Montgomery on 02-18-2017 at 7:00 am
Categories: Security

It’s been 32 years since the successful sci-fi comedy, Back to the Future, saw 17-year old Marty McFly – played by Michael J. Fox – accidentally travel 30 years back in time to 1955. The film was a box-office smash, as audiences worldwide delighted in McFly’s antics, only to soon realize that the cool kid from the future was jeopardizing the very thing that made his life a reality – his then-teen parents meeting and falling in love.

A key tenant of this film is that somebody living in today’s world – McFly – has discovered a way to go back in time – through a cosmic “back door” – and gains access to secret (let’s call it “encrypted”) information considered inaccessible to anyone other than those who generated it first-hand.

While time travel is not conceivable as far as we know (though I suspect Google is working on it), what is conceivable is that people or nation states will soon be able to travel back in digital time and retrieve secure encrypted data always considered non-retrievable.

Say what?

Well, here’s what Isaac Chuang, a distinguished MIT Professor of Physics, Electrical Engineering and Computer Science, says,

”if you are a nation state, you probably don’t want to publicly store your secrets using encryption that relies on factoring as a hard-to-invert problem. Because when these quantum computers start coming out, you’ll be able to go back and unencrypt all those old secrets.”

That shouldn’t be a problem, right? After all, in today’s technologically-advanced day and age, who and what could possibly be using factoring in cryptographic schemes?

The answer: most everybody and everything. That’s because the foundational cryptography underlying most existing so-called “secure” solutions is RSA, which relieson factoring as a hard-to-invert problem for its underlying security and which leading pundits believe is on the verge of crumbling.

And it’s not just the pundits that are ringing the death knoll for RSA. The chart below, extracted from the US NIST Report on Post – Quantum Cryptography clearly states that RSA, ECDH and DSA are nearing the end of their life cycle.

Professor Chuang alerts Nation States to the dangers of continuing to use crypto which relies on factoring, but his warning just as easily applies to businesses, even individuals. Picture your competitors or personal enemies going back in digital time and unlocking any data that you have ever created and encrypted for safe-keeping. The impact of such revelations will be overwhelming, even dangerous.

It’s time for the world to abandon cryptographic schemes created last century and make the bold move to quantum-resistant crypto that will ensure secrets, be they national, corporate or personal, remain where they are meant to be – locked and impermeable to outside intrusion.

February 17, 2017August 22, 2024

Could China Take the Lead in Installed 300mm Capacity?

Could China Take the Lead in Installed 300mm Capacity?
by Scotten Jones on 02-17-2017 at 12:00 pm
Categories: Foundries, GlobalFoundries

China buys more than half of the semiconductors manufactured in the world and yet only produces less the 10% of their own demand. Recently there have been a lot of announcements out of China about large scale investments in semiconductor manufacturing. The Chinese government for example has announced plans to invest $161 billion dollars over ten years in semiconductor manufacturing.

In terms of specific announcements Tsinghua Unigroup has the most ambitious plans. Tsinghua Unigroup has announced plans to invest $28 billion dollars in a 500,000 wafer per month foundry fab, $24 billion dollars for a 300,000 wafer per month 3D NAND Fab for their XMC subsidiary and also has plans for a $30 billion dollar investment in a 300,000 wafers per month memory fab. GLOBALFOUNDRIES has partnered with the Government of Chengdu on a $10 billion dollar foundry fab we project will produce >60,000 wafer per month including GLOBALFOUNDRIES 22FDX FDSOI process. There are several other projects underway or planned as well.

IC Knowledge LLC produces a database of all the current and planned 300mm fabs worldwide. We believe this is the most detailed and comprehensive 300mm database available. We are currently tracking 164 fabs and part of our analysis includes capacity by country.

As of the end of 2016 the top five countries in the world in terms of 300mm capacity in order from greatest to least capacity are:
[LIST=1]

South Korea

Taiwan

Japan

United States

China

Based on current announcements and our projections we expect that China will pass the United States for the fourth most installed capacity by the end of 2018. The end of 2018 capacity by country would then become:
[LIST=1]

South Korea

Taiwan

Japan

China

United States

Further projecting forward to 2020 we are forecasting China may pass Japan for third place and the rankings to be:
[LIST=1]

South Korea

Taiwan

China

Japan

United States

As surprising as these results may be, by the end of 2023 are forecasting that China may pass Taiwan for second place and the ranking to be:
[LIST=1]

South Korea

China

Taiwan

Japan

United States

And finally, in 2024 we are forecasting China may become the world leader in installed 300mm capacity and the ranking to be:
[LIST=1]

China

South Korea

Taiwan

Japan

United States

Figure 1 summarizes the percentage of worldwide capacity each country represents by year.

Figure 1. Percentage of worldwide 300mm capacity by country.

This analysis comes with several cautions:

This is 300mm capacity only and does not include older legacy 200mm and smaller wafer sizes. However, as 300mm is the most advanced and productive wafer size we believe this is a good metric for determining manufacturing leadership.
This analysis is based on current and announced fabs. Other countries could install more capacity than we are currently forecasting, and, or china could install less capacity than they are currently planning. The recent announcements from China are both larger and more forward looking than most 300mm announcements. Certainly, China has been working to climb the ranks of the semiconductor industry for a long time with only moderate success to-date so not all of these announcements may actually take place.
Currently the 300mm fabs in China lag the leading edge. The leading foundries worldwide are ramping 10nm processes and preparing 7nm for the next 12 to 24 months at a time when China’s most advanced foundry fabs don’t yet have 14nm in production. The XMC 3D NAND Fab will bring up a 32-layer process at a time that other 3D NAND producers will be on 64 layers and working on 96 layers.

Despite these cautions, the potential for China to have the largest installed 300mm capacity base by the mid twenty twenties should serve as a warning to the rest of the semiconductor industry of how aggressive China’s plans for semiconductor manufacturing expansion are.

February 17, 2017June 14, 2019

Mentor Plays for Keeps in Emulation

Mentor Plays for Keeps in Emulation
by Bernard Murphy on 02-17-2017 at 7:00 am
Categories: EDA, Siemens EDA

EDA has always been a fiercely competitive market, no more so than in emulation where the clash of claims and counter-claims can leave those of us on the sidelines wondering who’s really on top. Sales are the obvious indicator but leadership there flips back and forth between product releases. That makes Mentor’s choice to play a long game all the more interesting. This week they announced their Veloce Strato platform, raising the bar on specs again but also positioning this as the first step in a 5-year plan. When did you last hear of a 5-year plan from an EDA company?

Jean-Marie Brunet (Sr. Director of Marketing at Mentor) told me they had started with a study of capacity needs, stretching out to 2021. They see need to support up to 2.5 billion gates today and they have charted sizes, based on semiconductor company announcements and internal analysis, up to 15 billion gates 5 years from now. These monster designs are found where you would expect – CPUs, GPUs, APUs (application processing units in smartphones) and NPUs (network processing units) – possibly multi-die or multi-chip, maybe single die if EUV ever goes mainstream.

To get reasonable run-time performance, a design must fit in a single emulation box, whatever that box may contain. In light of these capacity projections, Mentor felt they had to move to a new architecture; Jean-Marie casts this as an evolution of the Veloce2 architecture rather than a revolution but significant enough that it can rise to these demands. This week they announced the Veloce Strato platform, designed to scale all the way to 15 billion gates, and availability of the Veloce StratoM emulator at 2.5 billion gate capacity as the first step in this plan.

Together with the Veloce Strato OS, designed with the same objective in mind, the new Veloce StratoM system delivers some impressive stats:

2.5x the capacity of Veloce2
Up to 3x improvement in compile times with 100% success rate
Up to 10x improvement in time to debug/visibility
Up to 3x co-modeling speed improvement
Overall, up to 5x improvement in throughput (compile-run-debug).

Strato OS has been designed to be platform independent and remains compatible with Veloce Apps and protocol solutions; it is also interoperable across legacy Veloce installations (Jean-Marie didn’t say how far back), as well as with Strato solutions. The StratoM fits in the aisle of a datacenter at 4-4.5 racks high and remains air-cooled. And StratoM boxes can be linked through StratoLink to further extend multi-user support.

Strato OS in many ways is the centerpiece of the Veloce Strato architecture. Of course, it must maintain compatibility and transparency across different Veloce architectures, but it also needs to offer support across multiple use-modes (ICE, accelerated testbenches, virtual components and others). Most important, it must integrate support for debug capabilities like Replay and LiveStream. This cross-platform support is a big part of what ensures scalability in the solution.

Applications for emulation beyond functional verification are multiplying in areas like software development and debug, power estimation and test debug. These capabilities will also scale with the platform. And there’s another compelling application where this level of emulation horsepower is already starting to become important – validation. We tend to think primarily in terms of verification when we think of EDA hardware, but validation (does the system operate as expected, not just does it conform to the spec) is just as important. Mentor has already taken a step in this direction in their partnership with Ixia, to model realistic network traffic. They anticipate, and they can hardly be wrong, that pre-silicon validation along these lines can only become more important across a wide range of designs. That will for them drive Strato OS as a common platform for verification, prototyping and validation solutions.

Naturally Mentor already has a StratoM customer and, just as naturally, it’s a customer who doesn’t allow their name to be used in press releases. But given the class of designs requiring this kind of box, it doesn’t take a lot of thought to narrow down the list of possibles. Feedback from that customer has been very positive and it sounds like other customers are now starting to use StratoM.

Putting this all together, Mentor has laid out a path to support scalable emulation of 15 billion gates within 5 years, they have redesigned hardware and software to meet this goal and have delivered the first step on that path, Veloce StratoM, proven with at least one large customer. And finally, the solution requires no disruption to existing Veloce customer flows, apps or protocol modeling; a run on StratoM just appears to be on a bigger and faster resource. That looks like the start of a well-executed long-game.

Four Barriers to Using an SoC for IoT Projects

Four Barriers to Using an SoC for IoT Projects
by Daniel Payne on 02-16-2017 at 12:00 pm
Categories: EDA, Events, IoT, IP, Open-Silicon, Siemens EDA

I often read about the large number of expected IoT design starts around the world, so I started to think about what the barriers are for launching this industry in order to meet the projections. One of my favorite IoT devices is the Garmin Edge 820, a computer for cyclists that has sensors for speed, cadence, power, heart rate, altitude and temperature. The Edge 820 also communicates with Bluetooth and ANT+ wireless protocols, and has GPS to track each ride. At the recent ARM TechCon event there was a panel session on this topic of IoT design with participants from ARM, Mentor Graphics, Open-Silicon and Sondrel. This group came up with the following four barriers to using an SoC for IoT projects:

Cost of the semiconductor IP blocks
Cost of the EDA software tools for design and verification
Silicon development costs
SoC design experience

Typical IoT devices use sensors, which means processing analog signals, plus there is typically a processor to run an OS or code. Here’s a snapshot of the building blocks in most IoT chips:

NRE
This acronym stands for Non-Recurring Engineering, and it appears in three of the top four barriers to creating an IoT project. So what if there was a way to reduce this NRE level so that you could do a proof of concept at little to no costs? Now that idea sounds compelling, and it turns out that ARM and Mentor Graphics have done something about it.

ARM DesignStart
We’ve heard about the great success that ARM enjoys as an IP company offering CPU cores for many market segments, and they’ve created a way for designers t get a trial selection of their cores without charge, called DesignStart.

What DesignStart means is that you can get a free download and use for design and simulation their Cortex-M0. The M0 offers a low-power, 32-bit CPU in a very small size.

EDA Software Tools
Now that you have a processor and some of your own analog IP blocks, you’ll need some EDA tools to do design exploration. There are free evaluation tools from Tanner EDA, part of Mentor Graphics, that last for 30 days, enough time to do a proof of concept. Design entry is done with schematic capture, and simulation is handled by T-spice for the analog portions and ModelSim for the digital blocks.

Sample IoT Design
To illustrate how you would use the ARM + Mentor design flow, consider an example IoT design with a sensor, ADC block, and Processor:

For this proof-of-concept design we’re just connecting up the components, but not running any code on the M0 processor, rather we are verifying the simple control logic between ADC and processor. In the Design Kit from ARM you’ll receive a pre-integrated processor subsystem with the following peripheral components:

Our Control Block is shown in dark purple above so we next add Verilog code to describe the behavior using the text editor in S-Edit:

The control block connects to the subsystem bus, so we use Verilog again after learning a bit about the APB (AMBA Advanced Peripheral Bus) and create a module to define APB inputs and outputs, design IOs, design signals, and port mapping:

In Verilog we connect our peripheral to the M0, then we can write a simple text program for the M0 in C code using the ARM Keil MDK-Lite, a software development environment. Here’s the C code that sets the memory-mapped address of the APB port 15:

This C code runs printf statements in the simulator through the UART module. With an ADC input set at 1.8V and ADC reference at 2.2V, then we will expect an ADC output value of (1.85V/2.2V) * 256 = 215. If 215 counts were simulated the test passes, else it fails.

Simulating the IoT Design
Design entry was done with S-Edit and the Verilog-AMS netlist gets split into two parts for simulation in either digital or analog simulators:

One last step is to create a design testbench that models the analog sensor input as a constant 1.8V, has a clock, and reads IO values for display:

Our 8-bit ADC does a successive approximation that converts the analog input from the sensor into a digital value, read by the processor. In the waveforms below we can see the Red signal reaching the 1.8V level:

Summary
It is now possible to do a proof-of-concept SoC design for an IoT project at no cost, other than your engineering time by using processor IP from ARM and EDA tools from Tanner EDA. So the first three barriers listed at the start are now addressed, the fourth barrier is addressed by ARM where they have a list of SoC design partners to help you through the development process. There is an 11 page White Paper from Mentor with more details here online. I cannot wait to see all of the new IoT designs coming out over the next few years that will improve my life.

February 16, 2017June 14, 2019

Aldec Rounds Out ALINT-PRO Checker

Aldec Rounds Out ALINT-PRO Checker
by Bernard Murphy on 02-16-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor automatically sets the RTL up correctly” and variants on these confident statements of infallibility.

Positions like these became much less frequent after IP reuse and SoC design took off. You might still feel the same way about your own code, but now you must work with RTL developed by someone no longer at the company, and integrate with other RTL developed by parties even further removed. How can you know what assumptions they made? You don’t have time to reverse-engineer this stuff in simulation, so do you just hope the other designers thought exactly the way you do when they built that code?

This topic is fairly widely understood in the ASIC world, perhaps less so in the FPGA world where design teams now working on monster FPGA SoC designs are starting to learn the importance of verification disciplines their ASIC counterparts have crafted over many years. A recent survey on trends in verification highlights that FPGA and ASIC verification needs are converging, which is good news for ALDEC who have in ALINT-PRO offered a common verification platform for both.

Static verification is your first safety net in functional verification. Naturally it won’t catch complex functional problems but it will get you past the basics – incorrect inferences, unintended truncation, unclocked cycles and other basic design flaws. You could still catch many of these in simulation but in verification environments of any scale that would be grossly inefficient. These all kick off with smoke tests, including static verification, to ensure basic mistakes are caught before valuable simulation cycles are wasted.

What’s more, simulation won’t catch everything. Signals crossing between asynchronous clock domains (say between a peripheral port and a central bus) can lock into metastable states or drop cycles, causing all kinds of havoc. While some claim you can catch these problems using simulation approaches, analyses of that kind are invariably incomplete. Static tools like ALINT-PRO have this kind of analysis built-in and since it is static, it is test-case independent, ensuring you will find all potentially problematic crossings.

That said, I’ll now contradict myself by adding that sometimes a combination of static and dynamic analysis is essential to reach more complete domain-crossing verification, especially where functional behavior is an essential part of the check. This often comes up in checking handshaking synchronization schemes. Aldec support this through close linkages between ALINT-PRO and the Riviera-PRO simulator or other simulators.

ALINT-PRO also provides pre-defined block-level models for Xilinx primitive libraries and now adds models for most of the Intel/Altera families of devices. This is important. When static analysis tools bump into a hard macro, such as a memory, they need hints on how to proceed, such as whether this is a registered interface and which clock controls the interface. Aldec provides a method for you to define these yourself, but life is a lot easier when models for all the basic blocks are already defined and verified with the FPGA vendor.

One last point I learned the hard way during my time in these trenches. Static checkers are based on rules and everyone has their own opinion on what rules should and shouldn’t be checked and at what stage. Some users want the whole check to be fire-and-forget so they enable all rules (more must be better, right?) and run. The result is massive volumes of reports they can’t possibly read and which they therefore ignore. Until a silicon spin fails, the boss asks whether they checked the static analysis and there’s a long, awkward silence.

The lesson is that checking everything makes no sense; you must be selective. And what you choose to select is sensitive to where you are in the design cycle. When building a brand-new RTL block, you might want to require more checks to comply with an internal (or external) standard. When checking modifications to a legacy piece of RTL, you need to loosen up; you don’t want to know about coding-style problems in areas you don’t plan to touch. In system integration, you want to focus mostly on functional issues (such as clock and reset domain crossing analysis). ALINT-PRO makes it possible to craft these choices in way that reflects your local preferences.

You can read the ALINT-PRO product description HERE.