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Functional Safety is a Driving Topic for ISO 26262

Functional Safety is a Driving Topic for ISO 26262
by Tom Simon on 05-23-2018 at 12:00 pm
Categories: Automotive, EDA, IP, Synopsys

When I was young, functional safety for automobiles consisted of checking tread depth and replacing belts and hoses before long trips. I’ll confess that this was a long time ago. Though even not that long ago, the only way you found out about failing systems was going to the mechanic and having them hook up a reader to the OBD port. Or, worse you found out when the car stopped running or a warning light came on. A lot has changed with the advent of ISO 26262 which defines the standard for automotive electronic system safety.

The most critical systems, which are designated as Automotive Safety Integrity Level (ASIL) D, have many requirements imposed on them to ensure high reliability. This applies to systems where a failure could lead to death or serious injury, e.g. ADAS systems. It is easy to understand that these systems must be carefully designed and documented. While this is true, the safety requirements extend into ensuring that these systems can self-check at startup and also continuously monitor their own health. In fact, ISO 26262 requires that every block in these systems must run a self-test every 100 milliseconds during operation. This can include fault injection too. In effect, it is now necessary to “check the checkers”.

Even the scope of the functional safety self-monitoring tests is impressive. For instance, in the case of memories, in addition to requiring ECC on data, addresses are also protected by ECC. SOC designers for automotive applications are now faced with not only building the system they have specified, they need to build in extensive new on-chip functionality to ensure functional safety that meets the ISO 26262 standard. This process is somewhat familiar to designers, who have been adding BIST and Scan test functionality into their designs for decades.

Fortunately, similar to the model for BIST and Scan, there are commercial IP based solutions and tools chains that address the needs arising from these dramatic changes in system testing. Synopsys has long been a player in both the IP and test markets. It is only natural that they extend and adapt these offerings to create a combined and comprehensive solution. They have done the work to make their solution ISO26262 ASIL-B through ASIL-D ready.

There is a very informative video presentation that gives an overview and then goes into detail on the Synopsys functional safety offerings along with specific customer experience from Bosch in the application of STAR Memory System (SMS) and STAR Hierarchical System (SHS). The presenters are Yervant Zorian, Synopsys Fellow & Chief Architect, and Christophe Eychenne, Bosch DFT Engineer. In the first half, the very knowledgeable Yervant covers the requirements of ISO 26262 systems and then outlines the offering from Synopsys. In the second part Christophe goes through a case study from Bosch.

Here are a few of the interesting things I learned from this video. In the case of memories, each memory is given a wrapper that can perform testing and then implements memory repair. The repair information is saved and reloaded at start up, However, an additional test is performed at every start to fully check each memory. This helps manage aging in memories. Soft error correction in memories is complicated in newer process nodes because of the increased likelihood of multi-bit errors. The SMS is aware of memory internal structure and this helps in error detection and correction.

The SHS wraps interface and AMS blocks, and connects to a sub-server using IEEE 1500. The wrapped memories are tied together using the SMS processor and all of these elements and the digital IPs with DFT scan are then connected to a server which offers the traditional TAP interface. In addition, there are external smart pins that can be used to quickly and easily initiate tests without needing a TAP interface controller. As an added bonus, this entire system can be used to facilitate silicon bring up using with the Synopsys Silicon Browser.

Back when we were changing hoses and belts for long trips, Synopsys was just an EDA tools company. But, like I said, that was a long time ago. Synopsys has evolved and developed impressive and sophisticated offerings in IP, which now includes many of the essential elements to build SOCs and systems for safety critical automotive systems. The video presentation is available on the Synopsys website, if you would like to get the full story behind their latest work in this area.

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Webinar: RISC-V IoT Security IP

Webinar: RISC-V IoT Security IP
by Daniel Nenni on 05-23-2018 at 7:00 am
Categories: Events, Intrinsix, IP, RISC-V, Security, Semiconductor Services

Disruptive technology and disruptive business models are the lifeblood of the semiconductor industry. My first disruptive experience was with Artisan Components in 1998. The semiconductor industry started cutting IP groups which resulted in a bubble of start-up IP companies including Artisan, Virage Logic, Aspec Technologies, and Duet Technologies. Back then we were getting hundreds of thousands of dollars for a library when all of a sudden Artisan introduced a free royalty based model backed by the foundries. Artisan was later purchased by ARM for $900M, Virage was purchased by Synopsys for $350M, Aspec, Duet and dozens of others went out of business.

I see the same opportunity with RISC-V. I see disruption coming to the CPU IP market. The challenge is the ecosystem and that’s where crowdsourcing comes into play.

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

IoT is one of the biggest markets for RISC-V and security is one of the biggest challenges facing IoT which brings us to the upcoming Intrinsix IoT Security Webinar:

  • a brief look at the market for IoT security IP
  • component functions of an IoT system-on-chip (SoC)
  • hardware acceleration for IoT devices
  • secure boot of an IoT device
  • benefits of hardware acceleration for IoT security
  • use of a dedicated RISC-V security boot processor
  • key components of an easily to deploy NSA Suite-B IoT security IP solution

About Intrinsix Corp.
Intrinsix Corp., headquartered in Marlborough, MA USA, is a design services company for advanced semiconductors with clients around the globe. The company has been servicing the needs of electronic product and semiconductor companies for more than 30 years. Intrinsix has the platforms, process and people to ensure first-turn success for industry-leading semiconductors.

IoT security primers:

Jump Start your Secure IoT Design with Intrinsix
by Mitch Heins Published on 12-05-2017 11:00 AM

Have you ever had a great idea for a new product but then stopped short of following through on it because of the complexities involved to implement it? It’s frustrating to say the least. It is especially frustrating, when the crux of your idea is simple, but complexity arises from required components that don’t add to the functionality of the design. Enter the world of an internet-of-things (IoT) device.

IoT Security Hardware Accelerators Go to the Edge
by Mitch Heins Published on 10-23-2017 10:00 AM

Last month I did an article about Intrinsix and their Ultra-Low Power Security IP for the Internet-of-Things (IoT). As a follow up to that article, I was told by one of my colleagues that the article didn’t make sense to him. The sticking point for him, and perhaps others (and that’s why I’m writing this article) is that he couldn’t see why you would want hardware acceleration for security in IoT edge devices. He wasn’t arguing the need for security. He was simply asking why you would spend the extra hardware area in a cost-sensitive device when you could just use the processor you already have in the device to do the work in software.

Intrinsix Fields Ultra-Low Power Security IP for the IoT Market
by Mitch Heins Published on 09-21-2017 05:00 PM

As the Internet-of-Things (IoT) market continues to grow, the industry is coming to grips with the need to secure their IoT systems across the entire spectrum of IoT devices (edge, gateway, and cloud). One need only look back to the 2016 distributed denial-of-service (DDoS) attacks that caused internet outages for major portions of North America and Europe to realize how vulnerable the internet is to such attacks. Perpetrators, in that case, used tens of millions of addressable IoT devices to bombard Dyn, a DNS provider, with DNS lookup requests. Analysts predict that by the year 2020, there will be over 212 billion sensor-enabled objects available to be connected to the internet. That’s about 28 objects for each person on the planet. While the opportunity for disaster seems obvious, the opportunity to make a lot of money on IoT is even bigger, so the industry needs to urgently address the problem. How can you make your IoT SoC devices secure?

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Block RAM integration for an Embedded FPGA

Block RAM integration for an Embedded FPGA
by Tom Dillinger on 05-22-2018 at 12:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP
2 Comments

The upcoming Design Automation Conference in San Francisco includes a very interesting session –“Has the Time for Embedded FPGA Come at Last?” Periodically, I’ve been having coffee with the team at Flex Logix, to get their perspective on this very question – specifically, to learn about the key features that customers are seeking to accelerate eFPGA IP adoption. At our recent kaffeeklatsch, Geoff Tate, CEO, and Cheng Wang, Senior VP Engineering, talked about a critical requirement that their customers have.

Geoff said,“Many of our customers are current users of commodity FPGA modules seeking to transfer existing designs into eFPGA technology, to leverage the PPA and cost benefits of SoC integration. One of the constituent elements of these designs is the use of the “Block RAM” memory incorporated into the commercial FPGA part. We had to develop an effective, incremental method to incorporate comparable internal RAM capabilities within the embedded FPGA IP. Flexibility is paramount, as well – we need to be able to accommodate different array types and configurations, with a minimal amount of our engineering team resources.”


Figure 1. Illustration of the integration of memory array blocks in a vertical channel between eFPGA tiles.

Cheng added, “Recall that the fundamental building block of our IP is the tile. eFPGA designers apply our tools to configure their IP as an array of tiles.” (Here’s a link to a previous article.)

“The edge of the tile is developed to provide an appropriate mix of inter-tile connections, balanced clock tree buffering, and the drivers and receivers for primary I/O ports on perimeter tile edges. To accommodate the customer need for memory arrays, we’ve developed an internal methodology to space the normally abutting tiles and introduce banks of memory blocks.”, Cheng continued.

The unused drivers/receivers at the interior tile edges provide the necessary interface circuits to the memory block, driving the loads of the memory inputs and interfacing the memory outputs back to the eFPGA switch fabric. A portion of the clock buffering and balancing resources at each tile edge is directed to the clock inputs of the array.

“Are the internal eFPGA memory blocks constrained to match the Block RAM in a commercial part?”, I asked.

“Not at all.”, Geoff replied. “We have customers interested in a wide variety of array size and port configurations. And, they are extremely cost-conscious. For example, they do not want the overhead of a general, dual-port memory configuration for their single-port designs.”

“To support this flexibility, we had to enhance our compiler.”, Cheng added. “The netlist output of Synplify is targeted toward the Block RAM resources of the commercial parts. When reading that netlist into the eFLX compiler, we re-map and optimize the Block RAM instances into the specific memory block configuration of the eFPGA.”

“What are the signal interconnect design requirements over the memory block?”, I asked.

Cheng answered, “We anticipate the memory arrays in the rows and columns between tiles will be fully blocked up through M4. Our inter-tile connections to the switch fabric are above M4. The power grid design readily extends to support the memory block, as well.”


Figure 2. A recent testsite design tapeout with embedded array blocks between tiles.

Cheng summarized the discussion well. “We have developed a methodology to allow our engineering team to develop an eFPGA design addressing customer requirements for memory blocks, with an incremental amount of internal resources. We are leveraging the tile-based architecture and the tile edge circuitry to simplify the integration task. Our engineering team does the electrical analysis of the final implementation. The customer utilizes the existing eFLX compiler, reading in the additional SDF timing library released for the internal memory array blocks.”

Geoff added, “This interface and implementation method would support the integration of a general macro between tiles, within the overall LUT and switch architecture of the eFGPA.”

So, back to the DAC session question – has the time for eFPGA IP arrived? If designers have the flexibility to quickly and cost-effectively integrate additional hard IP within the programmable logic of the eFPGA, without significant changes to the design flow, that’s pretty significant.

I’m looking forward to the DAC session, to see if others concur that the time is indeed here.

For more information on the Flex Logix RAMLinx design implementation for embedded memory blocks, please follow this link.

-chipguy

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Semiconductor, EDA Industries Maturing? Wally Disagrees

Semiconductor, EDA Industries Maturing? Wally Disagrees
by Bernard Murphy on 05-22-2018 at 7:00 am
Categories: AI, Automotive, EDA, Security, Siemens EDA
1 Comment

Wally Rhines (President and CEO of Mentor, A Siemens Business) has been pushing a contrarian view versus the conventional wisdom that the semiconductor business, and by extension EDA, is slowing down. He pitched this at DVCon and more recently at U2U where I got to hear the pitch and talk to him afterwards.


What causes maturing is saturation – the available market that can be divided among providers doesn’t have much room to grow, or rather will grow only relatively slowly. That triggers consolidation – you eat your competitors, they eat you, or you shrivel up and die because you’re too small to compete. The big guys continue to make money through efficiencies of scale, aka laying off a bunch of people in duplicated functions after a merger. So for some (eg Mark Edelstone at Morgan Stanley in late 2015), the wave of consolidations in semiconductors pointed to a maturing industry.

But Wally says that’s an over-simplified analysis of what’s really happening, and he has a lot of data to back up that viewpoint. Obviously there has been a lot of consolidation, but the best of it has not been winner-take-all across the market but rather winner-take-all in very targeted segments, which he calls specializationrather than consolidation. He cites as examples TI who famously pivoted from wireless/cellular, automotive, ASIC plus analog to a laser focus on analog, also NXP who have specialized in Automotive and Security. Another example he offers is Avago/LSI/Broadcom, now concentrated in wired and wireless infrastructure and enterprise datacenter (especially storage). What’s notable in each of these cases is that profitability has steadily climbed, for TI and Broadcom to ~40% and for NXP to ~20% (each in operating margin as a % of revenue). Contrast this with Intel which has acquired and divested many companies over the years and whose earnings as a % of revenue have remained more or less flat.


Wally took this further. He showed that there is essentially no correlation between operating margin and revenue; in other words, the economies of scale argument doesn’t fly (outside of a few cases – analog, RF, power and memory). But suppose the semis were trying it anyway; would they cut back on R&D? Again, the data doesn’t support that view. R&D in the semiconductor industry has remained pretty flat at 14% over 35 years. Moreover, the cost per transistor shipped continues to drop at 33% per year. Wally said this isn’t really a Moore’s Law effect (though of course process improvements have contributed and continue to contribute). Innovation and demand is driving this curve. So much for the smokestack view of semiconductors; the data simply doesn’t support this being a maturing market.

He also talked about top players in the market and new entrants, noting that combined market share of the top N (pick a number) companies in the industry has remained at best flat, which means there are smaller companies and new entrants grabbing some of the pie. From a western perspective we haven’t seen much VC activity around semiconductors but the picture in China is quite different; over $100B in the 5-year plan, originally concentrated in foundry investment but now increasingly shifting to fabless investments (up to 1500 fabless startups recently). OK, so maybe that doesn’t help us in the west, but we’re seeing, in the west and the east, new systems level entrants. Google, Amazon and Facebook are all building their own devices; not big volumes in some cases, but smart speakers and home automation are likely to change that. Bosch, a well-known Tier1 provider in the auto business, has opened a $1B fab. Who can afford to do this in 7nm? Not a lot of designs have to be that aggressive and for those that do, the FAANG group have deep, deep pockets.

What does this mean for EDA? Wally said in his talk that a lot more of the innovation drive is coming from system companies. This was also true in the early days of EDA; Mentor for example got a healthy share of its business from aerospace and the DoD for example. In fact while we tend to think very SoC-centric, 70% of the development effort (per Wally) in building a complete system is at the system level, not in the IC. At the board, or in the enclosure and across a vehicle you have to consider power integrity, thermal and mechanical stresses, EM interference, wiring harness design, etc, etc. You’ve heard of digital twins – this is where the Tier1s and OEMs are trying to reduce costs and iterations in getting all of this right before they build physical prototypes. He also pointed out something I have been hearing more recently. The Tier1s/OEMs are looking for more opportunities to differentiate through closer connections in design from modules down to die, again looking for analytics and optimization spanning this range.

Which to Wally means that the opportunities for innovation in EDA are richest at this full system integration/analysis level. That presents new challenges because verification complexity rises rapidly with the size of the system. He feels a lot of the innovation here is likely to come from the big EDA companies working with their customers, simply because of the complexity of the problem; it is difficult for a new entrant to make a dent in problems of this scale with point tools. However there could be opportunities in new capabilities in safety and security, also around new device physics/multi-physics around thermal and other system-level analysis domains. Machine learning applications are definitely interesting (qv Mentor’s Solido acquisition) – anything that can reduce analysis time and/or improve optimization.

My takeaway from all of this:

  • Semiconductor isn’t maturing, it’s evolving to support new applications and markets
  • Semiconductor can only mature if we lose interest in innovation in general. No matter what technology is hot (neuromorphic, DNA computing, nanobots, quantum, …), we will still need to compute, communicate, manage/generate power, .. How else are we going to do that?
  • EDA as always will follow semis and will equally evolve. But we EDA types need to follow the puck. The real money will not be in polishing the same old domains.
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UBER car accident: Verifying more of the same versus the long-tail cases

UBER car accident: Verifying more of the same versus the long-tail cases
by Moshe Zalcberg on 05-21-2018 at 12:00 pm
Categories: AI, Automotive, Cadence, EDA, Events
9 Comments

The recent fatal accident involving an UBER autonomous car, was reportedly not caused – as initially assumed – by a failure of the many sensors on the car to recognize the cyclist. It was instead caused by a failure of the software to take the right decision in regard to that “object”. The system apparently considered it a false positive, as “something” not important enough to stop or slow down the vehicle, as if it was a newspaper page flown by the wind.

The (rather disturbing) dashcam footage released indeed shows the car system “not bothering” about the cyclist crossing the road.

After all, this was an odd scenario. The system was probably trained to recognize cyclist ontheir bikes, riding along the road and not across, as crossing should only happen on pedestrian lanes, and most probably during the day.

One must consider the fact that such Artificial Intelligence systems are trained by actual frames and footage recorded in previous rides, that log the most common cases.If it’s not pre-classified as something that deserves attention, the car might well just move on.

In the Cadence CDNLive EMEA conference that took place in Munich in early May, Prof. Philipp Slusallek of Saarland University and Intel Visual Computing Institute, highlighted the critical role of verification of such AI systems. The pre-recorded footage is good to test for the routine and trivial cases (e.g. cyclist riding along the road), he said, but not for a complete coverage of the long tail of “critical situation with low probability” that the system may not implement or may not be tested for.


(I apologize for the quality of the slides’ pictures. The presentation was in well-attended large hall.)

The solution he offered was for a High Performance Computing (HPC) system that analyses the existing stimuli data and generates additional frames for such unavailable cases, to achieve a “high variability of input data” – just as one will do in constraint driven randomization of inputs in the the verification of VLSI systems. Such a system, should take the “real” reality, as recorded from actual footage, as a basis and augment it with a Digital Reality of additional instances of scenarios – as described in the following slide:


However, such system displays multiple challenges and requirements, to analyze the existing scenarios and create additional valid scenarios:


In light of this extensive list of requirements, no wonder that the first part of the presentation focused on the HPC platform necessary to run such analysis and simulation. Since AI for Autonomous Driving (and possibly other use-cases) is supposed to be ubiquitous (and therefore cost-sensitive), I wonder if this heaving-lifting computing system will be a viable solution for the “masses”?

Furthermore, a verification engineer looking at some of the slides above, might be tempted to think constrained-random is the solution. A researcher, might see Monte-Carlo simulation in it, and others might see their domain specific solution. The real solution to the problem, would most likely be all of those and none of them, as the problem at hand definitely requires a new paradigm. Talking from a verification engineer’s stand-point, constrained-random, while good at generating extremely varied solutions, always requires a set of rules, i.e. the constraints. Its native field of application was for generating unexpected combinations within well-defined protocols. With the problem of autonomous driving, there are really no hard rules, as the Uber incident demonstrates quite well. Rather than starting from constraints, building a well-defined solution space and then trying to pick the most varied and interesting ones, this problem requires starting from real-life scenarios and then augmenting them with interesting variance that follows only soft rules. Instead of fighting the last war, verification engineers should probably start looking for inspiration, new technologies and new methodologies for generating stimuli elsewhere, maybe in the machine-learning domain? On the other hand, machine-learning algorithms are often a “black-box” – with these inputs, those are the outputs – not giving the system, or the person designing the system, enough insight on what and how can be improved.

In fact, Intel/Mobileye just announceda large deal to supply 8 million cars to a European automaker with its self-driving technologies, as soon as 2021 and released footage of autonomous driving in busy Jerusalem. And the debate about how many and what types of sensors, cameras, LIDARs and radars are needed for a full autonomous vehicle is still on.

However, as discussed above, no matter how many “eyes” such cars have, the true challenge will be to verify that the “brains” behind such eyes are making the right decisions at the critical moments.

(Disclaimer: This early post by Intel claims that the Mobileye system would have correctly detected and prevented the fatal accident).

Moshe Zalcberg is CEO of Veriest Solutions, a leading ASIC Design & Verification consultancy, with offices in Israel and Serbia.

*My thanks to Avidan Efody, HW/SW Verification expert, for reviewing and contributing to an earlier version of this article.

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CEO Interview: YJ Su of Anaglobe

CEO Interview: YJ Su of Anaglobe
by Daniel Nenni on 05-21-2018 at 7:00 am
Categories: AnaGlobe, CEO Interviews, EDA

AnaGlobe Technology, Inc. is a leader in layout integration solutions that have been adopted by world-wide technology leading companies including the foundries, fabless, design services, packaging, panel, and IP companies. I know several of Anaglobe’s customers and am happy to work with them, absolutely.

The following is a Q&A discussion with YJ Su of AnaGlobe:

Please tell us about AnaGlobe?
AnaGlobe is a Taiwanese EDA company based in Hsinchu. We specialize in layout especially with custom layout creation and wafer-level chip-scale layout integration. We have been collaborating with several world-class semiconductor companies for more than 10 years, including customers in the US, Ireland, China, Korea, Japan, Singapore and Taiwan. We have distributors in the US, Europe, China, Korea, Japan and South-East Asia. AnaGlobe will exhibit at DAC 2018, booth #2340.

What makes AnaGlobe unique?
AnaGlobe offers a versatile IC layout framework and closely work with customers to embrace the fast-pace and timely response to the dynamic nature of top semiconductor foundries, design houses and packaging services providers. AnaGlobe has been working closely and responded rapidly to our customers’ demands, and expect to grow with customers’ in multi-wins collaborations.

AnaGlobe also sponsors some talented EDA researchers and projects in Taiwan. We though start with a small-scale company, but also do some state-of-the-art topics and have participated leading-edge technologies such as pattern matching, machine learning, etc. in IC layout domains.

What keepslayout integration engineers up at night?
Today’s semiconductor industry faces the dynamic dilemma among both economic and technology factors, e.g. time-to-market, ROI estimation (return-on-investment), with various process nodes, SOC or SIP path-finding and diversity of the end products such as applications in IoT, automotive, mobile and high performance computing and even heterogeneous components integration.

One common challenge to layout integration team is facing the dynamic nature of complicated design intents, revisions and huge data size. For example, a top-level layout assembly task normally manages hundreds of sub-blocks in either a SOC GPU chip, or an advanced-node testchip design or a multi-chip SIP project, while each sub-block owner may have many design re-spins. These require high performance layout integration platform, though not necessarily as-is expensive design implementation or signoff EDA options. As we’ve been engaging these with top-tier fabless, foundries and packaging houses, AnaGlobe commit this topic is good fit to our software strengths and decent technical customization supports, for multi-wins scenarios.

How can AnaGlobe products help?
We have two main products: GOLF aims at full custom layout creation with high flexibility; THUNDER eyes on wider diversities with great performance (e.g. terabytes data capability), from IPs to wafer-level chip-scale layout assembly integration. Furthermore, with flow automation and CAD features combination, we can build comprehensive database handling solutions in tape out flows, chip-packaging integration and path-finding, and even inline manufacturing image-to-cad inspection analysis domains.

GOLF:
For custom layout creation, we offer three levels of functionality:

[LIST=1]

  • Being a SI2 member, our tools are built-in OA (OpenAccess) database compatible, with proprietary data structure of GDS/OASIS/DXF/EDIF import/export. GOLF provides layout and schematic viewing, layout editing, hierarchical editing, query, undo/redo, schematic-driven layout (SDL) and also interface to major verification tools (Calibre and ICV).
  • Instead of tedious programming language to create PCell layout, GOLF (Geometric Objects Layout Formula) offers flexible and highly productive device-level layout creation and reusable hierarchical layout generator on OpenAccess, by both programming support (API for TCL, Python and Perl) and a GUI-based PCell Designer. It is an intuitive IDE (integrated development environment) for PCell creation, preview, testing, debug, and documentation on layout directly. Customers also adapt PCell Designer in the creation of manufacturing test key layout, flat panel display layout and 3D packaging layout, etc.
  • GOLF is also incorporated with several constraint-driven custom placers and routers, for specific application of examples, characterization test chip layout generator in advanced process nodes, all-angle router for free-form panel display, constraint-driven analog layout, and so on.THUNDER:
    For wafer-level chip-scale layout integration, our goal is to support the layout database from post P&R, IP merge, verification (XOR LVL, connectivity, etc.), debugging, defect inspection, failure analysis to chip-package integration. Comparing to normal OA file size handling capability, THUNDER has a proprietary database, called ThunderDB, and is capable to handle huge layout data with extreme performance of up to 600+GB GDS per minute. Users can then perform big data analysis for further processing (e.g. 3D-view, cross-section, density map, wafer map), machine learning based optimization, and read/write for GDS, OASIS, LEF/DEF, MEBES and OpenAccess.Can you provide some real world (customer based) examples?
    Generally, our customers include some of the top 10 ranking companies of IC foundries, OSATs, IC design houses, optoelectronics companies and even semiconductor equipment vendors. GOLF has been used in the layout creation of test structures for advanced process technology nodes, free-form panel displays, 3D packaging and analog designs. THUNDER has been tailored into a variety of applications including an in-house collaboration platform, a 2.5D/3D packaging layout integration flow, sign-off tape out flows and the layout data preparation front-end of e-beam equipment.

    For example, the IP merge and the XOR LVL functions of THUNDER have been adopted by several customers in their sign-off tape out flows and obtained 10x performance gain. Some of our customers use THUNDER to handle multiple data sources (e.g. layout data, DRC results, pictures from SEM, in hundreds of GB scale) to analyze the data sanity.

    Which markets do you feel offer the best opportunities for AnaGlobeproducts the next few years and why?
    We may recap our versatile layout platform positions good fit for both cell bottom-up design flows (mainly with GOLF) and system top-down design flows (mainly with THUNDER). In addition to GOLF user-friendly PCell creation, schematic and/or constraint-driven layout editing, THUNDER’s capability in huge design handling, efficient database structure, flexible flows automation and interface to major verification EDA tools also ensure the seamless design flows to confront the dynamic design efforts in IoT, automotive, mobile and high performance computing applications. AnaGlobe keeps spending tremendous efforts to develop advanced layout functions in the very near future, and commits to facilitating the whole design solutions.

    http://www.anaglobe.com/

Also Read:

CEO Interview: Ramy Iskander of Intento Design

CEO Interview: Rene Donkers of Fractal Technologies

CTO Interview: Ty Garibay of ArterisIP

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Chip Equipment where to from here?

Chip Equipment where to from here?
by Robert Maire on 05-20-2018 at 12:00 pm
Categories: Semiconductor Advisors, Semiconductor Services
1 Comment

We may know the top, do we know the bottom? What is the downside in NAND, DRAM, Foundry. Can China help or is risk worse than upside?

It would appear that our concerns in our preview piece prior to the AMAT call came true as the stock now has a “4” handle, NAND is in question and display is down.

However its not like business is falling off a cliff any time soon. The industry is clearly not like the bad old days when business fell off by 50% in a quarter, the industry is less volatile. Aside from the industry being more mature, so are the stocks, with dividends and significant buybacks.

Companies have enough excess cash to prop up EPS in a dropping market by buying back shares much as we saw in Applied’s just announced quarter. It may not seem like a lot but the combination of dividends and buy backs will cushion downturns at least from a stock perspective.

Customers are more rational. Rather than building new capacity in fab size chunks they have been modulating their capacity in smaller bites. We will get some exceptions such as display where Samsung came to an abrupt halt but that is an exception more than a rule and we also saw a huge uptick in OLED leading up to that abrupt stop.

However stocks still are volatile and react as we have seen in this 10% drop in AMAT. While we remain concerned about NAND spend, display, and slow foundry we are still intrigued by the upside in China. We saw over a $1B in sales by Applied.

Our problem is that the China upside brings with it huge political risk. Just as we thought the risk was going away, politicians started up new legislation aimed squarely at China and tech. We think that the upside in China could mitigate softness in NAND, foundry & display but the downside beta is huuuge as That $1B could go to zero inside of a quarter by the snap of a politicians fingers (see our preview in our recent April fools newsletter…)

In short the industry and stocks are at an interesting crossroad with conflicting currents yet to be sorted out.

NAND – We still like it but its getting old
The SSD revolution has been great. Iphones with 256GB of NAND are also great. The industry has been careful not to overbuild but we are sure that China wants to shoehorn its way into the NAND market and the way to do it is by price. Although we are way away from China being a force in NAND the existing supply/demand balance may be softening. The softening has not come from the supply side as it has been rational, the softening has come from the demand side which has not kept up. Capacity will not come off line as we finish up 2D to 3D conversions so we really need demand to pick back up.

Foundry
TSMC, the world’s biggest foundry, made it clear on their call that demand was softening. They have been very good spenders going to 10NM. However we would point out that there is significant equipment reuse between 10NM and 7NM whereas there was not a lot of reuse going from 14NM to 10NM. This reuse issue , coupled with soft smart phone demand makes for weaker spend, likely for a year or more. We could see spend on EUV as the industry tries to migrate but less so in other areas.

Yield management still good
We still think the difficult EUV conversion coupled with new inexperienced players in China that need to figure out process bodes better for yield management and with it KLAC & NANO etc;. Indeed KLA has been a slight bit more positive in outlook than AMAT or LRCX and the stock has also outperformed.

Subsuppliers – MKSI, AEIS, ICHR, UCTT etc…
As expected these companies are off in sympathy to their customers as well they should be. However, we would point out that they are more diversified and somewhat less levered to their customers fortunes and misfortunes as the case may be. Their performance has been very good and the stocks have held up much better than in previous cycles when they were at the end of the whip or bottom of the hill as things flowed downhill. They are much more resilient now.

The Stocks
In terms of the stocks, we might get interested again in Applied in the mid $40’s. We could potentially see another round trip to the mid $50’s but we think it will be harder to crack $60 given the headwinds now present. We doubt that news will improve after the current quarter is reported and we have the China sword returned to a position above our heads. Analysts who were bullish going into the quarter have lost some credibility and the dreaded “C” word (cyclicality) is being used again.

We still like KLAC as the copy least impacted by most issues (perhaps with the exception of China). ASML will likely see improving EUV business but that may not boost earnings as margins remain poor versus DUV so we are not intrigued by that play.

We still like Micron for being dirt cheap and see continued strong profits.

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AMAT has OK Q2 but Q3 flat to down

AMAT has OK Q2 but Q3 flat to down
by Robert Maire on 05-20-2018 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
1 Comment

“Puts & Takes” “Reduced NAND Expectations” 2019 to be down from 2018. Applied Materials reported a good quarter coming in at $1.22 EPS and $4.567B in revenues versus street of $1.14 and $4.45B.

However if we back out the buy back of 4% it would have been around $1.17 so a slight beat. Guidance was for EPS of $1.17 +-4 cents versus street of $1.16 but revenues of $4.43B +- $100M versus street of $4.53B.

So basically we had an in line quarter with a down guide.

On the call management said there were “Puts and Takes” in customer orders (which is code for cancellations). Management pointed out weak smartphone sales as the reason for the “re-adjustment” of business from customers.

Also on the call management said their expectations for NAND business in 2018 was “reduced” from prior expectations. This is no surprise as NAND has been feeling a bit “toppy”.

Perhaps the most interesting comment was management’s view that 2019 will be a down year. If we try to read into the numbers it sounds like a roughly 10% drop in 2019 versus 2018.

This seems to imply that we are at or near a peak in AMAT’s business. This may not be a sharp peak and feels a bit more like a plateau that will slowly fall off as management made clear that customer spend has been more rational.

Finally , as expected OLED display business was off while LCD TV business was OK.

Did AMAT just call a “market top”?

It kinda feels like it…..
With a projected down 2019 and near term “puts and takes” coupled with reduced NAND expectations it sure sounds like we are at or near a peak for the year or maybe for this entire “supercycle”. Add to that the OLED issues in display which will last through at least 2018 and we are very hard pressed to see the upside.

“Puts and Takes”
Puts and takes is usually code for pull ins and push outs of orders but usually only gets said when the push outs exceed the pull ins. Given that the comment was associated with smart phones we can only deduce that TSMC was backing off spending as they mentioned the same thing on their call. This is obviously the first sign of a deteriorating market in foundry.

“NAND expectations for 2018 reduced”
NAND has obviously been on fire for well more than a year and along with DRAM has been the vast majority of semiconductor tool spending. Apple’s comments said they expect memory pricing to moderate later in the year and this comment may reflect that.

Make no mistake, NAND spending is still huge but it will likely be less huge in the future and perhaps the rate of growth will slow or get negative.

Display will be down in 2019 – OLED off

As we had suggested in our preview note, OLED spending has slowed which reflects the comments from Samsung. Next gen LCD TV spend is still OK also as expected. We don’t see a bounce back in OLED any time soon and it sounds like AMAT expects that weakness to continue. Management expects 2019 display to be down.

The stocks
Given the cautious comments made by management on the conference call coupled with the flattish guide and 2019 down guide its clear that the stock trades off tomorrow. Management sounded overly defensive during the Q&A session. The stock is already off 7% as we write this and our preview piece suggested we could get back to a $4 handle , down 10%, and that’s what it feels like right now after listening to the call.

Bulls will try to defend it but the company made some key negative comments that are going to be hard to overcome.

Obviously this will be negative for the overall group but we did already get a similar flat/down from LRCX so we don’t see a major impact on that stock, but it will be down. KLAC remains the outperformer of the group but will likely be off a bit in sympathy as well.

It was a nice cycle while it lasted…….

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SPICE Model Generation by Machine Learning

SPICE Model Generation by Machine Learning
by admin on 05-18-2018 at 12:00 pm
Categories: EDA, FinFET
3 Comments

It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis)while I was characterizing a 1.5 μm Standard cell library developed by students at my Alma-Mata Furtwangen University in Germany. My professor Dr. Nielinger was not only my advisor he also wrote the first SPICE bible in German language. At that time SPICE simulation was already established as the “golden” Simulator for circuit design for over a decade – and remains so to this day.
Continue reading “SPICE Model Generation by Machine Learning”

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ZTE Caving shows China Trade Tirade is Hollow

ZTE Caving shows China Trade Tirade is Hollow
by Robert Maire on 05-18-2018 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

We have been watching the ZTE saga play out on the public stage as we think it is an extremely important leading example of how the administration will truly act. As we all know, actions speak louder than words, and in the case of ZTE our words said one thing and our actions said something else. We need to analyze what the actions really mean about trade issues that impact technology and China as ZTE was perhaps both the first real test as well as the poster child for China trade issues.

ZTE impacts both companies selling semiconductor components to ZTE and obviously ZTE itself. However, the true impact is much broader as it is an indicator of other semiconductor companies who sell into China, semiconductor equipment companies who sell into China as well as IP issues and many other far reaching issues.

There has been a cloud hanging over a large swath of semis as China sales are the fastest growing area of business for most companies and represents much, if not all of the future upside.

From a stock perspective, we have been very concerned about the downside risk to US tech companies if the US got into a real trade war with China. We were only partially kidding about our April fools note which jokingly announced a halt of US semiconductor equipment sales to China. We think it could happen but now the likelihood has been greatly reduced following the ZTE surrender.

Additionally, the Washington Post has printed a list of “demands” from China regarding trade. We now have a yardstick to judge the administration by as we can see which of the demands we have caved in on.

ZTE = Zhilaohu (paper tiger)

The term “zhilaohu” or “paper tiger” was coined by Mao Zedong to describe the US as being all bark and no bite. It would seem that we could resurrect that term to describe the current situation with trade as it applies to ZTE.

Hollywood screenwriters could not have dreamed up a more perfect nemesis for the current administration than ZTE.

  • More jobs in China versus US – check
  • Supporting Iran by providing equipment – check
  • Supporting North Korea by providing equipment – check
  • Suspected of espionage in equipment – check
  • Poster child for trade dispute – check

ZTE checks all the boxes and the administration could claim victory on so many fronts so it seemed like a slam dunk until we caved. This is why everyone is spinning.

The press has drawn a dotted line to a Trump company deal in Indonesia that will feature a Trump branded hotel, residences and golf course, being built with $500M from the Chinese government.

Some have suggested the US caved over concerns of agriculture exports to China being at risk.

Whatever the real story is, its confusing. The official US stance of saving Chinese jobs just doesn’t seem to hang together.

The Chinese “Demand List”

The demand list from China as published by the Washington Post;

  • The United States commits to eliminating the sanctions imposed after China’s crackdown on protesters in Tiananmen Square in 1989.
  • The United States relaxes export restrictions on technology such as integrated circuits- Read this as China can buy all the US technology it wants, good for US chip equipment makers bad for competing chip makers who could get trashed like solar and LED before them.
  • The United States allows U.S. government agencies to purchase and use Chinese information technology products and services- Goes against concerns of trojan horse firmware in Chinese equipment- routers and mobile phones.
  • The United States agrees to treat Chinese investment and investors equally to those from other countries and place no restrictions on Chinese investment –Would allow Chinese purchase of Lattice, Xcerra or Micron or many other US tech companies.
  • The United States agrees to ensure Chinese businesses can participate in U.S. infrastructure projects Allows suspect equipment and companies to be used in critical US infrastructure.
  • The United States agrees to strengthen protection of Chinese intellectual property. Means companies like AMEC will win over companies like Veeco. US IP protection would be zero.
  • The United States agrees to drop its anti-dumping cases against China at the World Trade Organization. China would be allowed to dump in the memory chip business just as they do in solar and LED.
  • The United States agrees to terminate its investigations into Chinese intellectual property theft and not impose any of the sanctions Trump already announced. China is free to rip off any US IP.

By any standards this is a pretty ugly list. We now have a very public yardstick to measure future US trade deals and can grade the ZTE reversal as an “F”

Removes the sword of Damocles
We have been concerned about the risk of a major event in the trade tirade with China. We have been concerned of halting chip sales or equipment sales or other things that could trash US tech stocks.

Given what happened with ZTE it is very clear that the probability of getting into a real trade war with China is near zero and all we will do is likely to be lip service.

People can point to CFIUS blocking several deals but the reality is that the biggest blocked deal was Broadcom buying Qualcomm and it was not directly against a Chinese company. The Lattice deal was blocked but probably would have been blocked for any foreign buyer.

The administration seems to be against most any large deal not just foreign companies buying US companies.

Maybe next years April fools article will be giving advanced chip tools & designs away free to China……

The stocks
In our view while there is no specific upside to be had in US stocks other than those directly involved with ZTE which have already popped.

In our view, risk to US semiconductor and equipment sales has been greatly reduced, perhaps not to zero, but to levels similar to what we had prior to the trade tirade.

The longer term threat to IP and technology dominance still remains and could get worse depending upon how the US responds to China’s demand list.

For now, at least another variable has been removed or reduced from an already volatile tech sector.

This could obviously change at any moment and we could see yet another 180 degree reversal from the administration so we wouldn’t get too comfortable.

Perhaps the administration is listening to cooler heads in the tech industry like Tim Cook , but we doubt it…….

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