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Single-Chip Narrow-Band IoT

Single-Chip Narrow-Band IoT
by Bernard Murphy on 06-05-2018 at 7:00 am
Categories: Ceva, IoT, IP

Many factors go into building a competitive solution for the IoT, but few are as important for high-volume applications as low cost – not just chip cost but total system cost. If your customers are going to deploy thousands, tens of thousands or even millions of your devices in cities, factories, logistics applications, power grids or homes, products above ~$5 a piece are going to be a very hard sell. I’m not talking here about high-functionality user equipment with high-end sensor fusion, graphics and so on. I’m talking about the little devices that don’t need to do a lot, just a little data-gathering, compute and communication, and should run on a battery for 10+ years.

The trend here is no mobility (eg for parking meters or street lights) or very low mobility, with need to send only a few bytes periodically (how often do you need to be reminded “still working and still no car parked at this meter”?). Battery life is incredibly important; maintenance costs to replace batteries, even annually, could undermine the value of the solution. Compute isn’t going to be a big power factor so low-power communication becomes very important. That’s why the Narrow-Band IoT (NB-IoT) standard was developed – to provide a low-power, low-datarate cellular communication solution.

Compared to standard LTE at rates of mega-bits per second, NB-IoT only has to support ~100Kbps, using only a small fraction of the bandwidth. It also can run at much lower power and need only provide half-duplex support. The smaller bandwidth allows for a much smaller RF bill-of-materials (BOM), reduced power means that the RF and power amplifier can be integrated on the same die with the rest of the functionality, and half-duplex further reduces the RF BOM. Together this allows all the communication hardware to be integrated on one die, it provides long-range communication eliminating the need for gateways, and it is reasonable to expect a 10-year battery life.


So far I’ve just talked about the standard (NB-IoT, also known as Release 13, also known as LTE Cat-NB1) because there is an upcoming revision (eNB-IoT, also known as Release 14, also known as LTE Cat-NB2) which I’ll talk about more in a later blog (*). CEVA provides a product to support this standard in their Dragonfly NB1 solution IP. They’re an acknowledged leader in communication IP building on their core DSP strengths, so it’s no surprise that they’re all ready to serve this domain. The solution is built on their X1 core (interestingly designed after the X2, making it a prequel?) and includes digital front-end, RF transceiver, peripherals and software stack. So far, so good – CEVA is helping their customers stay current with evolving communications options.

Where this gets interesting is that the X1 has been designed to function effectively not just as a DSP (for communication) but also as a general-purpose CPU for this domain. X1 has been tuned to deliver competitive performance as a CPU, comparable to Cortex-M4 in Coremark, and provides (they tell me) a compiler-friendly architecture, large orthogonal register file, compact code, full RTOS support, fast context-switch and more. And while M4 provides some DSP instructions for comms support, DSP is CEVA’s home turf so they’re naturally stronger in that area. OK, so X1 has the capability to handle both communication SW and general-purpose software, but won’t it be bogged down in communication when active?

CEVA ran an interesting NB-IoT benchmark, looking at load on the X1 at a typical operating frequency. They found that nearly 50% of the time, the processor was idle. Of course this core can’t run Android and other big workloads, but it doesn’t have to (honestly, if you’re trying to run Android on an NB-IoT device, you have different problems). All you want is to run is some sensor fusion and fairly simple application software. Which it looks like the X1 has plenty of capacity to support.


And that’s just what CEVA wanted – a low-cost single-chip solution for NB-IoT, no need to add a separately licensed MCU core. In fact all you have to add to Dragonfly is embedded flash. They provide all the other logic/interfaces, including cache memory to reduce latency on memory accesses. And they provide all the software. So this solution really can get down to the low unit cost that NB-IoT solution providers need. Naturally they provide a reference solution for all of this.

Emmanuel Gresset (Director Biz Dev in the CEVA Wireless Unit) tells me CEVA believes this has a lot of potential as NB-IoT takes off. Right now, solutions are commonly based around a slim modem (one chip) from a major supplier, plus your own chip to handle your requirements. Bluetooth started with similar multichip solutions, however price-pressures forced integration. The same will happen, perhaps even more so, for NB-IoT apps where pricing expectations will likely be lower still. He added another fascinating point along similar lines. Providers really want to drive solution prices down to the $2-$2.50 range. To do this, they’re looking for ways to reduce stacked margins up and down the supply chain. Some system houses are now partnering with CEVA and ASIC shops to provide the content and expertise to build and manufacture their solutions. Yet another driver of disruption in the supply chain 😎.

You can learn more about Dragonfly-NB1 HERE. You might also want to register for an upcoming related webinar chaired by Daniel Nenni: Custom SoCs for Narrowband IoT (NB-IoT).

(*) Thanks to Emmanuel for corrections to the naming :p

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Is there anything in VLSI layout other than “pushing polygons”? (10)

Is there anything in VLSI layout other than “pushing polygons”? (10)
by Dan Clein on 06-04-2018 at 12:00 pm
Categories: EDA
2 Comments

The year is 2005 and PMC Sierra decided that it is time to expand by adding a new site in Bangalore, India. We started with digital verification first but by 2006 we were ready to engage with Mixed Signal Design and Layout. I went to Bangalore in June 2006 for the first time and with the help of our local manager, Vikram Labhe, had a few layout services companies come and present their competence. Started with Wipro, SiCon, then Smartplay and Sankalp. After 2 weeks of meetings and interviews I decided that the best bet for PMC was Sankalp. The main reason was that their growth plan was “organic from inside” without stealing people from other companies, fact of pride for the other contenders. I met the management team, Vivek Pawar, Mrinal Das, Alok Pugalia, Prabhat Agarval, and Mohan R. Their dream was to build a service company by taking new grads and train them into solid layout designers. More than that, they decided to build design services centers in second tier cities attached to second tier universities, which will raise the level of these locations and their population.

This was also a good business idea from the point of retention compare to big cities like Bangalore, Noida, etc. As a person who already trained a “few” generations of layout designers in different countries this was “music to my ears”. I visited Sankalp sites and got 2 bright people with little layout experience but a lot of enthusiasm. Now we wanted to grow our Bangalore PMC Sierra team but also the Sankalp team working with us. If I wanted to get more knowledgeable people for my team I had to get involved in their training. I started by reviewing Sankalp materials and decided that they needed help. I took my Cadence 5 days training course and made it 5 weeks for new grads. As the students already had electrical knowledge I had to adjust a few things but with the help of Sankalp future trainers we got the ball rolling. Using Mohan analog experience, Alok memory expertise and Prabhat IO and design knowledge we ended up with a great material that covers 2 months training.

For the next 5 years I had sessions with all new students on tools and methodologies, and yes long nights and SKYPE video were part of the norm… But the results were astonishing and we were able to pick up the best students for our PMC team. Using these updated materials and contributions from Vivek, Mrinal and other external advisors, Sankalp trained from 2007 until today more than 1200 new grads, so I consider my time “well spent”.

I wrote and delivered in the following years a few more training for Sankalp: a Train the Trainer for the teachers of the course, an Introduction to Management and Project Management for new leaders, and helped the soft skills teachers prepare a few other courses. Later in Sankalp we developed Project management with Puneet Pandey and a lot of soft skills materials with Shilpa HP and Bhuvaneshwari Shurpali, the trainer in ekLakshya. I visited India every 6 months and all my weekends were training classes for Sankalp employees, new grads or experienced. As I said before, training was and it is, one of my favourite activities even so it was for food and board 😊

In 2013 when PMC Sierra decided to ramp down the layout team in North America I had to look for something else interesting to do. As Sankalp was my account from 2007 I knew the management, the infrastructure and most of the people, around 500 at that time. I figured that I can rebuilt some of the layout capabilities in Canada but I needed help from a low cost & big size partner. The obvious option was to join Sankalp and start a Canadian office in Ottawa.

All good but I cannot do only management and business, needed to get back to the “fun” activities: tools, flows, mentoring and training. One of the activities I am very proud of started with Mohan R and Sati Patil, the only CAD guy in 2013. We wanted to improve Sankalp productivity and grow people interest in automation. So we put together a plan:

1. First Sati built an internal Central CAD website where we uploaded all possible training materials we could find. DAC proceedings, CDN Live papers, vendors tools manuals, white papers, etc.

2. We worked on specialised training materials for CAD people so we can grow the group, organic again. We developed a full ticketing system to ensure the voice of inventors and innovators is recorded and addressed. This work helped building a new breed of experts with scripting skills, not only layout or design. Today Sati has more than 40 people in automation…

3. We agreed that the biggest ROI for an internal automation is “migration”. A lot of customers came to Sankalp and asked for small modifications, derivatives of IP or just IP migration between processes in the same technology node or different.

4. We also wanted to solve another Sankalp reality: even so our trainees for all specialties were much better prepared than other new grads or juniors, all customers wanted people with 2+ years’ experience in their projects.

5. Based on my personal knowledge on “compaction & migration” tools (Rubicad, Sagantec, Magma, Qdesign (Cadence VLM), etc.) I knew that we cannot succeed where more money and better trained resources failed.

We decided to build a Platform (not a software) for IP Process Migration.

I worked with 3 people: Sati Patil for CAD, Sumit Bhat for Circuit Design and Uday Pendse for Layout. For about 1 month we had brainstorming sessions to figure out the flow and then decided to put everything in a “marketing presentation” so Mrinal Das can review and approve project development and budget. We had options and processes, efforts and schedules so once we got the green light the team hit the ground running.
Sankalp can migrate analog/full custom IP today (not digital standard cell blocks or memories) and we can also help the customer make decisions. While in PMC we asked service providers if our blocks are migrate-able and the answer was always “sure”. It most cases proved to be wrong so I wanted a feasibility gate in this migration platform.

What is Sankalp Migration platform : and entire environment that contains scripts, decision points, built around CADENCE software, verification tools and a lot of manual labour. Tools cannot solve more than 80% of technology design rules so we are using the 0-2 years’ experience juniors with a few experts to bring the results to 100% compliance DRC and LVS and performance. This way they get experience in various technologies, different designs, etc. which makes them better prepared for customer challenges and we have a new business offer.
The biggest novelty is the feasibility. We are able to provide of migrate-ability factors to each IP candidate for migration.
1. Simple design rules changes – no layout architecture change (generally for same node different vendors)

2. Design rules changes that will require some layout architecture changes – process node size difference (resistors, capacitors, inductors, etc., do not change linearly with process size)

3. There are design rules limitations that impact circuit design so a circuit modification will be needed including new simulations and ECO – the case of different type of devices not available in destination process – little circuit design and a lot of layout

4. The new process has many different device options, electromigration and RC variants, etc. – a lot of circuit design changes and a lot of layout work but the circuit can me modified

5. Non migrate-able – circuits with inductors, VCO, LNA, big process variation that will require redesign

We can provide all these 5 “migration factors” including effort estimation for each and if customer decides to give Sankalp the job, we can implemented all options internally. I am very happy with this new platform that has 2 years and was used in many engagements, some complete solution and some partial as automation is useful to reduce any design effort. Not only that but parts of this platform automation is used in a variety of projects to improve team productivity.

On the other front, slowly but surely I am working with some of my industry friends to my second edition of CMOS IC Layoutbook planned to bereleased by end of 2018!

The conclusion I want the readers to take home after these 10 articles:

If you are a layout designer who just entered in the industry and wonder what else you can do, look around. Opportunities are everywhere if you want to expand your knowledge, get engaged into other activities related or not to Layout (of polygons), and have fun.

Never wait for others to offer (give, teach) you to grow, go do it on your own, I did!

I started layout in 24 January 1984 and still have fun today!

If you have ideas and would like an advice my email is cometic@ieee.org

If you want to talk to me face to face please visit Sankalp Booth 2457 at DAC 2018 in San Francisco.

Dan Clein

Pushing Polygons Series

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Mentor Siemens Update 2018

Mentor Siemens Update 2018
by Daniel Nenni on 06-04-2018 at 7:00 am
Categories: EDA, Siemens EDA

As you know I am a big fan of disruption and the Siemens acquisition of Mentor is turning out to be one of my favorite EDA disruptions. At first it was a little bit perplexing but after one short year it makes complete sense.

Siemens is acquiring Mentor as part of its Vision 2020 concept to be the Benchmark for the New Industrial Age. It’s a perfect portfolio fit to further expand our digital leadership and set the pace in the industry,” said Joe Kaeser, President and CEO of Siemens AG.

Just a quick example: User groups are a great source of information and customer engagement. EDA has a long history of user group meetings and I have attended more than my fair share of them. Great content, free food, excellent networking, and free food. This week is the Siemens PLM Connection user led conference in Phoenix Arizona. Last year close to 3,000 people attended from all over the world and they expect even more this year. Mentor is now part of PLM Connection and will be presenting more than 50 of the 400+ sessions. After the American PLM Connection event there will be one in Russia, China, Japan and Europe. Compare this with the hundreds of people that attend the average EDA user group and you will see what I mean by EDA disruption.

If you haven’t read the Siemens Wikipedia page you should take a quick look. What an incredible 171 year history with a very strong position for the future. My favorite part is the acquisitions section, Siemens is not shy about acquisitions. Not listed yet are Solido, Sarakol, and Infolyitica which are mentioned in the video below. Solido of course was the absolute best EDA acquisition of 2017 according to me.

If you want a quick update on the CAD software side of Siemens here is an interesting video with Tony Hemmelgarn, President and CEO, Siemens PLM Software and Wally Rhines, President and CEO, Mentor, a Siemens business. It’s just under 12 minutes but for those of you who don’t like videos here is the my take on the Mentor part:

Wally first talked about the Mentor integration with Siemens. According to Wally, customers are excited. From what I have seen and heard customers are not just excited, they are now believers in the Siemens industrial automation vision. The great cultural blend was also mentioned and supported by low single digit employee turnover.

This year has been an all time growth record for Mentor and the momentum continues with synergistic system level product integration with Siemens. Growth was faster than possible than when they were a separate company for sure. Large customer renewals grew 32% relative to prior contracts in terms of annualized run rate with strength across all of Mentor products. Mentor also saw continued improvement in customer satisfaction (via a survey).

The strong semiconductor market has certainly helped Mentor but there is more to the story. Example: Since the acquisition, Mentor initiated and developed a new Calibre product for memories resulting in a $50M order from a leading memory manufacturer. Mentor has also regained the lead in emulation which, from what I have heard from the SoC companies, is correct.

Wally also talked about midterm EDA trends: shrinking and miniaturization, 7nm to 5nm to 3nm where Calibre is the gold standard for verification. AI has taken off with $900M in Q4 2017 investment. Mentor’s leading product Calypto allows companies to develop AI algorithms and synthesize them into silicon. IoT and industrial IoT is causing enormous growth bringing in new companies developing complex products that can serve as sensors and actuators for gateways and edge nodes. Growth of automotive in which Mentor has a large presence representing 20% of their revenue. With leading positions in infotainment, ADAS, embedded software, etc… and continued growth of the semiconductor industry as chip design moves to system design bringing together data from all aspects of design.

No matter how you look at it, this acquisition is one for the record books and will make a nice chapter in Wally’s best selling autobiography, absolutely.

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What Mary Meeker Missed

What Mary Meeker Missed
by Roger C. Lanctot on 06-01-2018 at 12:00 pm
Categories: Automotive, IoT
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It must be a measure of the dim view taken of the automotive industry by Silicon Valley types that of the 294 slides in Mary Meeker’s annual Trends presentation delivered at this year’s Code Conference less than 10 of those slides refer to transportation. The Kleiner Perkins Caufield & Byers partner even managed to avoid using the word “car.”

With the main headline of the much-anticipated report being that the globe has achieved peak smartphone sales, with little new growth to be had, the opportunity to recognize the inexorable upward march of vehicle sales was overlooked. (An analysis of the report and the slides can be found here: https://tinyurl.com/ydbk7qf7 – care of Recode.)

This oversight is especially notable given the report’s focus on data collection. The car has rapidly emerged as the new frontier for data gathering as autonomous vehicle technology begins to take hold. Concerns surrounding data privacy are swirling across the worlds of social media and mobile devices, while car companies are beginning to lay the groundwork for an opt-in culture tuned to the needs of an increasingly connected transportation industry.

Dim view or not, the A-Team – Apple, Alphabet and Amazon – are all keenly interested in exploiting the unexplored world of vehicle data for marketing purposes with voice-based digital assistants capable of converting the car into a browser on wheels. But leading players in the world of transportation, such as Uber and Tesla, recognize deeper stores of value in using vehicle data to improving transportation experiences and business models and processes.

The car is the ultimate mobile device and it happens to serve the most inefficient business in the world: transportation. Massive amounts of metal are used to move people and goods across crumbling infrastructure at great cost and with relatively low utilization rates (at least of the vehicles themselves).

Upping the efficiency of the transportation network will require oceans of data to optimize transportation networks for ad hoc, on-demand services such as ride hailing, but also to improve public transportation options and to refine subscription-based vehicle usage models. At the core of transportation inefficiency is the increasingly tenuous vehicle ownership proposition.

In her talk, Meeker does highlight the growing inclination of consumer households to rely on on-demand transportation options in lieu of vehicle ownership. This behavior is reflected in the declining portion of household spending devoted to transportation even as cars continue to become more expensive.

Meeker is highlights the shift to cheaper ad hoc transportation options and lauds Uber’s algorhythmic acumen. So, she steps up to the edge of the question of potentially declining vehicle ownership but steps back before making the logical leap. It is almost as if cars are irrelevant in her calculations or at least a major blind spot.

In developed markets such as North America and Europe, vehicle ownership does appear to be in some peril. Ride hailing and car sharing options – along with proliferating public transportation options – are putting pressure on the ownership proposition. In Europe and China, there are active measures to limit the use of cars in traffic-clogged or pollution-choked cities (Europe) or to using licensing limits to make it difficult to obtain a car (China).

In spite of these obstacles, global vehicle sales are forecast to climb at a compound annual rate of 2.5% through at least 2025, rising to more than 112M vehicles annually and on a trajectory to 120M. While the developed world may be bumping up against peak vehicle sales and ownership, the developing world is only just beginning to explore its very own love affair with cars.

Data is at the core of preserving vehicle relevance in both worlds. Data is also at the heart of the market disruptions wrought by Uber and Tesla.

Both Uber and Tesla capture transportation related data. The customer opt-in is more or less a requirement. How do they do it and why do consumers accept it? Because the trade-off is implicit.

Just as Google provides free search in exchange for using your search behavior as a basis for advertising (and for the privilege of manipulating your search results) Uber provides a discounted taxi service in exchange for the data it collects. The data that Uber collects – regarding a substantial proportion of local ad hoc transportation activity – is gold.

By now Uber knows the most popular routes in and around 100’s of major cities around the world. The company knows how to manage the supply and demand of transportation services and also knows a lot about driver and passenger behavior. Uber is in position to advise municipalities regarding multimodal transportation infrastructure, parking, and traffic and may even be able to advise on congestion mitigation solutions – even though Uber itself is a major contributor to that congestion.

The ocean of data gathered on a daily basis by Tesla is rapidly advancing the company toward the autonomous vehicle future by enabling the company to gather essential information regarding driving behavior and driving conditions. Tesla has also managed to convert the thousands of Tesla drivers using its autopilot feature into human guinea pigs helping Tesla understand when and where humans have to take control of the driving task from the system – and even helping Tesla understand when and why the system fails.[

Tesla’s data collection activity is providing the company with advanced electric vehicle insights regarding the number and type of trips taken, the impact of driving behavior on battery performance and the long-term performance of the vehicle batteries. Tesla by now knows far more than any other electric vehicle company about the ideal locations for charging stations and consumer behavior associated with the charging activity.

Just as Uber provides discounted taxi rides in exchange for data, Tesla’s value exchange is in the form of software updates. Tesla will continue to enhance the value of your “ride” as long as you’re still opted into the data sharing proposition – though it’s not as if you have a choice.

Uber and Tesla are creating and delivering value related to the driving experience in exchange for the data they collect. Notably, both companies have eschewed leveraging vehicle data for annoying and intrusive marketing messages.

A quick side note here: Waze is another transportation-centric application that has built its brand on data aggregation. It is worth noting that Waze is seeming to lose its way of late with an increasing emphasis on those very distracting advertising and marketing messages during navigation that Tesla and Uber have skirted.

Some analysts have suggested that the value of vehicle data is such that cars ought to be or will someday be free to consumers in exchange for access to the vehicle data. The closest approximation to this value proposition is Hyundai’s WaiveCar program which allows Hyundai Ioniq drivers to use the car for free as long as they allow WaiveCar to load the car with external advertising signage.

The idea of a free car is no less compelling than the idea of a free smartphone – but neither of these propositions are likely. What is more likely is an exchange of value, in the case of the car, that enhances the safety or efficiency of the driving experience. An example: Tesla just updated its Autopilot software to lengthen the stopping distance associated with the system in order to get back in the good graces of Consumer Reports.

The greater existential problem facing the automotive industry, though, is efficiency. Cars are only used 3%-4% of the time. This fundamental inefficiency is spurring the consumer consideration of less expensive alternatives, such as Uber, Lyft, Car2Go etc.

Car companies seeking a long term future beyond selling large volumes of vehicles primarily in emerging markets will do well to shift their focus to leveraging vehicle data to enhance the efficiency of vehicle usage by enabling and supporting networked transportation services such as car sharing, ride hailing and subscription-based “ownership.” These new forms of networked customer engagement will help preserve the relevance of cars in a world of inefficient automobile-centric transportation.

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Imec Technology Forum: Gary Patton of GLOBALFOUNDRIES

Imec Technology Forum: Gary Patton of GLOBALFOUNDRIES
by Scotten Jones on 05-31-2018 at 12:00 pm
Categories: Events, FD-SOI, FinFET, Foundries, GlobalFoundries
17 Comments

The imec technology forum was held in Belgium last week. At the forum I had a chance to sit down with Gary Patton the CTO of GLOBALFOUNDRIES (GF) for an interview and he also presented “Enabling Connected Intelligence – Technology innovation: Enablers for an intelligent future” at the forum. In this article I will discuss what I see as the keys points from the presentation and interview.
Continue reading “Imec Technology Forum: Gary Patton of GLOBALFOUNDRIES”

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CEO Interview: Jason Oberg of Tortuga Logic

CEO Interview: Jason Oberg of Tortuga Logic
by Bernard Murphy on 05-31-2018 at 7:00 am
Categories: CEO Interviews, EDA, IP, Security, Tortuga Logic

I first met Jason Oberg, CEO and one of the co-founders of Tortuga Logic, several years ago when I was still at Atrenta. At that time Jason and Jonny Valamehr (also a co-founder and the COO) were looking for partners. The timing wasn’t right, but we’ve stayed in touch, for my part because their area of focus (security) is hot and likely to remain hot.

Jason has a PhD in hardware security from UCSD around timing side-channels, supervised by Ryan Kastner. Jonny is also a PhD in hardware security, from UCSB supervised by Tim Sherwood. They formed the company in the summer of 2014, funded by an NSF grant and a small business innovation research (SBIR) grant. They started in an incubator in San Diego and have now branched out, moving their head office to San Jose where we met for this interview:

What does Tortuga Logic do?
Everything related to securing hardware, which needs to cover a lot of security approaches, from the hardware/software boundary, through secure boot, to protection of privileged assets, resources and more. We believe strongly in the need for a secure design lifecycle, spanning the design and verification chain and extending even into post-silicon. Of course there are a number of security offerings today, from IP to formal-based tools, each of which have important roles to play, but on their own these are insufficient to provide a high assurance of system security. Our role is to complement these as I’ll explain shortly.

Incidentally, Tortuga doesn’t currently look at physical security concerns, such as power side-channels, PUFs and TRNG validation.

We have seen a lot of hardware security vulnerabilities recently. What’s your view on why and what are the challenges and opportunities in this space?
First let’s get rid of a possible misunderstanding. In big companies at least, this isn’t because designers are careless or don’t know what they are doing; many of these companies have large and very expert security teams. The real issue is that the range of possible problems is effectively unbounded, and therefore practical security, like safety, must be driven by an ROI calculation. What are the reasonably conceivable problems against which you are willing to defend? You have to draw a line somewhere because you can’t imagine all possibilities; even correcting for those you can imagine will have some consequences in cost, performance and power. Like it or not, you’ll have to trade off security in some areas against other objectives

Based on the judgement of your internal experts, you draw that line and make a conscious decision that whatever is on the other side of the line is too difficult to exploit. Over time, exploits become more sophisticated and what was once inconceivable or too difficult to exploit becomes conceivable. This is just the nature of security.

Smaller companies and teams don’t have armies of security experts, so face bigger challenges. First, they don’t have as much expertise in where to draw the line or what might lurk on the other side. And second, while they can and should use proven security IP and tools, those alone do not guarantee their systems will be secure. You can use security features incorrectly just as you can use any other feature incorrectly, and some of those bugs can be quite subtle. So the burden is still on the system designer to verify that their system is secure. Formal plays an important role in validating some integration characteristics but it can’t uncover potential problems in hardware/software interaction for example.

Certainly an opportunity here is to provide metrics and tools to analyze the vulnerabilities of a design, especially to simplify/standardize this task. The ideal is to create a security verification plan and ultimately an audit trail to be able to demonstrate your path to security. You could imagine a goal to demonstrate some standardized level of security in an auditable process, not unlike what we do today for safety. Microsoft has one good example (for software) in their Security Development Lifecycle (SDL) where they do up-front threat-modeling followed by threat model-aware architecture, design and verification.

How are Tortuga Logic’s solutions different from other offerings in this space?
A Tortuga user starts with threat modeling. A very important point to understand is that this doesn’t mean listing known or possible vulnerabilities. It means rather building a description of all the things you want to protect, e.g. assets and keys, along with all the possible ways those assets can be accessed. Think of this as a way to characterize the complete problem space before drilling down to discover and analyze specific vulnerabilities, which is where many system security methods start today. Based on that top-down analysis, Tortuga can then build analytics to assess vulnerabilities, to determine the effectiveness of protection methods against attacks you know about, also to help you understand what you haven’t considered.

The product next takes as input your design files and security rules based on this threat modeling and generates a security monitor model in the form of synthesizable IP which can be inserted in the design. There are several reasons we took this approach. First, this model sits in the existing verification environment, monitoring for potential weaknesses. It requires no change to the verification environment such as testbenches, so adds minimal overhead for the verification team. Because it is synthesizable, it can be run in emulation and FPGA prototyping, which means you can continue to monitor for weaknesses during HW/SW testing. You can even use our models with formal. This is an end-to-end solution across the verification flow.

Who is using your products?
We’re bound by the same constraints as other suppliers, so we’re limited in sharing names. I can tell you that we have been working for some time with government research labs, also large aerospace and defense primes. We have publicly announced a relationship with Xilinx who are working with us on both internal and external security objectives. We are also working with large processor companies exposed to the Meltdown and Spectre problems.

Where can people learn more about Tortuga?
Check out the whitepapers on our website and of course feel free to contact us (we’re very actively staffing up so welcome new engagements). We’ll also be at DAC. We won’t have a booth, but we plan to present at some of the major EDA vendor booths.

Also Read:

CEO Interview: YJ Su of Anaglobe

CEO Interview: Ramy Iskander of Intento Design

CEO Interview: Rene Donkers of Fractal Technologies

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Top 10 Highlights from the Samsung Foundry Forum

Top 10 Highlights from the Samsung Foundry Forum
by Tom Dillinger on 05-30-2018 at 9:00 am
Categories: FD-SOI, FinFET, Foundries, Samsung Foundry
9 Comments

Samsung Foundry recently held their annual technology forum in Santa Clara CA. The forum consisted of: presentations on advanced and mainstream process technology roadmaps; the IP readiness for those technology nodes; a review of several unique package offerings; and, an informal panel discussion with IP designers and EDA flow developers describing their recent collaborations with Samsung Foundry. Here are the (very subjective) highlights of the presentations and panel discussion.
Continue reading “Top 10 Highlights from the Samsung Foundry Forum”

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Webinar: Custom SoCs for Narrowband IoT

Webinar: Custom SoCs for Narrowband IoT
by Daniel Nenni on 05-30-2018 at 7:00 am
Categories: Ceva, IoT, Open-Silicon, Semiconductor Services

This joint CEVA and Open-Silicon webinar, moderated by myself, will elaborate on Narrowband IoT (NB-IoT) custom SoC solutions that are based on the CEVA-Dragonfly IP subsystem, and serve a wide range of cost- and power-sensitive IoT applications. Those joining the webinar will learn about the CEVA-Dragonfly NB1 IP subsystem, which pre-integrates the CEVA-X1 processor, optimized RF, baseband, and protocol software to offer a complete NB-IoT modem IP solution that can be extended seamlessly with GNSS and sensor fusion functionality.

Registration
Date: Tuesday, June 19, 2018
Time: 8 a.m. PST / 11 a.m. EST
Duration: 60 mins

The webinar will also address Open-Silicon’s NB-IoT custom SoC platform and software SDK, and how they enable customers to differentiate within the silicon with robust security and proprietary accelerator features with reduced risk, development schedule and cost.

The panelists will discuss the role of turnkey custom SoCs in lowering entry barriers, reducing time-to-market, increasing performance, adding security, and facilitating customization and scalability. The panelists will present sample use case platforms and explain how custom SoCs can enable product differentiation and total cost of ownership (TCO) savings for the next generation of NB-IoT applications.

This webinar is ideal for hardware designers and system architects of NB-IoT equipment/modules.

Speakers:

Emmanuel Gresset
Business Development Director, CEVA
Emmanuel is a Business Development Director in CEVA Wireless BU. For the last 30 years, Mr. Gresset has been with systems and semiconductor companies working in the fields of signal processing, wireless modems as well as processor and system-on-a-chip architecture in various companies: Octasic, STMicroelectronics, Philips, VLSI Technology, Spectral Innovations and Thomson. He received his M.Eng from the Ecole Supérieure d’Electricité in Paris.

Pradeep Sukumaran
Director, Systems & Software, Ignitarium
Pradeep Sukumaran is Director, Systems & Software at Ignitarium, a front-end design and software consulting company of Open-Silicon. Ignitarium offers high end VLSI and SW solutions to customers, with a strong focus on IoT and Vision Intelligence technology. Pradeep has over 17 years of experience in the embedded software and systems domain. Prior to Ignitarium, he was Senior Solutions Architect at Open-Silicon.

Naveen HN
Engineering Manager, Open-Silicon
Naveen HN is an engineering manager for Open-Silicon. He oversees board design, post-silicon validation and system architecture. He also facilitates Open-Silicon’s SerDes Technology Center of Excellence and is instrumental in the company’s strategic initiatives. He has over 16 years of experience in various domains of embedded systems design. Naveen is an active participant in the IoT for Smart City Task Force, which is an industry body that defines IoT requirements for smart cities in India. He received his M. Tech from SJCE, Mysore.

About CEVA, Inc.
CEVA is the leading licensor of signal processing platforms and artificial intelligence processors for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, industrial and IoT. Our ultra-low-power IPs for vision, audio, communications and connectivity include comprehensive DSP-based platforms for LTE/LTE-A/5G baseband processing in handsets, infrastructure and machine-to-machine devices, advanced imaging and computer vision for any camera-enabled device, audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For artificial intelligence, we offer a family of AI processors capable of handling the complete gamut of neural network workloads, on-device. For connectivity, we offer the industry’s most widely adopted IPs for Bluetooth (low energy and dual mode) and Wi-Fi (802.11 a/b/g/n/ac/ax up to 4×4). To learn more, visit us at www.ceva-dsp.com

About Open-Silicon, Inc.
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 135 million ASICs to date. To learn more, visit www.open-silicon.com

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ISO 26262 First – ASIL-D Ready Vision Processor IP Available

ISO 26262 First – ASIL-D Ready Vision Processor IP Available
by Tom Simon on 05-29-2018 at 12:00 pm
Categories: Automotive, EDA, IP, Synopsys

Synopsys made a pretty major announcement regarding their new ASIL-B,C and D ready embedded vision processor IP. This matters because you cannot bolt on the design elements and features needed to achieve these ASIL levels later, and this IP is absolutely necessary for ADAS systems and other critical safety systems in automobiles. These features have to be baked into the architecture, and the tools necessary to support them also need to be available. Simultaneously, Synopsys has gone to great lengths to ensure that the added safety features have minimal impact on performance.

So, what exactly are some of these features? Their press release itemizes them: “lockstep capabilities, ECC memories, error checking on core registers and safety-critical registers, a dedicated safety monitor, and a windowed watchdog timer for each core. An optional dedicated safety island monitors and executes safety escalations and diagnostics within the SoC and protects system bring-up”.

However, a list of safety features is not enough, there are a few more essential elements needed to crack the barrier to successfully implementing a vision processor based SOC for a system that complies with ISO 26262. Performance and capability are the first two major items to check off. The other necessary piece is development tools that are also ASIL ready. Let’s talk about these in order. I was fortunate enough to chat with Gordon Cooper, Product Marketing Manager at Synopsys for EV processors, about these topics. Much of what he discussed went beyond the press release and made it easier to understand their latest announcement.

Gordon told me that the crux of the announcement is that they have added the Safety Enhancement Package to their EV6x family of vision processors. Also, they have added vector processing that runs up to 1.2GHz with a 10 stage pipeline. The 1.2GHz speed, he pointed out, is at worst case for automotive standard conditions of 125 to -40 C in 16FF. Performance like this is much harder to achieve in these conditions, however they represent what is commonly found in automotive operating environments. Gordon emphasized that benchmarking for these applications is extremely important, it’s not enough to read a spec sheet and try to make a decision.

Gordon talked about data processing requirements for these systems as well. They are seeing 3-4 megapixel image sizes at frame rates of 30 fps, and increasing. By 2020 there will be over 24 cameras per vehicle as well as radar, all with higher resolutions. Yet, for different tasks, there needs to be differentiation in the kind of processor that is required. For instance, monitoring a driver’s face to detect distracted driving is a far different task than pedestrian or object detection. Synopsys offers different configurations of its EV6x family for each of these categories of tasks.

Gordon says that after thorough examination they have decided that 8 or 12 bit precision is preferred to the 16 bit precision often used. TensorFlow coefficients start out as 32 bit float, but they are quantized to 12 or 8 bits for recognition applications, with 8 bit being suitable in most instances.

On the tools side, they have invested in creating the documentation necessary to facilitate ASIL-D qualification. The tool chain has EV runtime and libraries, including OpenVX and OpenCV kernel libraries. They support C/C++ and OpenCL for developing applications and vision kernels. In addition, there is comprehensive debugging tool support. Synopsys also has a CNN graph mapping tool that helps mapping to the CNN engine. System level simulation support is available with system level models for host and EV processors.

Synopsys already has a large presence in the automotive market. Their processors are used in almost every application within that space. They already have customers who have taken some of the ASIL-D ready EV6x family to silicon. Availability of this IP will help accelerate ISO 26262 certification. Gordon also made it clear that they are going to be supplying their customers with a steady stream of updates to ensure they benefit from the latest research in vision processing. There is extensive material available on their website about the EV6x vision processor family and the Safety Enhancement Package that provides ASIL-D readiness.