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February 8, 2018

Webinar: Multiphysics Reliability Signoff for Next-Generation Automotive Electronics Systems

Webinar: Multiphysics Reliability Signoff for Next-Generation Automotive Electronics Systems
by Bernard Murphy on 02-08-2018 at 7:00 am
Categories: Ansys, Inc., Automotive, EDA, Foundries, TSMC

In case you missed the TSMC event, ANSYS and TSMC are going to reprise a very important topic – signing-off reliability for ADAS and semi-autonomous /autonomous systems. This topic hasn’t had a lot of media attention amid the glamor and glitz of what might be possible in driverless cars. But it now seems like the cold light of real engineering needs are advancing over the hype, if this year’s CES is any indication (see my previous blog on CES). Part of that engineering reality is ensuring not only that we can build these clever systems but that they will also continue to work for a respectable amount of time; in other words that they will be reliable, a topic as relevant for today’s advanced automotive electronics as it is for the systems of tomorrow.

This topic is becoming a pressing concern, especially for FinFET-based designs. There are multiple issues impacting aging, stress and other factors. Just one root-cause should by now be well-known – the self-heating problem in FinFET devices. In planar devices, heat generated inside a transistor can escape largely through the substrate. But in a FinFET, dielectric is wrapped around the fin structure and, since dielectrics generally are poor thermal conductors, heat can’t as easily escape leading to a local temperature increase, and will ultimately escape significantly through local interconnect leading to additional heating in that interconnect. Add to that increased Joule heating thanks to higher drive and thinner interconnect and you can see why reliability becomes important.

ANSYS has developed an amazingly comprehensive range of solutions for design for reliability, spanning thermal, EM, ESD, EMC, stress and aging concerns. In building solutions like this, they work very closely with TSMC, so much so that they got three partner of the year awards at the most recent TSMC OIP conference!

Incidentally my CES-related blog is here: https://www.legacy.semiwiki.com/forum/content/7274-ces-exhibitor-s-takeaway.html

Summary
Design for reliability is a key consideration for the successful use of next-generation systems-on-chip (SoCs) in ADAS, infotainment and other critical automotive electronics systems. The SoCs manufactured with TSMC’s 16FFC process are advanced multicore designs with significantly higher levels of integration, functionality and operating speed. These SoCs must meet the rigorous requirements for automotive electronics functional safety and reliability.

Working together, ANSYS and TSMC have defined workflows that enable electromigration, thermal and ESD verification and signoff across the design chain (IP to SoC to package to system). Within the comprehensive workflows, multiphysics simulations capture the various failure mechanisms and provide signoff confidence not only to guarantee first-time product success, but also to ensure regulatory compliance.

Attend this ANSYS and TSMC webinar to learn about ANSYS’ chip-package-system reliability signoff solutions for creating robust and reliable electronics systems for next-generation automotive applications, and to explore case studies based on TSMC’s N16FFC technology.

Founded in 1970, ANSYS employs nearly 3,000 professionals, many of whom are expert M.S. and Ph.D.-level engineers in finite element analysis, computational fluid dynamics, electronics, semiconductors, embedded software and design optimization. Our exceptional staff is passionate about pushing the limits of world-class simulation technology so our customers can turn their design concepts into successful, innovative products faster and at lower cost. As a measure of our success in attaining these goals, ANSYS has been recognized as one of the world’s most innovative companies by prestigious publications such as Bloomberg Businessweek and FORTUNE magazines.

For more information, view the ANSYS corporate brochure.

February 7, 2018July 18, 2025

Machine Learning And Design Into 2018 – A Quick Recap

Machine Learning And Design Into 2018 – A Quick Recap
by Alex Tan on 02-07-2018 at 3:00 pm
Categories: AI, Cadence, EDA, Events, Foundries, Synopsys, TSMC

How could we differentiate between deep learning and machine learning as there are many ways of describing them? A simple definition of these software terms can be found here. Let’s look into Artificial Intelligence (AI), which was coined back in 1956. The term AI can be defined as human intelligence exhibited by machines. While machine learning is an approach to achieve AI and deep learning is a technique for implementing subset of machine learning.

During last year 30-Year Anniversary of TSMC Forum, nVidia CEO Jen-Hsen Huang mentioned two concurrent dynamics disrupting the computer industry today, i.e.,how software development is done by means of deep learning and how computing is done through the more adoption of GPU as replacement to single-threaded/multi-core CPU, which is no longer scale and satisfy the current increased computing needs. The following charts illustrate his message.

At this month Santa Clara DesignCon2018 there were multiple well-attended sessions (2 panels and 1workshop) addressing Machine Learning Advances in Electronic Design. Highlighted by panelists coming from 3 different areas (EDA, industry and academia) were some successful snapshots of ML application in optimizing design and its potential consequences as how we should handle the generated models and methodologies.

From the industry:
Chris Cheng, a Distinguished Engineer from HPE presented a more holistic view of ML potential use coupled with test instruments as substitute for a software model based channel analysis. He also projected ML use to perform more proactive failure prediction of signal buses or complicated hardware such as solid-state drives.

Ken Wu, Google Staff HW Engineer shared his works on applying ML in channel modeling. He proposed the use of ML to predict channel’s eye-diagram metrics for signal integrity analysis. The learned models can be used to circumvent the need of performing complex and expensive circuit simulations. He believes ML opens an array of opportunity for channel modeling such as extending it to analyze the four-level pulse amplitude modulation (PAM-4) signaling, and the use of Deep Neural Network for Design of Experiment (DOE).

Dale Becker, IBM Chief Engineer of Electronic Packaging Integration, alluded to the potential dilemma imposed by ML. Does it supersede today’s circuit/channel simulation techniques, or is it synergistic? With the current design methodologies still reflecting heavy human interventions (such as in channel diagnostics, evaluation, optimization, physical implementation), ML presents an opportunity for exploration. On the other side of the equation, we need to be ready to address standardization, information sharing and IP protection.

From the EDA world, both Synopsys and Cadence were represented:

Cadence team — David White (Sr. Group Director), Kumar Keshavan (Sr. Software Architect) and Ken Willis (Product Engineering Architect) highlighted Cadence contribution in advancing ML adoption. David shared what Cadence has achieved with ML over the years on Virtuoso product and raised the crucial challenge of productizing ML. For a more in-depth coverage for David’s similar presentation on ML, please refer to another Wiki article TSMC EDA 2.0 With Machine Learning – Are We There Yet ? Kumar delved into Artificial Neural Network (ANN) concept and suggested its application for DOE of LPDDR4 bus. Ken Willis was moderating the afternoon panel and highlighted the recently introduced IBIS ML versus AMI model as well as impact of ML on solution space analysis.

Sashi Obilisetty, Synopsys R&D Director pointed out that the EDA ecosystem comprising of academic research, technology availability and industry interest) is ready and engaged. What we need is a robust, scalable, hi-performance and near real time data platform for ML application.

Several academia also shared their research progress under the auspice of Center for Advanced Electronics Through Machine Learning (CAEML) since its formation in 2016:

Prof. PaulFranzon discussed how ML could shorten IC physical design step through the use of surrogate model. The concept is to train a fast global model to evaluate from multiple evaluations of a detailed model that is slow to evaluate. Given an SOC design requiring a 40 minute per route iteration, the team needs about 50 runs to complete the Kriging based model overnight. Using this model, an optimal design can be obtained in 4 iterations which otherwise requires 20 iterations. The design has 18K gates derived from Cortex-M0 with 10ns cycle time and 45nm generic process.

Prof. Madhavan Swaminathan presented another application of ML based solution using surrogate model on channel performance simulation.

His view: Engineer (thinker) + ML (enabler) + Computers (doers) = enhanced solution. Extending ML into design optimization through active learning may ensure convergence to global optima and minimizing required CPU time.

With the increased design activities and research efforts in ML/DL applications, we should anticipate more coverage of such implementation into 2018. The next question would be if it will create a synergy and enhance design efforts through retooling and methodology adjustments, or it will create disruption that may change the human designer roles at different junctures of design capture. We should see.

February 7, 2018September 1, 2024

High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory

High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory
by Mitch Heins on 02-07-2018 at 10:00 am
Categories: eSilicon, FinFET, IP, Samsung Foundry
5 Comments

High Bandwidth Memory (HBM) systems have been successfully used for some time now in the network switching and high-performance computing (HPC) spaces. Now, adding fuel to the HBM fire, there is another market that shares similar system requirements as HPC and that is Artificial Intelligence (AI), especially AI systems doing real-time image recognition. I traded notes with Mike Gianfagna at eSilicon to get more information and he pointed me to a webinar that eSilicon had recently presented (link below) in conjunction with Samsung, Rambus, Northwest Logic and the ASE group.

I reviewed the webinar recordings to which Mike had referred me and learned a great deal more about HBM-based systems. According to Lisa Minwell of eSilicon, both networking and AI applications typically have large ASIC die, greater than 400mm[SUP]2[/SUP], containing high-performance cores, up to 1 gigabit of configurable multi-port embedded memories, and high-bandwidth wide-word interfaces to HBM2 stacked memories all integrated in a 2.5D system-in-a-package (SiP).

These SiPs use cutting-edge technology and as a result are complex and require an ecosystem of partners to ensure successful design, implementation and test. And that, as it turns out, was exactly what the webinar was about.

The webinar had a ridiculously long title, something like “FinFET ASICs for Networking, Data Center, AI, and 5G using 14nm 2.5D HBM2 and SERDES”. I think that was more for Google search engines – and so I include it here as well. True to form though, the webinar did in fact cover all those topics and at pretty good depth, much more than I can summarize here. As mentioned, the webinar included panelists from the companies listed above and covered the following areas:

HBM2 memories – Samsung Electronics
14nm FinFET silicon – Samsung Foundry
2.5D packaging, interposers assembly/test and micro-bump road maps – the ASE group
ASIC design services, configurable memory compilers and PHY IP – eSilicon
High-speed SERDES IP – Rambus
HBM2 memory controller IP – Northwest Logic

Each company gave a brief overview of their offerings along with road map data for their part in the overall solution. There was a ton of excellent data in the webinar that simply would not fit in this space. If you are interested in road map data for any of these areas, please make sure to follow the link below to watch the webinar. The recording is indexed by subject matter so that you can quickly go to the section of your interest.

One thing all the members made sure to point out was that this wasn’t “futures” work. The work they were doing with HBM2 was being used in real products with significant performance, power and area improvements for their customers. Note the ~2.5X improvement in overall system performance gained over DDR architectures when using HMB2. HBM3 (generation 3), due out sometime toward the end of the decade, is supposed to have 2X more performance than HBM2.

One of the interesting parts of this type of design is that you are dealing with multiple components from different companies. The tricky part of course is where to look when things don’t work as planned. This is where the eco-system partners were all quick to jump in and ensure their listeners that they were all there to work out any issues that come up. And… given their previous history of working with each other, the message was clear that they had figured out how to do this in an efficient manner.

The other thing that came across from the webinar is that none of the systems that were discussed were exactly alike. In fact, just the opposite was true. While they all shared common characteristics, each design had been customized in some way and it was evident that each of the eco-system partners were prepared to help their customer in this customization process, whether that meant changing the amount or speed of the HBM2 stack, customizing different memory mapping for the stack, creating unique multi-port embedded memories for the ASIC, customizing a set of SERDES or a creating a customized interposer.

And that, is what makes their joint solution so compelling. It is the ability to use and customize a design using production proven 14nm FinFET technology with silicon verified IP blocks that have been verified against each other. That’s hard to do when all the pieces are coming from different places. If you are doing networking, HPC or AI applications you may want to check out this webinar at the link below!

February 6, 2018November 22, 2019

Increased Processing Power Moves to Edge

Increased Processing Power Moves to Edge
by Tom Simon on 02-06-2018 at 12:00 pm
Categories: 5G, Achronix, Automotive, eFPGA, FPGA, IP

Recently there has been a lot of buzz about 5G networks. Aside from the talk about it possibly being nationalized, 5G will be a lot different than its predecessors. Rather than a single data link in a predetermined band, 5G will consist of a web of connections all working together to support existing types of data traffic and many new types, including automotive, IoT and others. In urban areas, there will be a large number of smaller nodes using GHz bands that do not travel far. Also, it will support IoT and automotive data traffic traffic that will require low latency and packet sizes suited to the data payloads.

Many of the effects of this shift in mobile data architecture are readily understandable, but there are other more subtle shifts in data communication and processing that are going to affect where compute resources are deployed. We live in the era of cloud computing. This is exemplified by light weight edge computing power augmented by heavy duty processing resources in the cloud. Many tasks manifest only as a user interface or have low compute requirements on edge devices, and the heavy lifting is done at data centers.

However, we are about to enter another cycle where the location of processing activity makes a significant migration. IoT and the automotive communications known as V2V (vehicle to vehicle) and V2X (vehicle to other) demand lower latency and more localized processing. A recent white paper by Achronix talks about these trends and the requirements they will impose on processing devices. The paper, “2018 Ushers in a Renewed Push to the Edge”, provides many specific examples of why edge processing demands will expand significantly.

Coming back to 5G, one of the new capabilities will be millisecond latency. Older networks have much higher latency and extended backhaul routing can add to huge delays to system responsiveness. In the case of moving vehicles dealing with their environment or other vehicles, time is of the essence. V2X is one of the more interesting topics. Roadside beacons can aggregate and communicate information about road surface conditions, traffic, obstacles, and other cars. V2V can be used to enhance safety to broadcast obscured hazard information.

Another harbinger of how computing is moving to the edge that is discussed in the Achronix white paper are services like Amazon Web Services’ Greengrass offering. Instead of requiring all network traffic to return to AWS for processing, Greengrass lets system designers define IoT based applications in the cloud and then instantiate them in remote/edge processing nodes that can operate without an active connection to AWS. An edge processing unit is used to network IoT devices to create a local IoT network. One example is in a hospital where there might be pulse, temperature and other sensors that can be linked together in a patient’s room to provide intelligent monitoring.

Greengrass uses Amazon’s flavor of FreeRTOS for the hub at the edge in the processing unit. When internet connections are available the edge processor can update the cloud, but it can operate on its own without the need for a cloud connection.

The drive to add processing power at the edge raises the question of what is the best hardware design for achieving reliability, power, security and performance goals. We have seen, through Microsoft’s Catapult project, how marrying traditional CPU’s and programmable logic can boost server performance. Achronix asserts that the same benefits accrue at the edge. Programmable logic can be uniquely tailored to the specific edge processing needs. FPGA based packet and data processing can occur in parallel with low overhead for a range of tasks. If we look at security needs, because these edge nodes may not reside in physically secure facilities, they need to be fundamentally more secure. Embedded FPGA fabric admittedly is more secure and reduces power. Also, lower part count and reduced board interconnect can lead to better reliability. Achronix makes a convincing case that for many applications that require enhanced edge processing, that their embedded eFPGA fabric is a desirable solution. You should download the paper if you are interested in learning about the other motivations for increased edge processing power, and also to learn about how effective solutions can be architected.

February 6, 2018

CES: An Exhibitor’s Takeaway

CES: An Exhibitor’s Takeaway
by Bernard Murphy on 02-06-2018 at 7:00 am
Categories: AI, Arteris, Automotive, Events, IP

There are few tech promises these days as prominent as those surrounding driverless cars (trucks, buses, …). But thanks to always-on media amplifiers, it’s not always easy to separate potential from reality. I recently talked to Kurt Shuler, VP Marketing at Arteris, who shared his view after returning from this year’s CES. Kurt is much an enthusiast as anyone but pointed immediately to the Gartner media-hype curve, saying that pitches were more muted this year, particularly in moving away from live demos, perhaps thanks to last year’s less than stellar performances. On the hype curve, Kurt feels we’ve moved past peak hype and are now into the long slog of delivery.

He’s not alone in this view. Others are also digging into the details, looking more closely at what it takes to get to different levels of autonomy and are more skeptical that wide-scale autonomy is right around the corner. No-one is saying it’s not going to happen, but reality is setting in on how long it’s going to take. In Kurt’s view, we’re 80% of the way there, but the last 20% is going to take years, maybe even decades.

Which obviously contrasts with the marketing message, since no-one wants to signal that they’re intentionally stretching out plans. Intel are making a big push with their acquisition of Mobileye, however a lot of what they are doing is immediately relevant to ADAS, whether or not autonomy takes longer. Tier1 companies are following a variety of strategies, some building their own systems (HW+SW), others using commercial branded systems under the hood and Baidu, Google Waymo push their big data mining/management advantage, though still unclear to me how far Google will get, given their spotty record on Other Bets.

Among OEMs, there’s a wide spectrum, from Tesla who always market to the hilt and seem to want to boil the ocean as fast as possible (witness now autonomous trucks), to perhaps Volvo who initially said they would offer autonomy in 2020 and now have pulled back, focusing more on driver assistance.

Obviously that last 20% represents the difference between what is possible and what is functionally safe, reliable and cost-effective, as in we’re prepared to let these things on the road in the real world and we can afford them. In our neck of the woods in semiconductor design, solution providers are still working hard to push into products more functionality with the “right” HW/SW and PPA balance. What makes for right depends on perspective. The Tier1s are pushing for more to be done in hardware, especially when integrating their IP, and less in software since that means less software problems to manage in the field, a less complex software BOM and generally a reduced safety/security problem around that software.

This naturally requires jamming more functions into a system on chip. Mobileye is adding more hardware accelerators to the bus and Kurt said that NVIDIA is now adding fixed-point accelerators in their latest architecture. The NVIDIA move shouldn’t be surprising. While they dominate in neural net (NN) training, that’s running in the cloud where power isn’t such a big issue and the MAC instructions central to NNs can use floating-point accelerators. In a car, power is very much an issue, which is why NNs on edge applications (inferencing rather than training) have moved to more power-efficient fixed-point accelerators.

Still on the subject of power, functional safety tends to increase power since it requires levels of redundancy. A common method to mitigate the impact of hardware failures in a CPU (through soft errors for example) is to have two (or more) CPUs doing the same calculations, then compare the results. In other areas, duplication or triplication of logic is common in safety-critical functions. Good for safety, not so good for power.

And while on safety, naturally this demands a very high quality of service, even though there are all these units hanging off the bus, along with traffic from the growing number of sensors around the car. Kurt made the point that when you’re traveling at 70 mph and someone cuts in front of you, that clever electronics has milliseconds to respond; cars don’t stop on a dime. Rolling that back into the system, functions on the bus have to be responding at picosecond levels – reliably, not “most of the time unless bus traffic gets heavy”. This takes very careful optimization and a bus architecture which can support that optimization; I’m pretty sure everyone would agree this has to be a NoC .

One more point on safety. When functionality is divided up between multiple components provided by multiple suppliers and assembled by a solution builder, how does the system builder ensure overall system safety? Through redundancy certainly, but how do they deal with varying or differing levels of safety management between these functions? More responsibility for safety management probably has to fall on or at least be mediated by the interconnect.

Looks like there’s still a lot of hard work to be done to turn autonomy promise into a scalable reality but that shouldn’t be a big surprise. Meantime on-chip interconnect, particularly NoC interconnect, is likely to play a significant role in those solutions. You can learn more about Arteris solutions HERE.

February 5, 2018

Is there anything in VLSI layout other than “pushing polygons”? (6)

Is there anything in VLSI layout other than “pushing polygons”? (6)
by Dan Clein on 02-05-2018 at 12:00 pm
Categories: EDA
8 Comments

I am very sorry but I have to break the flow of sharing initiatives, to reiterate the reason for these articles and maybe amplify the message these articles should promote.

I got a few inquiries from LinkedIn connections, who read the previous articles, with a very interesting point of view. This proves that after 5 articles some people did not get “yet” the message. They say that people like the stories, the explanations, the details, but I had a better chance to “invent” things as the world of VLSI automation was very “crude” and “primitive”. Today with all the automation going on, there is little to improve, improvise, innovate or invent. Most of what is needed is already here, so I should write about what should they invent next!!! If everybody will think this way we will stop growing, the gate size technology will stop “shrinking”, and the number of people in our industry will diminish.

To prove my point, I have to go back to history, my initial start in this profession. The year is 1984, the day is January 24, I was one of the 4 people selected to get trained in this “fancy” profession called IC Layout Designer. We were very excited recruits as the number of people with this profession was 6 in MSIL and in all Israel maybe 30 at that time. We were had a trainer from US to teach us Calma computer and software and for layout basics, flows and procedures our trainer was the Layout Manager, Miriam Zvuloni Gaziel. She had a challenging task: to get us from “know nothing” to people she can trust in 3 months. I can never forget the most shocking sentence she used at the end of the first training day:

As you will see, this is a very “fascinating” profession that you cannot learn anywhere else but in big companies like Intel, National, Motorola today. It will pay very well compare to other professions however, based on how the software automation is going, this profession has the potential to disappear in the next 5 years. This was in 1984.

I don’t want to invoke statistics but with all the automation the industry developed in in the last 30 years the number of IC Layout designers not only grew but exploded. Today there are many schools around the world teaching layout, Sankalp alone trained more than 1,000 new grads in the last 10 years. Universities are training Master and PhD student’s in layout so they can implement their projects in silicon. Only in India, that in 1983 probably had no VLSI development industry, there are more than 10,000 people doing VLSI today. We progressed from Calma mainframe to Linux machines, from 5 microns to 5 nano-meters. If somebody says that there is nothing else to invent because all is already there, they should move into the back seats and let the “inspired” and “creative” people take the driver and navigator seats. They will move forward, supporting new ideas, investing time and “Gray power” in new initiatives for automation and technology. Hopefully this clarification is understood and you can use my “historical stories” as stepping stones for your personal development without expecting others to tell you what to do.

A specific issue we had at MOSAID was that each project had to be developed in a totally new process so all tools setup had to be redone every time. We invented the Process Independent Setup (PIS) but people still needed to learn new design rules for each new project. In some cases, the rules changed while we were in the middle of the development. Luckily for us compaction engines showed up around 1996-1997. Rubicad from Germany and Sagantec originally from Holland, with later development moving to Israel. We did our homework by comparing the 2 company’s software features. I saw demos of both at DAC, some official some beyond that. I spoke with all the possible reference users they provided. The final decision was to invite Sagantec for an onsite demo.

We got a very strong AE to visit, Simon Klaver from Holland. The intention was that we can generate fast “dirty” cells and using compaction will get DRC clean results. We also wanted to see if we can use this technology to “migrate layout from process to process” a very new concept at that time. We gave Simon 2 cells for DREAM, the software name at that time, and ask him to clean all the design rules errors. We gave him 5 days with the hope that we can see some “good results” towards our target, but in 2 days he provided DRC and LVS clean cells. Case closed, we needed this tool, so we bought it. MOSAID bought the first DREAM license in North America at a good price with good maintenance service agreement.

After all, this was a huge risk for such a small company to buy a new “bleeding edge” technology from an unknown EDA vendor. We worked directly with the development team and their AEs so Malcolm MacIntosh, one of my team members became our expert. For the next 3 years I spoke with all new potential customers, being the reference customer for Sagantec. This helped their sales and me making new friends around the globe… The following 5 years I was close to Sagantec and help them develop the roadmap for new tools, at the same time being one of the first users for some. One year, after DAC, I went for dinner at the house of Hein van der Wildt, the CEO at that time. After dinner I started to talk with him and Coby Zelnik, a developer at that time, about what can we do next with DREAM. I wanted a tool that can run inside my layout editor, and we started to explore what is needed to make this happen. Like in all cool stories we actually wrote ideas on the napkins we used from the dinner, full of pasta sauce and red wine…

That night Companion, the idea of compaction inside Virtuoso was born.

From compaction flat we wanted hierarchical, from compaction we planned migration, so the life was exiting every time I met their team. I had, and still have, many “interesting” conversations on the roadmaps with Maarten Berkens, who was their CTO at that time, and now is in Sage software. SiClone, SiFix, Anaconda each had a lot of fun to be part of their initiation and development. Being so involved in Sagantec payed back many years later. While in PMC Sierra we needed a tool for DRC fixing so we looked at VLM from Cadence and SiFix from Sagantec. Coby Zelnik, now the CEO of Sagantec, came to Vancouver with Christen Decoin to show the tool and talk about the corporation new capabilities.

Unfortunately, he had to leave in the middle of the night having a family situation. Christen was a new AE with good technical knowledge of the tools but did not know how to answer all customers questions. He did the demo and I became the presenter of Sagantec corporate and technical presentation to PMC Mixed Signal Design & Layout. I had fun convincing PMC team that the tool I present (as Sagantec marketing) is the tool I want (as PMC Sierra Layout Manager) and it’s doing what we needed. The crowd had a lot of fun punishing me with questions, but I survived and we bought the tool.

More MOSAID “non-layout” initiatives next month…

Dan

Read the full blog series HERE.

February 5, 2018

AI-Leader Horizon Robotics Selects NetSpeed AI-based NoC IP For Next Generation Designs

AI-Leader Horizon Robotics Selects NetSpeed AI-based NoC IP For Next Generation Designs
by Mitch Heins on 02-05-2018 at 7:00 am
Categories: AI, Automotive, IoT, NetSpeed Systems
2 Comments

If you haven’t noticed, there has been a BIG influx of money into Artificial Intelligence (AI) technologies. Most recently, the Chinese government announced that AI is one of their top initiatives with a goal to catch up with the United States within 3 years and to be the world leader in AI by the year 2030. Horizon Robotics, founded in 2015, is one of China’s AI startups. It just closed a $100M A-round funding led by Intel Capital in October 2017 with the intent to build AI-based hardware and software targeted for use in autonomous vehicles, smart homes and smart cities. They plan to differentiate themselves by building low power, low cost intelligent processors that will enable devices to perceive, interact, understand and make decisions locally in the fog instead of having to transmit data to the cloud.

To accomplish their goal, Horizon’s team led by founder Kai Yu, former head of Baidu’s Institute of Deep Learning, has created a unique architecture they call their Brain Processing Unit (BPU). The architecture is open and allows for it to be targeted to multiple different compute platforms and end-markets applications. One of Horizon’s main goals is to be able to make any device an intelligent entity that can “think” locally without having to communicate to the cloud. That implies a lot of on-chip compute power, while also being cost effective enough to be sold in high volumes.

Because Horizon’s AI solutions are dealing with the real world, their chips have complex heterogeneous architectures that utilize multiple different processing engines, embedded memories and a variety of different sensor interfaces. Streaming data from sensors is fused into a homogeneous semantic environment upon which various hardware-accelerated AI-engines work to perceive objects, identify them and then predict their behavior. This implies an architecture that must deal with real-time cache coherency between different processors running at different speeds and workloads.

This clearly is not a one size fits all problem that can be tackled by one architecture. However, being a leader in AI is helping Horizon to attack the problem in a scalable way. Their understanding of AI’s benefits led them to license NetSpeed’s Orion and Gemini Interconnect IP for use in their AI chips. For those not familiar with NetSpeed, they use machine learning and AI techniques to help system architects synthesize System-on-Chip (SoC) interconnect fabrics known as networks-on-chip (NoCs). To be clear, Orion and Gemini NoCs are not static IP blocks, but instead are sophisticated interconnect fabrics that are synthesized by machine learning algorithms that analyze the anticipated workloads and traffic patterns between various processor engines, memories and external sensors interfaces.

While Orion and Gemini are incredible technology on their own, the thing that really makes them appealing to Horizon is the fact that the same NetSpeed IP can be easily scaled up or down to meet the needs of many different end-market applications using NetSpeed’s machine-learning Turing technology. And when Horizon says scaling they really mean scaling. They are ambitiously looking to put intelligence into as many as 1000 unique types of applications. You can imagine that the architecture for autonomous vehicles will be greatly different than an autonomous kitchen appliance. Yet both applications will use similar BPU building blocks from Horizon along with NetSpeed NoCs.

China by itself represents a huge AI market for Horizon. In the automotive market alone China now sells 30 million new cars each year. Advanced Driver Assisted Systems (ADAS) are well known for helping drivers park their cars or identifying objects in drivers’ blind spots. However, according to Yu from Horizon, ADAS used in Europe or the U.S. won’t cut it for China. ADAS in China must go to a whole new level as Yu says that in China the driving conditions are much more challenging. As examples, Yu says that in China drivers change lanes much more frequently than in most other countries and there are way more pedestrians everywhere, even on the highways!

Automobiles are just the tip of the iceberg however as China predicts it will need hundreds if not thousands of new AI applications to help it with city management, traffic, and a host of Internet-of-things (IoT) devices that will be running on 5G networks within its large populous cities. Here again Horizon plans to make those edge devices intelligent with their Brain technology.

In summary, there is a big push for AI at the edge of the cloud and it appears that NetSpeed’s NoCs are well positioned to leverage this upcoming market. As Horizon Robotics has figured out, the ability to integrate heterogeneous architectures with smart interconnect fabrics is an enabling technology for next generation AI systems.

About Horizon Robotics
Horizon Robotics aims for becoming the global leader of embedded AI. By jointly optimizing algorithm and processor design, Horizon Robotics is delivering software and hardware integrated solutions with high performance and low power to equip devices, such as autonomous vehicles and smart cameras, to make human life more safe, convenient and fun. The company has a strong R&D team with rich industrial experience support the development of the smart world. Horizon Robotics has received funding from venture investors including Morningside Venture Capital, Hillhouse Capital, Sequoia Capital, GSR Ventures, Linear Venture, Innovation Works, ZhenFund, Wu Capital, Tsing Capital and Vertex Ventures, as well as from Yuri Milner, a legendary venture capitalist from Silicon Valley. http://en.horizon.ai/

About NetSpeed Systems
NetSpeed Systems provides scalable, coherent on-chip network IPs to SoC designers for a wide range of markets from mobile to high-performance computing and networking. NetSpeed’s on-chip network platform delivers significant time-to-market advantages through a system-level approach, a high level of user-driven automation and state-of-the-art algorithms. NetSpeed Systems was founded in 2011 and is led by seasoned executives from the semiconductor and networking industries. The company is funded by top-tier investors from Silicon Valley. It is based in San Jose, California and has additional research and development facilities in Asia. For more information, visit www.netspeedsystems.com.

February 4, 2018

DSP SoC a la Française

DSP SoC a la Française
by Lauro Rizzatti on 02-04-2018 at 11:00 am
Categories: IP
1 Comment

I enjoyed reading Eric Esteve’s article “ French Tech at CES, 2nd country after USA with 274 Start-Up at Eureka Park!” It brought back happy memories of my time at EVE until Synopsys purchased it in 2012.Here is another intriguing story by a French startup named VSORA and founded by Khaled Maalej with a team of scientists and engineers. Not new to the French high-tech landscape, Khaled and team already reached success in a previous enterprise named DiBcom when it was acquired by Parrot, a dronecompany, in 2011. DiBcom was the leading providing of integrated circuits for mobile digital TV receivers incorporated into cell-phones, cars and PCs.

This time the team came up with a rather interesting idea.Digital Signal Processors (DSP) have been around for about four decades and by now they are ubiquitous in the semiconductor industry, used for image and audio processing, in communication and mobile applications, lately in automotive designs, essentially everywhere there is a need to elaborate digital signals. Today DSP designs are by far more complex and advanced than the pioneering implementations introduced by TI, AMD, NEC, and others in the late 1970’s. Still, all current offerings meet the need for ever growing processing power via one or more DSP co-processors: the higher the processing power requirement, the more th eco-processors. All well and good, but co-processors are essentially hard-wired algorithms. Any change to an algorithm, no matter how small, forces the DSP engineers to re-spin the hardware. A costly proposition with a very lengthy design-iteration-time (DIT) in the ballpark of one month or longer.

Based on their previous experience at DiBcom, the team conceiveda DSP architecture that eliminates the co-processors. Instead, they devised a flexible fabric built on a matrix of multiple DSP cores they call Multi-Core Signal Processors (MSP). Each core can be configured and optimized to perform a specific task. You can size the memory assigned to each core, tune the processing power, that is, select the number of arithmetic-logic-units (ALU),or adjust the floating point accuracy. For example, a DSP performing MiMo combinations requires different computation accuracy and rather higher processing power than one performing signal synchronization.

But this is not all there is to it. Vsora went a step,actually two steps further.

In an SoC design that includes an embedded DSP, for example a base station for a wireless application, the traditional development process involves four different design teams. First, the signal processing team, comprised of highly specialized engineers, defines an algorithm at high level of abstraction, commonly using Matlab-like coding. Once pleased with the results,they pass their creation on to the DSP design team to implement it either on the DSP or, when not feasible, in one or more co-processors. The two teams come from different backgrounds, possess different skills, use different development tools and methods, and habitually mis-communicate blaming each other. The scenario leads to multiple iterations between them until they agree on a result. The real problem is, each iteration may take weeks.

Once the DSP design is satisfactory, it is dispatched to the SOC hardware team that incorporates it into the SoC, and to the embedded software team that develops the supporting software stack.

Vsora envisioned a development environment that unifies the two DSP teams into the algorithmic team, giving them the tools to fine tune the algorithms until ready to be deployed in the SoC. They can perform “what-if”analysis, try different configurations, size each core for performance, power, orarea, generate multiple version of the DSP and compare them without implementing the actual hardware. Once pleased with the results, they forward the MSP to the SOC hardware and software development teams. The approach eliminates the detrimental iterations and accelerates the development schedule by few months.

As a cheery-on-the-cake, the team is also setting up the VSORA MSP development environment on the Amazon Web Services FPGA (AWS-F1) cloud. Engineers will be able to access the VSORA development environment and fine tune their algorithms while mapping it directly to the DSP. They will be able to reduce the simulation time of the implemented DSP by factor of 10s compared to simulation of the algorithmic model running on a PC, and eliminate the risk that abstract and implemented models may differ. Signal processing engineers will be able to define and implement their algorithms and verify them on a “prototyping-like”platform within minutes. This leads to better system/cost optimization at the early stage of the project and avoid significant upfront investments to setup a traditional development environment.

The upcoming 5G standard, heavily reliant on DSP technology, is posing new and steep challenges to the engineering community,stressing the traditional DSP development flow. The adoption of millimeter waves, MIMO, and other advanced technologies requires lots of processing power,creating a golden opportunity for the VSORA approach.

Recently VSORA closed their first round of funding from Omnes Capital, Partech Ventures, and few Angel Investors.Definitely, there must be something unique in the DNA of the French engineering community.

February 4, 2018

The future of education is virtual

The future of education is virtual
by Vivek Wadhwa on 02-04-2018 at 7:00 am
Categories: AI
2 Comments

Massive open online courses (MOOCs) were supposed to bring a revolution in education. But they haven’t lived up to expectations. We have been putting educators in front of cameras and shooting video — just as the first TV shows did with radio stars, microphone in hand. This is not to say the millions of hours of online content are not valuable; the limits lie in the ability of the underlying technology to customize the material to the individual and to coach.

That is about to change, though, through the use of virtual reality, artificial intelligence and sensors. Let me illustrate this with an imaginary school of the future in which Clifford is an artificial intelligence, a digital tutor, and Rachael is the human educational coach.

Clifford has been with the children for years and understands their strengths and weaknesses. He customizes each class for them. To a child who likes reading books, he teaches mathematics and science in a traditional way, on their tablets. If they struggle with this because they are more visual learners, he asks them to put on their virtual-reality headsets for an excursion, say, to ancient Egypt.

Watching the design and construction of the pyramids, children learn the geometry of different types of triangles and the mathematics behind these massive timeless monuments. They also gain an understanding of Egyptian history and culture by following the minds of the geniuses who planned and constructed them.

Clifford also teaches art, music and biology through holographic simulations.

By using advanced sensors to observe the children’s pupillary size, their eye movements and subtle changes in the tone of their voice, Clifford registers their emotional state and level of understanding of the subject matter. There is no time pressure to complete a lesson, and there are no grades or exams. Yet Clifford can tell the parents how the child is doing whenever they want to know and can advise the human, Rachael, on what to teach.

Rachael does not lecture or scrawl facts or equations on a blackboard. She is there to listen and help. She asks questions to help develop the children’s values and thinking and teaches them how to work with one other. She has the responsibility of ensuring that students learn what they need to, and she guides them in ways Clifford cannot. She also helps with the physical side of projects, things made out of real materials rather than in mind and machine.

With Clifford as teacher and Rachel as coach, children do not even realize that what they are undertaking is study. It feels like building cool stuff, playing video games, and living through history. Clifford, being software and having come into being in the same way that the free applications on our smartphones have, comes without financial charge. Rachael’s coaching is part of our public education package, funded in the same way today’s teachers are.

We already have wonderful teachers who are supportive and can teach teamwork and values. Believe it or not, we have the ability to build Clifford today. The artificial intelligence tools and sensors to observe human emotion are commonly available via smartphones and digital assistants, and the virtual-reality headsets will soon be powerful enough and affordable enough for holographic learning.

Take Facebook’s Oculus Rift virtual reality headset. When Facebook released Oculus Rift in March 2016, it cost $599 and required a $199 controller and a $1,000 gaming PC. The headset and controller now cost $399 together and do the work of the gaming PC. Facebook says a new version, Oculus Go, will ship later this year and cost $199. At the recent Consumer Electronics Show in Las Vegas, HTC announced Vive Pro, a headset with much higher resolution and better features than Oculus Rift; and its price will surely be lower, because dozens of other companies, including Google, Lenovo and Magic Leap, are in also the race.

We can expect that within two or three years, VR headsets will cost less than $100 and have built-in artificial intelligence chips, enabling billions of people to benefit from the education revolution finally at hand.

For more, you can read my book, Driver in the Driverless Car. It details the advances that are making this amazing–and scary–future possible.

February 2, 2018July 3, 2021

Cloud Provider Leverages FPGA Prototyping

Cloud Provider Leverages FPGA Prototyping
by Daniel Nenni on 02-02-2018 at 7:00 am
Categories: Prototyping, S2C EDA

Talking to customers is one of the best parts of being a semiconductor professional. It keeps you grounded and offers you the collective experience of some of the smartest people around the world, absolutely.

Webinar: The Emergence of FPGA Prototyping for ASIC/SoC Design

Customer success stories are a close second and interestingly much harder to come by than a face to face meeting. The semiconductor industry is very competitive (secretive) so when you do get a customer willing to speak up it is definitely worth your time. This success story is from my favorite FPGA Prototyping provider S2C:

Inspur is a leading cloud provider in China offering high-end servers, mass storage, cloud operating system, and information security technology. As a chip and systems developer Inspur was faced with the challenges of establishing an executable platform for hardware validation and integration, building a high bandwidth transmission channel to transfer mass packet to DUT for verification, and supporting fast and stable system startup then quickly and accurately locating problems.

Inspur’s routing control design consumed 96% BRAM of VU440 FPGA which allowed no extra memory resources for ChipScope debugging. The S2C delivered MDM does not consume design FPGA memories which perfectly solved this debugging issue.

The complexity of Inspur’s SoC increased both cost and schedule risks due to the need to verify real-world scenarios. Generally no one knows when a bug will hit or when it actually occurs, especially if there isn’t enough sampling depth to analyze. MDM mitigated those challenges as a cost-effective solution. After the initial 1~2 MDM and Single VU systems bring up, Inspur used 10 sets of systems running 24 hours a day without interruption. This enabled Inspur to detect and fix many bugs in the real network testing environment which cut six months off their development schedule.

Inspur used the Single VU440 Prodigy Logic Module for prototyping verification on a routing control chip and selected the MDM to run the deep trace debugging which allows Inspur to grab as many packets as possible to then be analyzed for correctness.

“The performance capabilities of the Prodigy Logic Module, deep trace debugging of MDM software, professional daughter card customization services, and fast support helped us efficiently verify our SoC designs. This allowed us to focus on the innovation and validation of the SoC.” Said Huang Jiaming, General Manager of High-end Server Department at Inspur.

“The biggest advantage S2C MDM gives us is the ability to detect bugs deeply embedded in the design that can be detected only by processing the real word packets. This significantly speeds up the debug process and gets our design to the market quickly with greater confidence.”

Overview

S2C’s single VU440 Prodigy Logic Module providing multi-million ASIC gate capacity
The Prodigy Multi-Debug Module (MDM) enables greater sampling depth which makes debugging easier
The customized QSFP Interface Module is well designed and higher performance
The quick response of S2C’s support team helped Inspur to bring up the FPGA validation environment successfully

With S2C’s rapid SoC prototyping solutions Inspur saved about six months in developing and debugging their SoC design. Features like scalability, reuse, flexibility, and deep trace debugging let Inspur quickly port the design into FPGA prototyping, transfer mass packet to the DUT, and speed up the debugging progress.

S2C Solution

S2C’s Single VU440 Prodigy Logic Module providing multi-million ASIC gate capacity allows Inspur to quickly port their routing control chip for verification
Customized two QSFP cage interface modules to provide the high-speed transmission channel for the DUT
Specialized Prodigy Multi-Debug Module hardware enables deep trace debugging with the ability to store up to 16GB of waveforms
Prodigy Player Pro is used to setup trigger conditions and capture related packets for chip-level debugging

Figure 1: Inspur routing controller validation platform using S2C Single VU440 + MDM

About S2C
Founded and headquartered in San Jose, California, S2C has been successfully delivering rapid SoC prototyping solutions since 2003. S2C provides:

Rapid FPGA-based prototyping hardware and automation software
Prototype Ready™ IP, interfaces and platforms
System-level design verification and acceleration tools

With over 200 customers and more than 800 systems installed, S2C’s focus is on SoC/ASIC development to reduce the SoC design cycle. Our highly qualified engineering team and customer-centric sales force understand our users’ SoC development needs. S2C systems have been deployed by leaders in consumer electronics, communications, computing, image processing, data storage, research, defense, education, automotive, medical, design services, and silicon IP. S2C is headquartered in San Jose, CA with offices and distributors around the globe including the UK, Israel, China, Taiwan, Korea, and Japan. For more information, visit www.s2cinc.com.