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Compute at the Edge

Compute at the Edge
by Bernard Murphy on 05-01-2019 at 7:00 am
Categories: AI, Ceva, IoT, IP, Mobile, Security

At first glance, this seems like a ho-hum topic- just use whatever Arm or RISC-V solution you need – but think again. We’re now expecting to push an awful lot of functionality into these edge devices. Our imaginations don’t care about power, performance and cost; everything should be possible so let’s keep adding cool features. Of course reality has to intrude at some point; edge nodes often aren’t plugged into a wall socket or even into a mobile-phone-class battery. Power and recharge constraints (as well as cost) don’t necessarily mean our imagined products are unattainable but they do require more careful thought in how they might be architected.

Start first with what we might want to build. Cameras must continue to at least keep pace with your cellphone camera so have added remote control and voice-activation. VR and AR headsets need to recognize your head and body position to correctly orient a game scene or position AR overlays in real-world scenes. Headphones are becoming increasingly smart in multiple ways, recognizing you through the unique structure of your ear canal, recognizing voice commands to change a playlist or make a call, detecting a fall or monitoring heart rate and other vital signs. Home security systems must recognize anomalous noises (such as breaking glass) or anomalous figures/movement detected on cameras around the house.

Each of these capabilities demands multiple compute resources. First and most obviously, you need communication; none of these wonderful products will be useful standalone. In some cases, communication may be through relatively short-range protocols such as Bluetooth or Wi-Fi, in other cases you may need cellular support, through NB-IoT for small packet transfers (such as from a parking meter) or through LTE or 5G for broadband support (drones or 4k/8k video streaming for example). Whichever protocol you choose, you need a modem, and for cellular it probably needs to support MIMO with beam-forming to ensure reasonably connectivity.

Modems are specialized beasts, usually best left to the experts. You could buy a standalone chip, but then your product needs at least 2 chips (one for everything else). That makes it more expensive and more of a power hog, definitely not extending to a 10-year battery life, maybe not even 10 hours. The best choice for PPA is an integrated modem with tight power management, especially for the power-amp.

Now think about compute for sensing, where a good example is a 9-axis sensor, fusing raw data from a 3-axis accelerometer, 3-axis geomagnetic sensor and 3-axis gyroscope, such as you might use in a VR/AR headset. Together these sensors can provide information on orientation and movement with respect to a fixed Earth frame, which is just what you need for a realistic virtual gaming experience or orienting virtual support information and controls against a real machine you want to manage.

This fusion requires yet more compute, heavily trigonometric along with filtering, which could be accomplished in a variety of ways but needs to be more or less always-on during use. You could make some allowance for human response times, perhaps allowing for update every 1/60[SUP]th[/SUP] of a second, but that’s still pretty continuous demand. Again you could get this through an integrated chip solution, but for all the PPA reasons mentioned earlier an ideal solution would be embedded in your one-chip SoC. And since the fusion algorithms are math-intensive, a DSP is a pretty natural fit.

One more example – AI embedded in your product. AI is ramping fast in edge-based devices in a lot of use-cases; here let’s consider just voice-control. This needs multiple components – audio beamforming, noise management and echo-cancellation, and trigger-word recognition at minimum. Beamforming, echo cancellation (especially indoors) and noise filtering are all DSP functions. Perhaps you could prove these are possible on some other platform but you’d never compete with DSP-based products. Trigger-word recognition gets into neural nets (NN), the heart of AI. And in many cases it needs to be combined with voice recognition – recognizing who is speaking rather than what is being said. Again, DSPs are a well-recognized low-power, high-performance option in the NN implementation spectrum, above CPUs, FPGAs and GPUs (and below full-custom solutions like the Google TPU).

GPUs are very well known in the AI domain, but primarily in NN training and in prototypes or cost/power-insensitive applications. Mobile VR headsets you may have seen are likely to be based (today) on these platforms but they’re expensive (~$1k for the chip alone) and deliver short battery lives (I haven’t heard the latest on the Magic Leap, but I do know you need to wear a battery on your belt and they have been cagey about time between charges – maybe a few hours at most).

Finally, full operation of your ground-breaking product requires some level of remote functionality but you probably don’t want to depend on it being up all the time. And probably you would prefer that sensitive information (health data, credit cards, face-id, etc) not travel over possibly insecure links to possibly hackable cloud-based platforms. You don’t want your semi-autonomous drone crashing into a tree because it lost line of sight with a base station or flying off to someone else who figured out how to override your radio control. That means you need more intelligence and more autonomy in the device, for collision avoidance, for path finding and for target object detection, without having to turn to the cloud. Which means need for more AI at the edge.

All of the functions I have talked about here are supported on DSP platforms and some can potentially be multiplexed on a single DSP. You probably still want a CPU or MCU as well, for administration, authorization, provisioning and whatever other algorithms you need to support. Not so much for the AI; you can get basic capabilities on CPUs/MCUs but they tend to be quite limited compared with what you can find on DSP platforms. If you want to learn more about what is possible in communication, sensor fusion and AI at the edge, check out CEVA.

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TSMC Technology Symposium Review Part II

TSMC Technology Symposium Review Part II
by Tom Dillinger on 04-30-2019 at 10:00 am
Categories: Events, Foundries, TSMC
6 Comments

TSMC recently held their annual Technology Symposium in Santa Clara. Part 1 of this article focused on the semiconductor process highlights. This part reviews the advanced packaging technologies presented at the symposium.

TSMC has clearly made a transition from a “pure” wafer-level foundry to a supplier of complex integrated system modules – or according to C.C. Wei, CEO, TSMC is a leading source for “nano-mass production innovations”. (Taiwan News, 4/23/19) This is the outcome of years of R&D investment – for example, see the discussion on 3D stacking in the “SoIC” section below.

Dr. Doug Yu, VP, Integrated Interconnect and Package R&D provided a detailed update. Dr. Yu classified the package technologies into unique categories – “front-end” 3D chip integration (SoIC) and “back-end” packaging advances (CoWoS, InFO). Additionally, he addressed the progress in pad pitch and Cu pillar/SnAg bump lithography, specifically mentioning the automotive grade reliability requirements.

Here’s a brief recap of the TSMC advanced packaging technology status.

Bumping
TSMC continues to advance bump technology, with 60-80um bump pitch achievable (for smaller die).

CoWoS
The initial TSMC 2.5D packaging offering was chip-on-wafer-on-substrate (CoWoS), which has enabled very high-performance system integration by bringing memory “closer to the processor”.

  • >50 customer products
  • TSMC is developing “standardized” configurations – e.g., 1 SoC with 2 or 4 HBMs, evolving to >2 SoCs with 8 HBM2Es (96GB @ 2.5TB/sec – wow.)

Correspondingly, TSMC will be expanding the maximum 2.5D interposer footprint from a max of 1X reticle (~50×50) to 3X (~85×85), with a 150um bump pitch.

  • The silicon interposer supports 5 metal layers and a (new) deep trench capacitor – see the figure below.

InFO
TSMC continues to evolve the Integrated FanOut (InFO) package offerings. Recall that InFO is a means of integrating (multiple) die using a “reconstituted wafer” molding compound to provide the package substrate for RDL patterning. InFO builds upon the traditional small-package WLCSP technology to enable (large area) redistribution interconnect and high bump count – see the figure below.

InFO-PoP supports stacking of a logic die and a DRAM die on top of the base, using through-InFO-vias (TIV) to connect the DRAM to the metal layers. InFO-PoP development has focused on improving the pitch and aspect ratio (vertical-to-diameter) of the TIVs.

InFO-on-Substrate offerings attach a (multi-die) InFO module to a (large area) substrate, leveraging the multiple reticle stitching technology developed for CoWoS.

SoIC (“front-end” 3D integration)
The big packaging announcement at the symposium was the introduction of the “front-end” 3D die stacking topology, denoted as SoIC (System-on-Integrated Chips).

SoIC is a “bumpless” interconnect method between multiple die. As depicted in the figure below (from an early R&D paper from TSMC), Cu pads from a base die and exposed Cu “nails” from the (thinned) top die utilize thermo-compression bonding to provide the electrical connection. (An appropriate underfill material is present at the die-to-die interface, as well.)

  • Through-silicon vias in the die provide connectivity, with a very tight pitch.
  • Both face-to-face and face-to-back die connectivity are supported. The “known good” stacked die may be different sizes, with multiple die on a stacked layer.
  • TSMC showed a mock-up of a 3-high vertical SoIC stack.
  • EDA enablement is available: physical design (DRC, netlisting/LVS), parasitic extraction, timing, IR/EM analysis, signal integrity/power integrity analysis, thermal/materials stress analysis.
  • The qualification target for the SoIC package offering is YE’2019. (My understanding from a separate TSMC announcement is SoIC volume availability will be in 2021.)

Dr. Yu also indicated, “The front-end SoIC module will be able to be integrated as part of a back-end 2.5D offering, as well.”

Summary
Both 2.5D and InFO “back-end” package offerings continue to evolve.

Yet, for me the highlight was the introduction of the tight-pitch, Cu compression-bonded full-3D stacked die of the SoIC topology. The available circuit density (per mm**3) will be very appealing. The challenges to leverage this technology will be considerable, though, from system architecture partitioning to complex electrical/thermal/mechanical analysis across the stacked die interfaces.

Moore’s Law is definitely alive-and-well, although it will require 3D glasses. 😀

-chipguy

Also read: 2019 TSMC Technology Symposium Review Part I

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2019 TSMC Technology Symposium Review Part I

2019 TSMC Technology Symposium Review Part I
by Tom Dillinger on 04-30-2019 at 7:00 am
Categories: Events, Foundries, TSMC
5 Comments

Each year, TSMC conducts two major customer events worldwide – the TSMC Technology Symposium in the Spring and the TSMC Open Innovation Platform Ecosystem Forum in the Fall. The Technology Symposium event was recently held in Santa Clara, CA, providing an extensive update on the status of advanced semiconductor and packaging technology development. This article briefly reviews the highlights of the semiconductor process presentations – a subsequent article will review the advanced packaging announcements.

First, some general items that might be of interest:

Longevity
TSMC was founded in 1987, and has been holding annual Technology Symposium events since 1994 – this was the 25th anniversary (which was highlighted prevalently throughout the Santa Clara Convention Center). “The first Silicon Valley symposium had less than 100 attendees – now, the attendance exceeds 2000.”, according to Dave Keller, President and CEO of TSMC North America.

Best Quote of the Day
Dr. Cheng-Ming Lin, Director, Automotive Business Development, describes the unique requirements of TSMC’s automotive customers, specifically with regards to continuity of supply over a much longer product lifetime. He indicated,

“Our commitment to legacy processes is unwavering. We have never closed a fab or shut down a process technology.” (Wow.)

Best Quip of the Day
Dr. Y.-J. Mii, Senior Vice President of Research and Development / Technology Development , highlighted three eras of process technology development, as depicted in the figure below from his presentation.

In the first phase, Dennard scaling refers to the goal of scaling FEOL linear lithographic dimensions by a factor of “s” (s < 1) in successive process nodes, achieving an improvement of (1 / s**2) in circuit density, measured as gates / mm**2. The next phase focused on material improvements, and the current phase centers on design-technology co-optimization – more on that shortly.

In a subsequent presentation at the symposium, Dr. Doug Yu, VP, Integrated Interconnect and Packaging R&D, described how advanced packaging technology has also been focused on scaling, albeit for a shorter duration. “For over 10 years, packages have also offered two-dimensional improvements to redistribution layer (RDL) and bump pitch lithography. With the multi-die, 3D vertical stacking package technology we’re describing today – specifically, TSMC’s SoIC offering – we are providing vast improvements in circuit density. S is equal to zero. Or, in other words, infinite scaling.” 😀 (Indeed, it is easy to foresee product technologies starting to use the metric “gates / mm**3” .)

Here is a brief recap of the TSMC advanced process technology status.

N7/N7+
TSMC announced the N7 and N7+ process nodes at the symposium two years ago. (link)

N7 is the “baseline” FinFET process, whereas N7+ offers improved circuit density with the introduction of EUV lithography for selected FEOL layers. The transition of design IP from N7 to N7+ necessitates re-implementation, to achieve a 1.2X logic gate density improvement. Key highlights include:

 

  • N7 is in production, with over 100 new tapeouts (NTOs) expected in 2019
  • Key IP introduction: 112Gbps PAM4 SerDes
  • N7+ is benefitting from improvements in sustained EUV output power (~280W) and uptime (~85%). “Although we anticipate further improvements in power and uptime, these measures are sufficient to proceed to N7+ volume ramp.”, TSMC said.
  • TSMC has focused on defect density (D0) reduction for N7. “The D0 improvement ramp has been faster than previous nodes, at a comparable interval after initial production volume ramp.”, according to TSMC.
  • TSMC illustrated a dichotomy in N7 die sizes – mobile customers at <100 mm**2, and HPC customers at >300 mm**2.
  • To my recollection, for the first time TSMC also indicated they are tracking D0 specifically for “large chips”, and reported a comparable reduction learning for large designs as for other N7 products.
  • N7+ will enter volume ramp in 2H2019, and is demonstrating comparable D0 defect rates as N7.

“Making 5G a Reality”
TSMC invited Jim Thompson, CTO, Qualcomm, to provide his perspective on N7 – a very enlightening presentation:

  • “N7 is the enabler for the 5G launch, as demonstrated in our latest Snapdragon 855 release.”
  • “5G MIMO with 256 antenna elements supports 64 simultaneous digital streams – that’s 16 users each receiving 4 data streams to a single phone.”
  • “Antenna design is indeed extremely crucial for 5G, to overcome path loss and signal blockage. There are new, innovative antenna implementations being pursued – in the end, it’s just math, although complex math for sure.”
  • “There’s certainly lots of skepticism about the adoption rate of 5G. Yet 5G is moving much faster than 4G did – at a comparable point in the rollout schedule, there were only 5 operators and 3 OEM devices supporting 4G, mostly in the US and South Korea. Currently, there are over 20 operators and over 20 OEM devices focused on 5G deployment, including Europe, China, Japan, and Southeast Asia.”
  • “And, don’t overlook the deployment of 5G in applications other than consumer phones, such as ‘wireless factory automation’. Communication to/from industrial robots requires high bandwidth, low latency, and extremely high availability. Consider the opportunities for manufacturing flexibility in a wire-free environment, enabled by 5G.”

N6
TSMC introduced a new node offering, denoted as N6. This node has some very unique characteristics:

  • design rule compatible with N7 (e.g., 57mm M1 pitch, same as N7)
  • IP models compatible with N7
  • incorporates EUV lithography for limited FEOL layers – “1 more EUV layer than N7+, leveraging the learning from both N7+ and N5”
  • tighter process control, faster cycle time than N7
  • same EDA reference flows, fill algorithms, etc. as N7
  • N7 designs could simply “re-tapeout” (RTO) to N6 for improved yield with EUV mask lithography
  • or, N7 designs could submit a new tapeout (NTO) by re-implementing logic blocks using an N6 standard cell library (H240) that leverages a “common PODE” (CPODE) device between cells for an ~18% improvement in logic block density
  • risk production in 1Q’20 (a 13 level metal interconnect stack was illustrated)
  • although design rule compatible with N7, N6 also introduces a very unique feature – “M0 routing”

The figure below illustrates a “typical” FinFET device layout, with M0 solely used as a local interconnect, to connect the source or drain nodes of a multi-fin device and used within the cell to connect common nFET and pFET schematic nodes.


I need to ponder a bit more on the opportunity use M0 as a routing layer – TSMC indicated that EDA router support for this feature is still being qualified.

N6 strikes me as a continuation of TSMC’s introduction of a “half node” process roadmap, as depicted below.


A half-node process is both an engineering-driven and business-driven decision to provide a low-risk design migration path, to offer a cost-reduced option to an existing N7 design as a “mid-life kicker”.

The introduction of N6 also highlights an issue that will become increasingly problematic. The migration of a design integrating external IP is dependent upon the engineering and financial resources of the IP provider to develop, release (on a testsite shuttle), characterize, and qualify the IP on a new node on a suitable schedule. N6 offers an opportunity to introduce a kicker without that external IP release constraint.

N5
The process node N5 incorporates additional EUV lithography, to reduce the mask count for layers that would otherwise require extensive multipatterning.

 

  • risk production started in March’19, high volume ramp in 2Q’20 at the recently completed Gigafab 18 in Tainan (phase 1 equipment installation completed in March’19)
  • intended to support both mobile and high-performance computing “platform” customers; high-performance applications will want to utilize a new “extra low Vt”(ELVT) device
  • 1.5V or 1.2V I/O device support
  • an N5P (“plus”) offering is planned, with a +7% performance boost at constant power, or ~15% power reduction at constant perf over N5 (one year after N5)
  • N5 will utilize a high-mobility (Ge) device channel

Advanced Materials Engineering
In addition to the N5 introduction of a high mobility channel, TSMC highlighted additional materials and device engineering updates:

  • super high-density MIM offering (N5), with 2X ff/um**2 and 2X insertion density
  • new low-K dielectric materials
  • metal Reactive Ion Etching (RIE), replacing Cu damascene for metal pitch < 30um
  • a graphene “cap” to reduce Cu interconnect resistivity

An improved local MIM capacitance will help to address the increased current from the higher gate density. TSMC indicated an expected single-digit % performance increase could be realized for high-performance (high switching activity) designs.

Nodes 16FFC and 12FFC both received device engineering improvements:

  • 16FFC+ : +10% perf @ constant power, +20% power @ constant perf over 16FFC
  • 12FFC+ : +7% perf @ constant power, +15% power @ constant perf over 12FFC

NTO’s for these nodes will be accepted in 3Q’19.

TSMC also briefly highlighted ongoing R&D activities in materials research for future nodes – e.g., Ge nanowire/nanoslab device channels, 2D semiconductor materials (ZrSe2, MoSe2) – see the figure below (Source: TSMC).

Manufacturing Excellence
Dr. J.K. Wang, SVP, Fab Operations, provided a detailed discussion of the ongoing efforts to reduce DPPM and sustain “manufacturing excellence”. Of specific note were the steps taken to address the demanding reliability requirements of automotive customers. Highlights of Dr. Wang’s presentation included:

“Since the introduction of the N16 node, we have accelerated the manufacturing capacity ramp for each node in the first 6 months at an ever-increasing rate. The N7 capacity in 2019 will exceed 1M 12” wafers per year. The N10/N7 capacity ramp has tripled since 2017, as phases 5 through 7 of Gigafab 15 have come online.”

“We have implemented aggressive statistical process control (measured on control wafer sites) for early detection, stop, and fix of process variations – e.g., upward/downward shifts in baseline measures, a variance shift, mismatch among tools. We have established 2D wafer profile measurement criteria, and in-line monitoring and comparison to an “acceptance” profile across each wafer.”

“The DDM reduction rate on N7 has been the fastest of any node.”

“For automotive customers, we have implemented unique measures to achieve the demanding DPPM requirements. We will ink out good die in a bad zone. And, there are SPC criteria for a maverick lot, which will be scrapped.”

“We will support product-specific upper spec limit and lower spec limit criteria. We will either scrap an out-of-spec limit wafer, or hold the entire lot for the customer’s risk assessment.” (See the figures below. Source: TSMC)



Automotive Platform
TSMC has developed an approach toward process development and design enablement features focused on four platforms – mobile, HPC, IoT, and automotive. Dr. Cheng-Ming Lin, Director, Automotive Business Unit, provided an update on the platform, and the unique characteristics of automotive customers.

Growth in semi content
Dr. Lin indicated, “Automotive systems will require both advanced logic technologies for ADAS, such as N16FFC, and advanced RF technologies for V2X communications. Although the CAGR for cars from now to 2022 is expected to be only ~1.8%, the CAGR for the semiconductor content will be 6.9%.”

He continued, “The L1/L2 feature adoption will reach ~30%, with additional MCU’s applied to safety, connectivity, and EV/hybrid EV features. There will be ~30-40 MCU’s per vehicle. “ (In his charts, the forecast for L3/L4/L5 adoption is ~0.3% in 2020, and 2.5% in 2025.)

“The adoption rate for the digital dashboard cockpit visualization system will also increase, driving further semiconductor growth – 0.2% in 2018 to 11% in 2025.”

L2+
The levels of support for automated driver assistance and ultimately autonomous driving have been defined by SAE International as “Level 1 through Level 5”. Perhaps in recognition of the difficulties in achieving L3 through L5, a new “L2+” level has been proposed (albeit outside of SAE), with additional camera and decision support features.

“An L2+ car would typically integrate 6 cameras, 4 short-range radar systems, and 1 long-range radar unit, requiring in excess of 50GFLOPS graphics processing and >10K DMIPS navigational processing throughput.”

N16FFC, and then N7
The 16FFC platform has been qualified for automotive environment applications – e.g., SPICE and aging models, foundation IP characterization, non-volatile memory, interface IP. The N7 platform will be (AEC-Q100 and ASIL-B) qualified in 2020. “Automotive customers tend to lag consumer adoption by ~2-3 years, to leverage DPPM learning – although that interval is diminishing. We anticipate aggressive N7 automotive adoption in 2021.”,Dr. Lin indicated.

“The TSMC RF CMOS offerings will be used for SRR, LRR, and Lidar. The 16FFC-RF-Enhanced process will be qualified for automotive platforms in 2Q’20.”

IoT Platform
The TSMC IoT platform is laser-focused on low-cost, low (active) power dissipation, and low leakage (standby) power dissipation. Dr. Simon Wang, Director, IoT Business Development, provided the following update:

Process Roadmap

  • 55ULP, 40ULP (w/RRAM): 0.75V/0.7V
  • 22ULP, 22ULL: 0.6V
  • 12FFC+_ULL: 0.5V (target)
  • introduction of new devices for the 22ULL node: EHVT device, ultra-low leakage SRAM

The 22ULL SRAM is a “dual VDD rail” design, with separate logic (0.6V, SVT + HVT) and bitcell VDD_min (0.8V) values for optimum standby power.

The 22ULL node also get an MRAM option for non-volatile memory.

Note that a new methodology will be applied for static timing analysis for low VDD design. The stage-based OCV (derating multiplier) cell delay calculation will transition to sign-off using the Liberty Variation Format (LVF).

The next generation IoT node will be 12FFC+_ULL, with risk production in 2Q’20. (with low VDD standard cells at SVT, 0.5V VDD).

RF
TSMC emphasized the process development focus for RF technologies, as part of the growth in both 5G and automotive applications. Dr. Jay Sun, Director, RF and Analog Business Development provided the following highlights:

  • For RF system transceivers, 22ULP/ULL-RF is the mainstream node. For higher-end applications, 16FFC-RF is appropriate, followed by N7-RF in 2H’20.
  • Significant device R&D is being made to enhance the device ft and fmax for these nodes – look for 16FFC-RF-Enhanced in 2020 (fmax > 380GHz) and N7-RF-Enhanced in 2021.
  • New top-level BEOL stack options are available with ‘elevated’ ultra thick metal for inductors with improved Q.
  • For sub-6GHz RF front-end design, TSMC is introducing N40SOI in 2019 – the transition from 0.18um SOI to 0.13um SOI to N40SOI will offer devices with vastly improved ft and fmax.

Summary
There was a conjecture/joke going around a couple of years ago, suggesting that “only 7 customers will be able to afford to pursue 7nm designs, and only 5 customers at 5nm”.

Clearly, the momentum behind N7/N6 and N5 across mobile communication, HPC, and automotive (L1-L5) applications dispels that idea. TSMC is investing significantly in enabling these nodes through DTCO, leveraging significant progress in EUV lithography and the introduction of new materials.

Part 2 of this article will review the advanced packaging technologies presented at the TSMC Technology Symposium.

-chipguy

Also read: TSMC Technology Symposium Review Part II

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Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
by Tom Simon on 04-29-2019 at 4:00 pm
Categories: EDA, Events, MunEDA

The letters “PVT” roll of the tongue easily enough, belying the complexity that variations in process, temperature and voltage can cause for analog designs. For semiconductor processes, there are dozens of parameters that can affect the viability of a design. It would be easy enough to optimize a circuit with only one or two varying parameters. However, the high number of varying parameters operating on each device in a design creates a huge multidimensional problem.

The baseline approach is to use Monte Carlo, randomly selecting process variables based on the distribution function for each. This brute force approach can require enormous amounts of time and compute resources, so over the years more sophisticated methods have been developed to shorten the process.

MunEDA is a leading provider of solutions for analyzing variability and its effects on circuit operation and yield. They have developed highly effective solutions based on statistical analysis theory that are practical and save time. With the high volumes involved with modern consumer devices, even failures on the order of parts per million are unacceptable. So, it is vitally important that designers have the right tools to perform analysis up to and beyond six-sigma.

MunEDA will be presenting a free live webinar on the topic of Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis on May 8[SUP]th[/SUP] at 10AM PDT, there will also be presentations for the Asia and European time zones, to make viewing convenient.

The webinar will be moderated by MunEDA’s Andreas Ripp, and the presenter will be Dr. Michael Pronath, also from MunEDA. The webinar is intended for full-custom circuit designers, project leaders and managers responsible for design verification and full custom design for yield. They will discuss the pros and cons of a range of techniques to predict circuit yield and robustness. Also, they will highlight the applicability of the techniques to actual circuit design problems.

It will definitely be worthwhile to sign up for this webinar and to lean about this important topic.

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A Brief History of Methodics

A Brief History of Methodics
by Daniel Nenni on 04-29-2019 at 12:00 pm
Categories: EDA, IP, Perforce

Methodics has been a key player in IP management for over 10 years. In this section, Methodics shares their history, technology, and their role in developing IP Lifecycle Management (IPLM) solutions for the electronics industry.

Methodics is recognized as a premier provider of IP Lifecycle Management (IPLM) and traceability solutions for the Enterprise. Methodics solutions allow semiconductor design teams to benefit from the solutions ability to enable high-performance analog/mixed signal, digital, software, and SOC design collaboration across multi-site and multi-geographic design teams and to track the usage of their important design assets.

The journey started in 2006, when Methodics was founded in 2006 by two ex-Cadence experts in the Custom IC design tools space, Simon Butler and Fergus Slorach. After leaving Cadence, they started a consulting company called IC Methods, active in Silicon Valley from 2000 – 2006. As their consulting business grew, they needed to create a new company to service an engagement that had turned into a product for analog data management. With IP management in their DNA, They reused the IP in their consulting company name and Methodics was born!

Methodics first customer was Netlogic Microsystems, which was later to be acquired by Broadcom. Netlogic used the first commercial product developed by Methodics, VersIC, which provides analog design data management for Cadence Virtuoso. The development of Virtuoso was unique in that Methodics did not have to also develop an underlying data management layer as the first generation design data management companies in the semiconductor industry had to. During the late 1990’s and early 2000’s, a number of data management solutions had entered the market. Some of these solutions were open source, such as Subversion, and others were commercially available, like Perforce. These solutions had developed very robust data management offerings and were in use by 100,000’s of users in multiple industries.

In order to leverage these successful data management solutions, Methodics made the architectural decision to build a client layer on top of these products, allowing the team to focus it’s engineering efforts on developing a unique and full featured client, and not having to develop and maintain a layer for the design data management. Customers would benefit from this arrangement by having a full featured client integrated directly into the Virtuoso environment, and also have a robust data management layer that was widely in use, without necessarily having to concern themselves with the ongoings of the data management system.

It wasn’t too long before Methodics’ customers started asking for a solution that could be used in the digital domain as well. With the increase of companies adopting design reuse methodologies and using third party IP, Methodics decided to not only deliver a solution for digital design, but also one that could be used to manage and track IP reuse throughout their companies. This lead to the development of ProjectIC, which could be used not only for digital design, but analog design as well.

ProjectIC was an enterprise solution for releasing IP’s and cataloging them for reuse, SoC integration, tracking bugs across IP’s and managing permissions. ProjectIC also allowed for the comprehensive auditing of IP usage and user workspaces. With ProjectIC managers could assemble configurations of qualified releases as part of the larger SoC and make this available for designers to build their workspaces. Workspace management was a key technology within ProjectIC as well, and Methodics created a caching function to allow data to be populated in minimal time. Like VersIC before it, ProjectIC was built on top of the growing number of solutions available for data management, which allowed customers to quickly integrate to their development methodologies, especially if design teams had already adopted a commercially available system for data management.

In 2012, Methodics acquired Missing Link Software, which had developed Evolve, a test, regressions and release management tool focused on the digital space. Evolve tracked the entire design test history and provided audit capabilities on what tests were run, when and by whom. These were associated with DM releases and provided a way to gate releases based on the required quality for that point in the designs’ schedule.

With the acquisition of Missing Link, Methodics began to focus on the traceability of design information throughout the entire development process. While the core solutions of Methodics could keep track of who were developing IP, who were using which releases in which designs, and what designs were taped out using specific releases, customer wanted even more visibility into the life cycle of the IP. They wanted to know what requirements were used in developing IP, whether it was internally developed or acquired, what versions of the IP incorporated which features based on requirements, and how that IP was tested, verified, and integrated into the design. What was needed by customers was not only an IP management solution, but a methodology that could be adopted to track the lifecycle of an IP.

In 2017, Methodics released the Percipient platform, the second generation IP Lifecycle Management solution. Percipient built on the success of ProjectIC, but also began to allow for integrations into other engineering systems. In order to fully track an IP’s lifecycle, Percipient created integrations into requirements management systems, issue and defect systems, program and project management systems, and test management systems. These integrations allow for a fully traceable environment, from requirements, through design, to verification, of the lifecycle of an IP. Users of the Percipient platform can now not only track where an IP is used and which version is being used, but can now see what requirements were used in the development of an IP, any outstanding issues that IP might have and what other projects are affected, and whether the IP is meeting requirements based on current verification information.

Today, Methodics continues to develop solutions for fully traceable IP lifecycle management as well as solutions for mission critical industries that require strict adherence to functional safety requirements like automotive and ISO 26262 and Aerospace DO-254. Methodics is also working on solutions to increase engineering productivity. With workspaces growing exponentially, Methodics is developing solutions like WarpStor, which virtualizes engineering workspaces and drastically reduces data storage requirements while increasing network bandwidth. With the adoption of cloud computing by semiconductor companies, Methodics is also working on solutions to help customers work with hybrid compute environments of on premise and cloud based. Just as it was in 2006, Methodics goal is to bring value engineering teams by making the development environment more efficient by enabling close collaboration and the optimization of resources.

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The Evolution of the Extension Implant Part I

The Evolution of the Extension Implant Part I
by Daniel Nenni on 04-29-2019 at 7:00 am
Categories: Events, FinFET, Semiconductor Services, Threshold Systems
2 Comments

The 3D character of FinFET transistor structures pose a range of unique fabrication problems that can make it challenging to get these devices to yield. This is especially true for the all-important Extension implant that is put in place just prior to the nitride spacer formation.

The Extension implant is a central component of any transistor because the physical distance between the two elements of this high-dose implant defines the speed of the transistor. In planar transistors the Extension implant is self-aligned to the edges of the gate electrode and is the chief reason why great effort has been made in the past to minimize the Length (Lg) of the gate electrode, and in so doing, improve transistor performance.

In planar devices the Extension implant in realized by implanting dopant at a angle of 90 degrees to the silicon surface on either side of the gate electrode (refer to figure #1).

However, since the channel in a FinFET device is perpendicular to the silicon surface, this methodology is not an option. Instead, an angled implant is employed that implants the top and both sides of the fin, usually at a steep angle as illustrated in figure #2.

The issue with implanting the Extension at such a steep angle is that a large percentage of the dopant is not retained on the fin, but is instead ricocheted off. The relationship between the Extension implant angle and dopant retained on the sidewall is illustrated in figure #3. As this figure indicates, the steeper the implant angle, the less dopant is retained on the fin sidewalls.


Figure #3

Unfortunately, the height of the photoresist used to shield the PMOS devices during the NMOS Extension implant (and vice-versa) dictates that a steep double implant angle be used at an angle of + and -20 degrees. Figure #2 as illustrates one of these two implants.

This problem was mitigated in the first iteration of the FinFET architecture by the fact that the fins were sloped. This increased the incident angle of the implant and allowed more dopant to retained on the fin sidewalls. However, at the 14nm and 10nm nodes the fins were tall and vertical and the mitigating effect of sloped fins was absent (refer to figure #4).

The solution to this problem was to replace the tall photoresist used to separate the NMOS Extension implant and the PMOS Extension implant with a short hard mask that would permit a greater implant angle, and in so doing, allow a greater percentage of the dopant to remain on the fin sidewalls. Figure # 5 illustrates this approach to the problem. By employing a short hard mask material to shield the PMOS devices during the NMOS Extension implant (and vice versa), an implant angle of as much as +/-30 degrees can be used, and the majority of the dopant in the Extension implant is retained on the fin sidewalls ensuring a high performance device.


Figure #5

Of course the use of a hard mask in lieu of photoresist will only be advantageous in very dense regions where there would normally be numerous, tall photoresist lines. Since this is the most common situation on sub 14nm devices, this technique can be very useful.

However ultimately, the primary limiting factor in realizing the Extension implant into the fin is fin-to-fin shadowing. This is an increasing problem with the tall, closely spaced fins that are present at the 10nm node and below.

For more information on this topic and for detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

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EDA Update 2019

EDA Update 2019
by Daniel Nenni on 04-26-2019 at 12:00 pm
Categories: Cadence, EDA, Siemens EDA, Synopsys
3 Comments

Over the last six years EDA has experienced yet another disruption not unlike the Synopsys acquisition of Avant! in 2001 which positioned Synopsys for the EDA lead they still enjoy today. Or the hiring of famed venture capitalist Lip-Bu Tan in 2009 to be the CEO of struggling EDA pioneer Cadence Design Systems. Under Lip-Bu’s command Cadence has prospered like no other company in the history of EDA, absolutely.


In 2017 Siemens acquired Mentor Graphics for $4.5B representing a 21% stock premium. Acquisition rumors had been flying around the fabless semiconductor ecosystem but no one would have guessed it would be the largest industrial manufacturing company in Europe. At first the rumors were that Siemens would break-up and sell Mentor keeping only the groups that were part of Siemens core business, specifically they would sell the Mentor IC Group. Those rumors were flatly denied at the following Design Automation Conference during a CEO roundtable and now Mentor, including the IC group, is an integral part of the Siemens corporate strategy.

While Mentor was the biggest and most disruptive EDA acquisition there were many others. EDA has always been focused on non-organic growth (acquisitions) which we track on SemiWiki with our EDA Merger and Acquisitions Wiki. Synopsys is the largest acquiring EDA company scooping up EDA and IP companies as well as companies outside of the semiconductor ecosystem. In the last six years Synopsys has acquired 10 companies involved with software security and quality including the acquisition of Black Duck Software in 2017 for $547M. In total Synopsys has acquired more than 88 companies and we should expect the acquisition spree to continue.

Mentor financials are no longer public but inside sources say that revenue growth since the acquisition has by far exceeded expectations based on the extended reach of the Siemens workforce. Some estimate it to be as high as 25% growth. Synopsys and Cadence have also prospered since the Mentor acquisition was announced with revenues and market caps jumping in a very unEDA way. Synopsys (SNPS) stock price has almost doubled and the Cadence (CDNS) stock price has more than doubled. Clearly Wall Street has a renewed interest in EDA as they should. After all, EDA is where electronics begins.

Another significant EDA change that has evolved over the previous six years is the customer mix. Following Apple, systems companies are now taking control over their silicon destiny and developing their own chips. We see this on SemiWiki with the domain additions of our expanding readership. Systems companies now dominate our audience with the rapid growth of the IP, AI, Automotive, and IoT market segments.

Systems companies are also changing the way EDA tools are purchased. Rather than buying point tools and assembling custom tool flows (a fabless tradition), systems companies can buy complete tool flows and IP from Synopsys, Cadence or Mentor. The “One throat to choke” concept of customer support is a very attractive business strategy for companies venturing into the world of chip design for the first time.

Systems companies are good candidates for EDA in the cloud which is finally coming to fruition after many failed attempts. Cadence has been in the cloud for many years starting with Virtual CAD (VCAD) more than 20 years ago, Hosted Design Solutions (HDS) 10 years ago, and the Cadence Cloud announcement in 2018 with TSMC, Amazon, Microsoft, and Google as partners. In 2019 they announced the Cloudburst Platform which is another important EDA step towards full cloud implementation.

System companies are also not bound by the margin challenges of traditional fabless semiconductor companies. Apple for example can pay a much higher price for premium tools and support without notice to their bottom line. As a result, EDA companies are catering to system companies by providing and integrating IC tools with system level design tools. System based software development is also an EDA target as noted by the recent Synopsys acquisitions.

EDA has prospered in the last six years like no other time in EDA history and will continue to do so as semiconductors and electronic products continue to dominate modern life, absolutely.

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A Quick TSMC 2019 Tech Symposium Overview

A Quick TSMC 2019 Tech Symposium Overview
by Daniel Nenni on 04-26-2019 at 7:00 am
Categories: Events, FinFET, Foundries, TSMC
3 Comments

This year TSMC did a FinFET victory lap with the success of 16nm, 12nm, 10nm, and 7nm. It really is well deserved. Even though TSMC credits the ecosystem and customers, I credit TSMC and their relationship with Apple since it has pushed us all much harder than ever before. TSMC CEO C.C. Wei summed it up nicely in his keynote: Innovation, collaboration, and hard work.

Tom Dillinger also attended and he will be writing in more detail next week. Tom has been busy of late. He just finished his second textbook on VLSI Design Methodology Development for Prentice Hall. Remember, Tom started the FinFET discussion on SemiWiki in 2012 so you can bet FinFETs will be mentioned a time or two.

Here is an outline of what Tom will be writing about next week so stay tuned:

Advanced Technology Development and Materials Engineering:
1) N7/N7+ update
highlights: “Making 5G a Reality” — N7 as a technology enabler; D0 defect density improvement; 112Gbps PAM4 SerDes IP

2) N6 update
highlights: PPA comparisons to N7; ease of RTO/NTO migration from N7; new M0 routing (very unique!)

3) N5 update
highlights: schedule; D0 ramp; PPA comparisons to N7; “designed from the start for both mobile and HPC platforms”

4) Advanced process development / materials engineering
highlights: additional Vt devices for HPC in N5 and ULL/ULP technologies; high mobility (Ge) channel device; metal RIE (replacing damascene patterning); new metallization materials (graphene cap on Cu); future research into 2D semiconductor materials

5) Manufacturing excellence
highlights: focus on in-line process monitoring; maverick lot identification; “ink out good die in a bad zone” (very unique!); Continuous Process Improvement focused on wafer edge (very unique!); product-specific UpperSpecLimit + LowerSpecLimit statistical process control (also very unique!)

6) Roadmap for automotive platform
highlights: new “L2+” automotive grade introduced; focus on DPPM reduction; MCU’s in a vehicle transitioning from eFlash to MRAM memory offering

7) Roadmap for IoT platform
highlights: new eHVT device; unique analog device process engineering; new “dual-rail VDD” SRAM offerings (aggressive SRAM_Vmin scaling); MRAM roadmap

8) RF process development focus
highlights: device engineering to improve ft and fmax (in several processes), new thick metal to improve inductor Q factor; device model characterization

Although the specialty technologies presentation was very interesting, there’s probably not enough room in the article to cover MEMS, CIS (at near infrared wavelengths), etc.

“Front-End” and “Back-End” Advanced Packaging:
1) SoIC
highlights: diverse die size and stacking options (e.g., face-to-face and face-to-back bonding)

2) CoWoS
highlights: reticle size roadmap, embedded deep trench caps (DTC) in Silicon interposer

3) InFO
highlights: InFO_PoP through InFO via (TIV) scaling; InFO without substrate (2020)
4) 3DIC ecosystem support

History is always a part of semiconductor symposiums because semiconductors really have come a long way fueled by a series of technological disruptions. When I went away to college my beautiful girlfriend (wife) used to write letters to me everyday and call me on the weekends. My parents and grandparents had similar experiences. Shortly after we married, PCs and the internet landed on our desks and we emailed and Usenet-ed our way around the world. Then came smartphones and social media, probably the biggest disruption of them all. Phones are now in our hands and faces more than ever before but that is going to change.

The next disruption will be fueled by 5G and AI which is just now beginning. If you think semiconductors are important today just wait another ten years because you will not be able to survive without them, absolutely.

TSMC and the semiconductor industry have been living a very mobile life since PCs and phones left our desks. Moving forward, AI enabled edge devices will continue to be a semiconductor industry driver but the real upside for the foundry business will be getting the many zettabytes of data into the cloud and processed. Today Intel CPUs and GPUs dominate the cloud. Tomorrow it will be custom AI processors built by the cloud companies themselves in close partnership with the fabless semiconductor ecosystem and that means TSMC.

From writing letters to “real-time thought processing” in one lifetime, simply amazing.

Also read: 2019 TSMC Technology Symposium Review Part I

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Deep Learning, Reshaping the Industry or Holding to the Status Quo

Deep Learning, Reshaping the Industry or Holding to the Status Quo
by Daniel Payne on 04-25-2019 at 12:00 pm
Categories: EDA, Siemens EDA

AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator Jean-Marie Brunet from Mentor, a Siemens business:
Continue reading “Deep Learning, Reshaping the Industry or Holding to the Status Quo”

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Semiconductor Equipment Revenues To Drop 17% In 2019 On 29% Capex Spend Cuts

Semiconductor Equipment Revenues To Drop 17% In 2019 On 29% Capex Spend Cuts
by Robert Castellano on 04-25-2019 at 7:00 am
Categories: Information Network, Semiconductor Services

The semiconductor equipment market grew 37.3% in 2017 on the heels of capex spend by memory companies in order to increase bit capacity and move to more sophisticated products with smaller nanometer dimensions. Unfortunately these companies overspent resulting in excessive oversupply of memory chips. As memory prices started dropping, these companies put a halt to capex spend, and global equipment revenues increased only 13.9% in 2018. As excess inventory continues to increase in 2019, capex spend by these companies is projected to drop 29%, which will result in a significant reduction in equipment revenues in 2019.

As a result, the global semiconductor equipment market is forecast to drop 17% in 2019, reaching revenues of $64.5 billion, according to The Information Network’s report, “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts.”

To analyze the equipment market in 2019, we need to look at revenues and market shares for previous years. For 2018, Applied Materials (AMAT) ended the year with a market share of 18.8%, down from 21.2% in 2017, as shown in Chart 1. Fellow U.S. supplier Lam Research (LRCX) held a 16.8% share in 2018, down from 16.9% in 2017.


Japanese supplier Tokyo Electron Ltd. (OTCPK:TOELY), a major competitor of AMAT and LRCX in the deposition and etch sectors, held a 16.7% share in 2018, an increase of 1.6 points from a 15.1% share in 2017.

Chart 2 illustrates the change in revenue YoY for the leading semiconductor equipment companies. As I said above, the overall market increased 13.9%, so Lam’s growth of 13.7% attributed to its 0.1 point loss in share. AMAT’s lackluster growth of only 1.1% in 2018 contributed to its loss of 1.6 share points. Growth was less than the composite growth of companies ranked 8 through 75. The company has been losing market share to competitors YoY for the past three years.

KLA-Tencor (KLAC) grew 26.1%. I noted in a January 31 Seeking Alpha article entitled “KLA-Tencor And Metrology/Inspection Peers Will Be Less Impacted By Memory Capex Cuts Than The Rest Of The Equipment Industry In 2019” that a shift to more inspection in the fab was underway.


AMAT sells equipment for nearly all the processes used to make a semiconductor chip. Its two major segments are deposition and etch. In 2015-2017, deposition made up 46% of AMAT’s revenue, while etch made up 18-20% of revenues. These two sectors represent 2/3rd of the company’s revenues.

In 2018, the deposition market grew 3.9% and etch grew 4.4%. Since AMAT’s total revenues grew just 1.1%, it is obvious that the company lost shares in both sectors to competitors in these sectors, namely Lam Research, Tokyo Electron, and Hitachi High Technologies (OTC:HICTF).

2019 Analysis
Based on capex spend data as detailed in Table 1, The Information Network projects the semiconductor equipment market will drop 17% in 2019, compared to growth of 13.9% in 2018.


The main reason is the drop in capex spend by memory companies tied to the inventory overhang and oversupply of 3D NAND and DRAM chips. In total, capex spend is projected to drop 29.1% in 2019.


But there is another important factor investors need to consider: market share gains and losses. Why are market shares important?

Semiconductor manufacturers purchase equipment based on a “best of breed” strategy. Market share losses indicate equipment is not best of breed. When a customer decides to make additional equipment purchases to increase capacity, it will buy more from its current supplier. This means further market share gains.