Bronco Webinar 800x100 1
Semiconductor Expert Forum

Posted on

Webinar Recap: IP Security Threats in your SoC

Webinar Recap: IP Security Threats in your SoC
by Daniel Payne on 11-28-2019 at 10:00 am
Categories: EDA, Events, Perforce

Methodics Security SoC

Three years ago my youngest son purchased a $17 smart watch on eBay, but then my oldest son read an article warning about how that watch would sync with your phone, then send all of your contact info to an address in China. My youngest son then wisely turned the watch off, and never used it again. Hackers have been able to spoof and hide obstacles from the Tesla Model S using Autopilot. In 2015 hackers took control of a Jeep Cherokee through its entertainment system. A researcher in 2016 showed how he could control his or any other Nissan Leaf over the Internet.

Clearly we live in a connected world and the number of security threats to life-critical areas  need to be contained. The experts at Methodics just conducted a webinar on this topic: IP Security Threats in Your SoC, so I watched the 25 minute archived video to find out if there’s hope against security breaches .

Vishal Moondhra was the presenter and he noted how semiconductor IP use is growing, with a single SoC often containing 100’s of IP blocks. The most sensitive electronic design areas are considered life-critical: automotive, medical, aerospace and industrial.

IP use is really quite a patchwork, with blocks coming from multiple sources:

IP patchwork Methodics

The entire process of creating an IP block is quite dynamic, taking months to years with many versions being released along the lifecycle in order to meet changing requirements. IP users often have many tough questions which impact security,  like:

  • Which version of each IP is really being used?
  • What scenarios for attack have each IP been subjected to?
  • Are there security vulnerabilities in each IP being used within an SoC? 

Let’s consider the example of a USB core, where during post-silicon penetration testing a security issue is uncovered. Which USB core version was being used? Who provided the IP? Did previous versions have the same security issue? Are there other cores using the same IP?

Answers to these questions often take too much time, they could be incomplete, and they requires collaboration between multiple engineers across teams probably using spreadsheets and documents. This is not a good security approach.

There is a systematic way to meet these security challenges by using enterprise traceability with an IP Lifecycle Management approach in the Percipient tool from Methodics. Here’s the big picture of how Percipient fits into an ecosystem:

Starting at the bottom we see the Data Management (DM) layer which uses industry standard DM tools. On top of that is workspace management layer where each engineer has their specific portion of an SoC design. The IP Lifecycle Management (IPLM) layer is where engineers control the release management process. At the meta-layer there’s information attached to each IP block like which engineers are using it on projects and any special IP properties. The Bill Of Materials (BOM) layer is fully addressable, so you know exactly what your SoC project really contains, in a full hierarchical fashion.

In this too flow there are multiple vendor tools integrated like Jira for bug reporting, Jama and Doors for requirements gathering, even simulators from EDA vendors. The analytics portion allows you to quickly find out about any project, and know the overall security vulnerability of your system

The standards body Accellera has an IP Security Assurance (IPSA) Working Group, and Methodics is a member of that, because it takes a village to ensure that IP security is done right.

With a tool like Percipient you can now easily track the consumption of all IP use, like: who is using an IP block, where each IP block is being used, versions of an IP, report bugs per IP, even check IP against a list of approved projects. Once this is all setup, you can measure the security level by looking at a dashboard or traversing the IP hierarchy fo security issues where the colors define the security severity:

For IP BOM management there are three main features provided:

  • IP traceability
  • Versioning with dependencies
  • SoC version history

With Percipient there is traceability for all of the IP blocks and each workspace being used per engineer on the project, which enables the system to identify which users are affected by any IP version change. Event notifications are then automated for each engineer involved, so there are no costly communication delays.

The BOM is traceable and integrated with Jira for bug tracking, so all security impacted IPs are revealed. This traceability is created by adding a ‘security concern’ field for each bug, then Percipient rolls up all of the security concerns, and the displays the known Security Threats.

Security Threat Matrix

A live demo was then performed, walking us through how to use both Percipient and Jira tools to report bugs, assign security issues to an IP block, then seeing how the security matrix is auto-updated with the latest issues.

The final webinar part had Mr. Moondhra answering questions that were asked by attending engineers.

Q&A Session

Q: In the dashboard of security numbers, where do they come from?

A: All of the security numbers are automatically rolled up from the entire IP hierarchy of an SoC. In our demo, we had 28 concerns, 4 high, 1 medium, and 23 low. This live number is auto-updated as time progresses, and the integration ensures consistency between Jira and Percipient.

Q: How easy is it to bring 3rd party IP into Percipient?

A: We’ve made it easy to import IP, so each new IP version is typically brought in as a tar file using check-in with a tool like Perforce, then you release a new version into Percipient, and it takes just seconds,

Q: Who fills out security concern field?

A: The users who track bugs and security issues, using the Jira tool.

Summary

The challenges of IP security threats are a real and growing concern for teams building new SoCs. Using tools like Percipient and Jira for safety-critical designs in automotive, medical and other human-life fields makes a lot of sense. Instead of trying to create your own home-grown software patchwork, why not give Methodics a call to see how their approach would fit into your methodology.

Watch the archived video here. 

Related Blogs

Posted on

GM’s CES No Show: EmBARRAssing!

GM’s CES No Show: EmBARRAssing!
by Roger C. Lanctot on 11-28-2019 at 6:00 am
Categories: Automotive
1 Comment

After failing in 2017 and 2018 to put a single woman on-stage to deliver a high profile keynote, the Consumer Technology Association featured four female keynoters in 2019. Until recently, two women were on the docket for the 2020 show in January, but news arrived last week that General Motors’ CEO Mary Barra had cancelled her previously announced appearance.

All indications and expectations had been pointing to an announcement from Barra of more details regarding GM’s plans for new electric vehicles with the potential of a high profile EV reveal. Alas, GM claimed that the distraction of the United Auto Workers strike negated the General’s ability to put an EV prototype together in time.

There are few in the industry that buy that excuse or explanation. Any EV prototype would have been assembled without much assistance from the UAW rank and file. The more likely and credible explanation is that GM got wind of what Ford Motor Company was going to show last Sunday and realized that its own plans were half-baked.

GM executives generally, and Barra in particular, can talk a good game on earnings calls regarding the progress of the company’s Cruise Automation autonomous vehicle development or its plans for electric pickup truck production in Hamtramck in 2021. But when it comes to taking the stage at the largest technology event in the world it appears that GM lost its nerve.

There will be no shortage of auto makers touting their tech at the Las Vegas event. But Daimler will now grab the limelight as the sole car maker keynote.

Since her appointment as CEO on January 15, 2014, Barra’s signature strategy has been to downside the once-massive GM organization – selling off Opel to PSA, closing plants, and exiting multiple overseas markets. The moves, though severe and maybe even necessary, have been greeted with unmitigated admiration by investors as GM’s profits have spiked.

When the UAW walked out, an observer might have been forgiven for thinking that GM had decided that the soundest financial move for the company would be to eliminate vehicle production entirely – in the interest of improving profits. Sadly enough, the reality set in after a more than month-long work stoppage that actually making cars was essential to the company’s fiscal well being.

Nobody buys the explanation – from GM – that the UAW is to blame for Barra’s keynote cancellation. Just as GM failed to deliver a final negotiated agreement to the UAW in time to forestall the walkout, Barra and GM determined that there was more to be gained from NOT taking the stage than from taking the stage with a half-baked tale to tell.

GM is getting quite adept at not doing things, like not supporting California’s effort to preserve its exceptional status regarding emission controls and not launching a comprehensive EV strategy. GM’s decision to opt out of CES might even free up the stage for a rival – maybe even Ford, which would welcome the opportunity to talk about the new Mustang Mach-E.

If Mary Barra isn’t careful she may well be remembered more for what she didn’t do than for what she did while leading GM. Not showing up for CES is simply embarrassing.

Posted on

Webinar Recap: Challenges of Autonomous Vehicle Validation

Webinar Recap: Challenges of Autonomous Vehicle Validation
by Daniel Payne on 11-27-2019 at 10:00 am
Categories: Automotive, EDA, Siemens EDA

Waymo Jaguar

Autonomous vehicle progress is in the daily news, so it’s quite exciting to watch it develop with the help of SoC design, sensors, actuators and software from engineering teams spanning the entire globe. Tesla vehicles have reached Level 2 autonomy, Audi e-tron is at Level 3, and Waymo nearly at Level 5 with robot taxis being tested in Phoenix and Silicon Valley with a human driver ready to take the wheel. How are EDA, IP and systems companies facing the challenges of delivering electronic systems to enable autonomous vehicles that are safe under all conditions?

Tesla Model 3
Waymo Jaguar
Audi e-tron

To help answer that question I attended a webinar from Mentor, a Siemens business, presented by Dave Fritz – he’s the Global Technology Manager for Autonomous and ADAS. Three key concepts were shared to frame the webinar discussion on how to validate Autonomous Vehicles:

  1. Correct operation can only be determined in the context of the entire vehicle and the environment within which it is operating.
  2. Constrained random testing cannot guarantee coverage corner cases not possible with physical platforms, requires correlation between virtual and physical models.
  3. Consolidation of functionality is inevitable and will follow the path of other industries that have gone through the same transformation.

There are similarities in how a Smartphone Application Processor gets designed and validated compared to an ADAS/AV Controller, as they both have closed loop modeling as shown below with inputs on the left, outputs on the right, and a stack in the middle:

Smartphone App Processor
ADAS/AV Controller

With an AV the input stimulus comes from the real world driving conditions, so the number of states is huge, something way beyond what an App Processor would encounter, so a new validation methodology is sought. Instead of using a hardware-driven development process where hardware is developed first, then software and validation in sequence later, the continuous integration process of hardware and software being developed in parallel is a better approach.

The ecosystem for automotive design is quite complex, with multiple vendors which in turn calls for increased collaboration in order to meet the stringent ISO 26262 requirements for functional safety.

Automotive Ecosystem

Shown in blue above is the Virtual Model, and this early model is what allows AV design teams to get to market quicker by simulating and validating the entire environment.

From a product viewpoint Siemens has assembled quite a wide swath of technology called PAVE360 that allows automotive scenarios to be modeled, video viewed, and sensor models generating raw data for LIDAR, Radar and camera.

PAVE360

The beauty of this methodology is that a complete system like AV can be modeled and validated even prior to silicon. In the example Dave talked about how the ECO was modeled with a PowerPC core, the braking used physics-based control, transmission was modeled in Matlab, and even the dashboard was instrumented. Scenarios can be brought into PAVE360 from accident databases or created. Big questions are answered when running scenarios like:

  • Did we avoid the accident?
  • Did the occupants survive?

Yes, you can even model what happens to the passengers in terms of airbag interactions.

Air bag deployment

It’s wonderful to hear about AV companies driving millions of actual miles to build up experience in real driving, but to reach sufficient safety levels it has been estimated that you need to drive billions of miles, a goal not likely to happen. With virtual scenarios you can drive the billions of miles under any scenario.

Summary

The webinar also addressed issues like the fidelity of modeling abstraction, using formal methods, correlating between physical and virtual models, and handling corner cases. What I came away with after this webinar was that using PAVE360 as a platform creates a high confidence that virtual models indeed match physical, and that you can catch corner case issues in the lab before in the field. Of course, you want to continue on-road testing to ensure that there are no surprises with virtual testing.

To view the archive webinar start here.

 

 

Posted on

MEMS Actuation and the Art of Prototyping

MEMS Actuation and the Art of Prototyping
by Bernard Murphy on 11-27-2019 at 5:00 am
Categories: EDA, Prototyping, Siemens EDA

Thermal actuator prototyping

I mentioned a while back that I’m really getting into the role that sensors play in our new hyper-connected world – in the IoT, intelligent cars, homes, cities, industry, utilities, medicine, agriculture, etc, etc. If we can think of a way to sense it and connect it, someone is probably already doing it. But there’s more to these devices at the edge than sensing. One of the really neat things about MEMS is that you also can build machines – actuators – at the micro-level, delivering a breathtaking range of possibilities, already used in camera autofocus, laser-based 3D scanning using micro-mirrors, the tiny speakers in earbuds, pumps for biomedical analysis and many other applications.

These machines can get pretty complicated so John Stabenow (Mentor/Tanner) and Mary Ann Maher (SoftMEMS) eased me into it with a simple example – a thermal actuator, a device which causes an arm to bend (in this example) thanks to thermal expansion due to resistive heating. These are not toy examples; such devices have multiple real uses, to tilt micro mirrors for barcode reading or biomedical imaging, to tune lasers and to control adaptive optics for sight correction.

The idea is not difficult to understand. Two pads (blue above) are anchored to the substrate, and from these extend two arms, one narrow and one mostly wide (though it starts narrow, to not impede flexing I would guess). These arms are connected together at the far end. Now apply a voltage across the pads. Current flows through the arms, resistively heating each; obviously the narrow arm heats up more (higher resistance) and expands more than the wide arm. Since they’re connected at the far end, the structure bends upwards. Presto – you have a micro-machine with an arm which will bend upwards when you apply a voltage across the pads.

An interesting point here is that the design of these devices is pretty unconstrained. Where conventional semiconductor devices follow well-defined recipes and rules, teams who build these kinds of devices can up to a point do whatever they want, as long as their MEMS foundry is willing to support them. I’ve seen examples using polymers as part of the arm structure, rather than polysilicon, for preferable characteristics in bending at lower voltages. Less dramatically, all dimensions and materials (typically less exotic) are completely open for experimentation.

Clearly this means that design must be tested through a lot of virtual prototyping and analysis, though here that prototyping and analysis uses tools that wouldn’t look out of place in turbine design – drafting, 3D modeling and finite element analysis (FEA) of thermal and mechanical behaviors.

Mentor/Tanner, SoftMEMS and OnScale have partnered to provide a front-to-back solution for this prototyping. Tanner provide the tools to define parametrizable structures, a layer at a time. SoftMEMS converts this to 3D-models, given additional input on material choices and other parameters. OnScale then provides cloud-based FEA for elastic scalability in thermal and mechanical analyses. The results are directly viewable back in the Mentor and SoftMEMS tools.

The flow is setup so that you can easily run multiple trials in parallel to compare and contrast different options. The Tanner tools allow for parametrization with no need for coding in some cases, and with an option to code in more complex cases. Using these capabilities, you can parametrize the length of the actuator arms for example. Parameterized structures are called T-cells (think of them as a type of P-cell). SoftMEMS understands T-cells so can carry these through in 3D-modeling to generate multiple variants for prototyping analysis.

You might be thinking at this point (because I was) “OK, all very good and necessary, but how do I know that simulated behavior will correlate with manufactured behavior? Geometries and physical properties (resistance, thermal expansion coefficients, stiffness) can all be influenced by defects and manufacturing variability.

When you’re building regular semiconductors, you have access to PDKs with lots of rules, primitive devices and P-cells, all qualified by the foundry. These are what you rely on to know that your analysis of your design will correspond reasonably with what is finally built.

John and Mary Ann told me that the state of this art is not so advanced for MEMS, in part because of the huge variability in design of these devices, also because foundries, customers and tool makers are still figuring out how best to optimize yields. Currently it is typical to correlate 3D models with as-processed devices and to do statistical simulations to model variation so that they can develop reasonable correspondences between modeling and manufacturing.

This enables some platforms to offer PDKs for a stable range of cell types; however it is still necessary to support customers who want to experiment outside those constraints. This team finds in such cases that it is best to work with the foundry and customers to build PDKs on-the-fly to suit that customer’s special needs. Mary Ann cited both Bosch and ST as examples where this is quite common. She believes the Mentor-Tanner/SoftMEMS/OnScale partnership is differentiated from other prototyping options through it’s strengths in supporting such flows.

Very cool technology. I’m hoping to write about more examples over time. You can learn more about the collaboration HERE.

Posted on

Mentor unpacks LVS and LVL issues around advanced packaging

Mentor unpacks LVS and LVL issues around advanced packaging
by Tom Simon on 11-26-2019 at 6:00 am
Categories: EDA, Siemens EDA

Innovations in packaging have played an important role in improving system performance and area utilization. Advances like 2.5D interposers and fan-out wafer-level packaging (FOWLP) have allowed mixed dies to be used in a single package and have dramatically reduced the number of connections that need to go all the way to the PCB level. Mixed dies allows for mixing process nodes and combining different types of chip, or chiplets, in a single package. Also every time a net needs to travel to a PCB, there are issues with delay, coupling and transmission line effects, among other things. Yet despite their advantages these high density advanced packaging (HDAP) introduce more complexity into package verification. By moving what used to be on-chip or on-board signals into the package, complexity goes up greatly. At the same time the mature approaches for PCB or IC LVS and LVL cannot easily be applied to this problem.

Mentor unpacks LVS and LVL issues around advanced packaging

Mentor has recently published a technical paper entitled “A deep dive into HDAP LVS/LVL verification” written by Tarek Ramadan, that looks closely at the verification challenges which arrive when HDAP is used. There are a host of issues that stem from how new much of the technology is.

The ownership of design and verification for HDAP can vary from organization to organization and from chip to chip. Often, interposer designs are considered more chip centric and the responsibility can fall to the silicon teams. For FOWLP opposite can be the case and packaging teams may be tasked with verification.

Because of the interdependence between the IC’s and the package interconnect, package verification might have to wait for die information to stabilize and be delivered, which can delay the entire design. The paper describes the methods that can be used to permit parallel work to avoid schedule impacts.

Another complicating factor is that unlike IC processes, the ‘stack up’ for a package may vary from design to design due to the specifics of the chips and how they can be most efficiently combined. This prevents the use of off the shelf PDK-like information for layer and pin definitions. The tools used in these flows must be flexible and have the ability to adapt to design specific configurations easily.

To help readers understand the possibilities, the Mentor paper goes through several cases that illustrate how LVS and LVL verification can be completed in various scenarios. The first case deals with what happens when there is no explicit schematic for the interconnect in the package. Of course, with simpler technologies spreadsheets sufficed for determining correct package connections. The efficacy of spreadsheets goes down with the increased complexity of HDAP. The Mentor paper describes how labels on the geometry can be used to overcome these issues and help detect shorts and opens in these designs.

The other limitation that is encountered when trying to use chip level LVS and LVL tools is that there are no devices per se in the package netlist. The paper talks about how assembly level tools can work around this issue by creating placeholders for the pins in the package. There are a number of variations where the data needed is not directly available and the flows must accommodate this.

Based on their understanding of the issues enumerated in the paper, Mentor offers several tools that facilitate LVL and LVS verification of HDAP designs. Their Xpedition™ Substrate Integrator (xSI) tool performs HDAP system-level connectivity management and planning. Calibre 3DSTACK HDAP, used in conjunction with xSI, can run all the flows outlined in the paper, providing solutions for most cases. The paper makes good reading and can be downloaded from the Mentor website.

Posted on

Where has the ASIC Business Gone?

Where has the ASIC Business Gone?
by Daniel Nenni on 11-25-2019 at 10:00 am
Categories: Delta, Events, Semiconductor Services

Delta ASIC Design Services

As the traditional ASIC business disappears before our eyes with the recent divestitures and acquisitions, I have been asking questions amongst the fabless semiconductor ecosystem and am getting few answers.

Who or what is going to step in to enable start-ups and new to silicon systems companies with application specific chips?

Interestingly, I met Gert Jørgensen at the Tower Jazz Symposium last week. Gert is the VP for Sales and Marketing at the ASIC company DELTA Microelectronics. Gert has been with DELTA since 1982 where he worked as test engineer, design engineer and project manager before moving to business development.

Just in case you missed that, Gert has been doing ASICs for 37 years at the same company. He is the closest thing to a chip design unicorn as I have ever seen in my 35 year semiconductor career, absolutely.

Coincidentally, or not, Gert and I are doing a webinar on “Choosing the Right ASIC Manufacturing Model for Your Business” next week:

ASIC production is a part-science, part-art discipline which requires extensive knowledge. The many available options, which combine various 3rd party services and internal resources, require an understanding of the technical intricacies, the pros and cons, and the financial implications of each option. The more knowledge you have, the cheaper ASIC production can be for your company.

This webinar examines three common business models for hardware implementation including IC production and the financial impact of each. Using a real-life project case, it then identifies production volume break even points, distinguishing where one production model has an obvious financial benefit over another.

The webinar is on Tuesday December 3rd at 10am PST. SemiWiki Webinars are generally 30 minutes but more importantly they give you access to key people inside the semiconductor industry even if you are not able to attend it directly. Just register and you will be sent a link to the replay when it is finished. I always ask the presenters to give their contact information at the end of the presentation and they do. I hope to see you there!

About Delta
DELTA Microelectronics is a European company. We offer services ranging from design (front and back end), development of test solutions, production testing of components, wafer probing, failure analysis and logistics for the supply of components including purchasing of wafers and packaging.

We allow the customer to get the most cost effective combination of services.

History
DELTA has been supporting microelectronics development since 1976, providing services to hundreds of successful integrated circuit projects for some of the world’s best-known OEMs/IDMs and fabless semiconductor suppliers. We are a business unit of DELTA Danish Electronics, Light & Acoustics that was established in 1941.

DELTA Microelectronics is headquartered in Hørsholm, Denmark, and has an office in South Wales, UK.

Partners and in-house capabilities
A range of European and Far Eastern wafer and packaging partners enable DELTA to provide a full supply chain solution. DELTA has a large semiconductor test department where we can test wafers and components. Our test engineers ensure that the test hardware and software are customized to your chip. DELTA’s experienced ASIC design team is specialised in very low power chips, payment systems, RFID designs, sensor interfaces and optical chips.

Posted on

Could TSMC’s spend be part of the seasonal pattern?

Could TSMC’s spend be part of the seasonal pattern?
by Robert Maire on 11-25-2019 at 5:00 am
Categories: Semiconductor Advisors, Semiconductor Services

Is there more downside than upside in stocks?
Entering a seasonally weak period, then what?
Does China trade come back to haunt industry?
Cycle is past the bottom-But what kind of up cycle?

The most recent up cycle in the industry was a huge one, driven by a huge spend on NAND as SSD’s sucked up infinite number of devices. DRAM spend wasn’t too shabby either and logic/foundry kept up a fairly good pace.

In our long history of following the industry it was clearly one of the stronger up cycles…the kind of strength that makes less experienced management and industry analysts say that the industry is no longer cyclical. While the down cycle was not like the down cycles of old in which everyone lost money and some companies went out of business, it was still a significant cut in revenues and earning for a full year (or more).

No two cycles have ever been the same so its impossible to predict the size, shape, slope & length of the current upcycle with any accuracy.

Not firing on all cylinders
Its clear that memory is still weak and even Applied Materials, on its recent earnings release, didn’t want to comment on the timing of NAND recovery and DRAM seems out of the range of even wild speculation at this point.

However, foundry/logic seems to have been enough to get the industry off the bottom it was bouncing along on.

Our concern is that the memory recovery seems far enough away and uncertain enough that we have to discount it significantly when looking at valuation. If DRAM doesn’t recover til 2021 and NAND at the end of 2020 at best, what is that worth?

The excess capacity of idled tools sitting in fabs suggests that the memory recovery slope will be fairly shallow when it happens. It will almost certainly not be a huge tsunami of spend that we saw in the last up cycle. Memory makers still have a significant hangover from the drunken spending binge and likely will be a bit more conservative in the current up cycle when it comes.

Could china come back to the forefront of concerns?
Everyone did an excellent job of kicking the trade can down the road for quite a long time as we suggested would be the case.  The problem is that nothing was ever solved or accomplished.  If anything we are in worse shape now than when we started as both sides have had time to dig into positions.

China is less likely in our view to concede very much as they likely view the current administration as either a short timer or in a strategically weaker position or both.  The truce/business as usual seems to be the current status so not much has happened over the prior 3 years and all China has to do is stick it out for another year or maybe less.

We had written many groundbreaking articles about both Taiwan and Hong Kong risks over several years and those issues seem to be coming to a head, increasing the difficulty of a clean solution.

With elections less than a year away it seems less likely that a trade war that could hurt farmers and consumers would be started in earnest.  Trump has all but promised Tim Cook that Apple will be exempted (well played Tim..).

The delay of an EUV tool destined for China may be the beginning of a different approach to trade. We would also not be surprised for Huawei to become a target again.

We don’t see a “real” China trade solution
At best the administration will do some hand waving, declare victory and hope that everyone forgets prior promises.

At worst the administration needs a diversion from impeachment and starts a trade war to rally people around the flag and the administration.

The bottom line is that we see more downside than upside for chip stocks now than several months ago, related to China trade. An end to the trade war seems priced in but is now less certain.

Q1 seasonality may soften investors chip optimism
The calendar first quarter has almost always been the weakest quarter for chip stocks.  The industry is in the “post partum” depression after the strong holiday selling season for electronics. Certainly after the new Iphone cycle in September.

On a historical basis memory tends to be at its lowest price point based on seasonally lower demand.

Chinese new year always takes a week or two bite out of the quarter as well. In general Q1 is always weak for semiconductors.

Could TSMC’s spend be part of the seasonal pattern?
TSMC announced a huge uptick in spending which is the main driver of the “recovery” of the industry.  The spending seems clearly focused around an end of year “hockey stick” as TSMC gears up for next year’s 5NM production.

From a seasonal timing perspective, TSMC has to order and receive new equipment in Q4 and Q1 to get process ready in Q2 and production ready for the next Iphone in Q3.

TSMC moves less equipment into the fab in Q3 as it usually has been in ramp mode.

Basically TSMC is now in an annual spending pattern based on release dates of the new Iphone by its biggest and bestus customer, Apple.

This suggests that after a couple of strong quarters of tool orders and shipments that TSMC will likely slow going into the summer of 2020.

The question at hand will then be will memory come back before TSMC’s spending spree slows down or could the industry see a plateau or air pocket?

We think its fairly likely that TSMC will not likely increase spend from where it is now.  The probability is higher that TSMC will slow from this peak spend period spanning Q4 and Q1.

The Stocks
After recommending that investors get into the stocks prior to the quarterly reporting season which we predicted would have an upside surprise, we suggested, after Applied reported last week that investors would be better off taking some profits off the table at the end of earnings season after Applied reported.

So far that appears to be the case as we have seen stock price weakness since we made that call post Applied’s rounding out of a great quarterly earning season.

The stocks still seem to have a bit of air in them as they are still trading at industry historically high valuations on a P/E basis, yet fundamentals are not at historically high levels nor does it look like we are getting there soon given memories uncertainty.

In short we think downside beta remains higher than upside beta in current circumstances.  We think that we could see the stock prices stick around here or go lower but we are hard pressed to find a motivation to make them go higher in the near term. There remain a lot of cross currents and risks over the next quarter or two which are not priced in, whereas a strong recovery has been already priced in.

We think our negative call last week remains the appropriate position on the stocks….

Posted on

Top Three Reasons to Attend the Synopsys Fusion Compiler Event!

Top Three Reasons to Attend the Synopsys Fusion Compiler Event!
by Daniel Nenni on 11-22-2019 at 10:00 am
Categories: EDA, Events, Synopsys

As a professional semiconductor event attendee I can pretty much tell if an event will be successful by looking at the agenda. What I look for is simple, customer presentations. Not company presentations or partner presentations but actual customer case studies presented by name brand companies. For this event Google, Intel, and Samsung stand out for me.

Intel because they have gone through some major disruptions in the last year. Example: Hiring Jim Keller as senior vice president in the Technology, Systems Architecture and Client Group (TSCG) and general manager of the Silicon Engineering Group (SEG). Jim is a very disruptive personality and that is exactly what Intel needed in the design ranks, my opinion.

Google because they are doing some extremely clever stuff! The whole Google approach to chip design is also very disruptive. If you ever get a chance to participate in a Google chip project do it if at all possible. If you ever get to hear a Google chip person speak do not miss it. Seriously, I speak from experience here on both parts, absolutely.

Samsung is a bleeding edge company in regards to logic and memory chips. They design a very wide spectrum of silicon and systems and literally go where no chip designers have gone before. Always worth listening to Samsung.

Synopsys’ Fusion Compiler was announced a year ago and from what I have heard it is doing quite well delivering on promises Synopsys made from the beginning. I know of a very large SoC that was taped out recently using Fusion Compiler and there were no complaints which is very rare in this business. In fact, I was told that Synopsys support was excellent for this project.

Fusion Compiler Technical Symposium
Wednesday, December 4, 2:00 PM, Synopsys Building 1

Since its launch one year ago, Synopsys’ Fusion Compiler™ RTL-to-GDSII product has delivered on its promise to help digital designers efficiently bring their differentiated products to market faster, realizing their Simply Better PPA™ goals.

But you don’t have to take our word for it.

Come hear from industry leaders including Arm, Google, Intel, Renesas, and Samsung at the Fusion Compiler Technology Symposium as they discuss today’s design challenges and how these challenges are being solved with Fusion Compiler.

AGENDA

2:00 PM Registration and Refreshments

3:00 PM Presentations

5:00 PM Networking Reception and Entertainment

LOCATION

Synopsys – Building 1 at the New Pathline Park Complex

800 N. Mary Ave.

Sunnyvale, CA 94085

Register Now!

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Posted on

U.S.-China trade war continues

U.S.-China trade war continues
by Bill Jewell on 11-22-2019 at 6:00 am
Categories: China, Semiconductor Intelligence, Semiconductor Services
2 Comments

Electronics production

The trade dispute between the U.S. and China continues to drag on. According to Reuters, U.S. President Donald Trump recently threatened to raise tariffs further on Chinese imports if no deal is reached. Tariffs affecting most consumer electronics imports from China are scheduled to go into effect on December 15, according to a timeline from China Briefing.

The trade war has already had a significant impact on U.S. electronics imports. In the first three quarters of 2019, total U.S. electronics imports have dropped 6% versus the first three quarters of 2018. Imports from China dropped 12%. China still is by far the largest source of electronics imports, accounting for 54% in 1Q-3Q 2019. The second largest source, Mexico, dropped 3%. Two countries benefiting from the U.S.-China dispute are Vietnam (third largest) and Taiwan (fourth largest). U.S. electronics imports versus a year ago are up 59% from Vietnam and 64% from Taiwan. All other significant sources of U.S. electronics imports were down from a year ago, with the biggest declines coming from South Korea (down 32%) and Malaysia (down 29%).

Numerous companies have shifted production out of China in recent months. Samsung ended mobile phone production in China, moving to countries such as Vietnam and India. Inventec Corp., plans to shift production of notebook PCs (including HP branded PCs) for the U.S. market from China to Taiwan. A CNBC article cites Vietnam, Taiwan and Thailand as the biggest beneficiaries of the production shifts.

Electronics production data by country demonstrates the shifting production. China electronics year-to-year growth was in the 12% to 15% range in each month of 2018. In 2019, growth has ranged from 7% to 11%. Taiwan’s production has boomed in 2019, reaching a 24% three-month-average growth versus a year ago in August. Vietnam has experienced accelerating electronics growth in 2019, reaching 12% in October. U.S. electronics production has been showing modest growth in the 5% to 7% range for most of 2018 and 2019 but slipped to 2% in September. Thus, it appears the U.S.-China trade dispute has not been a significant boost to U.S. electronics manufacturing. Other major electronics producing countries have been weak lately. South Korea, Japan and the 28 countries of the European Union (EU28) have been flat to negative for most of 2019.

Although the shift of electronics production from China to other Asian countries has been accelerated by the current trade dispute, the trend has been in place over the last few years. Multinational companies are moving production to Vietnam and other countries due to lower labor costs, favorable trade conditions and openness to foreign investment.

How is the trade dispute affecting overall electronics in 2019? Key electronic equipment markets remain weak. Gartner projects combined unit shipments of PCs and tablets will decline 3.1% in 2019, followed by a 2.4% decline in 2020. IDC forecasts a 2.2% drop in smartphone units in 2019. Smartphones are expected to grow 1.6% in 2020, helped by the emerging 5G market. The impact of the trade dispute on PC, tablet and smartphone shipments is difficult to measure. These are mature markets which have been weak the last few years.

How will the U.S.-China trade dispute affect the economy and electronics going forward? Goldman Sachs estimated the trade dispute has cut 2019 GDP by 0.5% in the U.S. and 0.7% in China. The Consumer Technology Association (CTA) estimates tariffs on China have cost the U.S. consumer technology industry almost $12 billion since July 2018.

U.S. consumers have not yet seen tariff driven price increases on most electronics. However, unless a resolution is reached, on December 15 a 15% tariff will be applied to U.S. imports from China of mobile phones, TVs, digital cameras, set-top boxes, laptop PCs, tablets, video monitors, headphones, video game consoles, smartwatches, fitness trackers and other consumer products. Consumers are conditioned to expect a general trend of lower prices and higher functionality for electronics. If implemented, the 15% tariff will not affect the 2019 holiday season, but going forward it will negatively impact the U.S. demand for consumer electronics in 2020.

Posted on

MIPI gaining traction in vehicle ADAS and ADS

MIPI gaining traction in vehicle ADAS and ADS
by Tom Simon on 11-21-2019 at 10:00 am
Categories: Automotive, IP, Mixel

I am old enough to remember when cars did not come with air conditioning unless you purchased it as an option. Of course, now you can’t even find a car that doesn’t come with air conditioning. So, it goes with Advanced driver assistance systems (ADAS). They are becoming more and more common and will certainly become baseline features in cars in the future. In all likelihood autonomous driving systems (ADS) will follow the same path as they become more feasible and affordable. Video data from sensors, either heading to an internal display or to a computer for processing, is required for both of these systems.

The automotive environment brings with it a number of specialized requirements for these systems, such as low power and high reliability in a challenging physical environment. They also must also be cost effective. System designers for ADAS and ADS have been turning to existing standards for transferring video information in mobile systems, which share many of the same requirements as ADAS and ADS. Specifically, there has been a lot of interest in MIPI® Alliance specifications. The proven technology found in the well-established D-PHY℠ for connecting high resolution cameras, vision processor and displays has become a popular solution for in-vehicle video needs.

Mixel, a leading provider of mixed signal mobile IP has published an article discussing the application of their D-PHY IP in GEO Semiconductors’ GW5 CVP product family. MIPI D-PHY is a source synchronous PHY that uses one clock lane and a varying number of data lanes. It is a widely adopted standard that has been in use since 2009. There are two differential pins per signal. D-PHY can be used with MIPI CSI-2℠, DSI℠ and DSI-2℠, to connect to cameras and displays. Mixel’s D-PHY v2.1 TX and RX IPs can handle 2.5Gbps per lane, up to 4 lanes to achieve 10Gbps. The TX and RX IPs are AEC-Q100 compliant for auto-grade 0/1/2 temperature ranges.

In GEO Semiconductor’s product they used D-PHY v1.1 TX and RX with 4 lanes of 1.5 Gbps, for a total of 6Gbps. The GEO GW5400 includes in-camera vision processing to enable ADAS functionality. The GEO GW5 supports up to 8-megapixels and includes GEO’s eWARP® geometric processor, innovative High Dynamic Range (HDR) Image Signal processor (ISP), and 2D graphics functionality. For the GEO GW5 there are 2 RX interfaces, supporting dual sensors. However virtual channels can be used to connect to more sensors. There is an HDR feature that allows each RX interface to receive images from multiple HDR sensors and combine them into a single high dynamic range video stream.

The Mixel PHY IP come with a BIST engine that can be used for IC, board or system tests. Mixel has had silicon success across multiple nodes at a variety of foundries. Mixel reports widespread deployment of their IP in ADAS and ADS chipsets.

MIPI interfaces will increasingly play a major role in ADAS and ADS systems. In the future in addition to radar, LIDAR and video sensor input, ADAS and ADS will also rely on data links between vehicles and between vehicles and their surroundings. Sensor data rates and resolution will increase over time as well. From reading the Mixel article it is pretty clear that they intend to stay on the forefront of the technology. The article which can be found here also goes into more details about the specifics of their offering and the GEO Semiconductor products that employ their IP.

Also Read:

A MIPI CSI-2/MIPI D-PHY Solution for AI Edge Devices

FD-SOI Offers Refreshing Performance and Flexibility for Mobile Applications

New Processor Helps Move Inference to the Edge