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Mustang Mach-E!

Mustang Mach-E!
by Roger C. Lanctot on 11-21-2019 at 6:00 am
Categories: Automotive

Ford Motor Company detonated an epochal explosive in the form of an electrified Mustang SUV on the eve of the Los Angeles Auto Show last night. The move marked an industry altering turning point as auto makers commence the process of electrifying their internal combustion engine line-ups in anticipation of a global market embracing electrification.

The move came three days ahead of a rumored electrified pickup truck announcement expected from Tesla Motors and follows by one year Rivian’s announcement of plans for its own electrified pickup truck. Of course, the significance of a rush to electrify pickup trucks cannot be lost on Ford, which makes the F-150 – the best-selling vehicle of any kind in the U.S. for the past 36 years.

Ford sells nearly a million F Series pickup trucks every year and has tipped its plans for a full electric version sometime in late 2020 or early 2021. That is about the same timing that Rivian (in which Ford is an investor) has discussed for its own EV pickup – i.e. end of 2020. For its part General Motors asserted that it is in the process of refitting its Hamtramck plant to make electric pickup trucks – though a specific timeframe for delivery is unclear.

The electric Mustang Mach-E likely represents the first domino to fall in a sweeping shift in sports car propulsion of domestic makes from internal combustion to EV tech. Ford’s introduction of an electric Mustang SUV likely points to the eventual arrival of Cadillac and Corvette equivalents and, perhaps further down the road, an EV Camaro and EV FCA Challenger.

With sales of sedans and sports cars in decline the shift to SUV form factors with EV propulsion suddenly seems like a no-brainer. But the boldness and courage required by Ford to make this move ought not to be underestimated.

Ford (with the Focus) and GM (with the Volt and Bolt) have flirted with EVs in the past, but these expensive endeavors have failed to fire up consumers to the point of putting up impressive sales figures. These models had the trappings of “regulatory” offerings intended to fulfill California zero emission requirements or Federal Corporate Average Fleet Efficiency (CAFÉ) standards. Dealers were unenthusiastic about these early EV models and advertising dollars in support of the effort were scarce.

The launch of the Mustang Mach-E moves Ford’s EV effort to center stage and the announcement, coming at the L.A. Auto Show with a significant dealer audience in attendance, marks a pivotal moment for the industry. The iconic Mustang will now stand as the fulcrum of a committed EV marketing effort that will reshape Ford’s relationship with its customers, its dealers, and its suppliers.

Ford dealers will now be on the front lines of the new vehicle resale proposition of marketing both ICE and EV vehicles on the same showroom floor. The software and connectivity elements of the Mach-E with over the air software updates and an exceptionally nimble infotainment system will present a substantial contrast to existing in-vehicle systems – at least until elements of the Mach E can be extended across the other vehicles in the Ford line up.

As important as the shift of domestic marques from ICE to EV will be as it unfolds, the shift of the pickup sector will be even more powerful and momentous. The vehicle volumes and profits at stake in the pickup sector are more critical to the automakers involved – GM, Ford and FCA – and the change in performance characteristics and expectations will require different means of communication.

At last week’s Fleet Forward event, put on by Bobit Media, an industry analyst from Vincentric noted the total cost of ownership advantage of high-mileage EVs. A Cox Automotive executive, also speaking at Fleet Forward, noted the growing number of EVs making their way to the market … and with greater range. (The Mustang Mach-E has a 300-mile range, according to Ford.)

SOURCE: Cox Automotive

Shifting sports cars to EV propulsion is an almost pure enhancement – if you ignore the loss of soothing engine growls and roars. Shifting pickups along the same path may require some demonstration and convincing – though Ford has already taken the first steps in this direction with its stunt of towing a railroad train with an EV propelled F Series truck earlier this year.

The transformative impact of the Mustang Mach-E launch cannot have been lost on attendees of last night’s press event or Ford dealers or Ford competitors. Along with the Mach E comes a comprehensive software update solution, a new in-house developed infotainment user interface (dubbed “Menlo”), smartphone-based keyless vehicle access via the FordPass app, and a global fast/and regular speed charging network – in conjunction with multiple partners including Shell’s Greenlots.

It’s a new day for Ford, a rebirth for the Mustang, and a turning point for the industry. It will be interesting to see what impact electrified pickups will have following the arrival of a Mustang rendered silent but deadly with its electrified powertrain.

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WEBINAR REPLAY: AWS (Amazon) and ClioSoft Describe Best Cloud Practices

WEBINAR REPLAY: AWS (Amazon) and ClioSoft Describe Best Cloud Practices
by Randy Smith on 11-20-2019 at 10:00 am
Categories: Cliosoft, EDA, Events

ClioSoft has been working with the leading cloud computing providers running experiments on various EDA cloud architectures for a while now. One example of that was a project with Google I previously wrote a blog about, For EDA Users: The Cloud Should Not Be Just a Compute Farm. Since then, ClioSoft has also teamed up with Amazon Web Services (AWS) to show examples and talk about best practices for designing in the cloud. This information was shared at a webinar on Thursday, October 17th, 2019. You can sign up to view the replay of that webinar here.

All of us have heard about the advantages of on-demand computing. Some of the EDA companies have now come along and offered licensing solutions to accommodate that. However, there are multiple ways to architect EDA solutions in the cloud. I think it is important that everyone understands the trade-offs with various cloud architectures. Design Data Management tools, such as those that come from ClioSoft, provide additional benefits to cloud architectures, though it is not the case that “one size fits all” when it comes to implementing your cloud architecture. In fact, at a high level, there are at least two dimensions to the architectural choices – the tool architecture and the data architecture.

When considering the tool architecture in a cloud environment, we are describing where tools will run. Today that even applies to interactive tools. Cloud services are giving us ever-decreasing latencies, and since we can render full-motion video over the internet, it should not be a problem to render interactive EDA tools over the internet. However, to work optimally, we need to have the correct hardware for each tool. We also need to understand EDA tool workloads – how many resources, for how long, at what point in the design flow?

Data architecture is also critical to your efficiency and cost. You need to decide where you will keep each type of data. However, much more than that, modern solutions involve caching data. You also want to consider persistent storage in the cloud. Where are the master copies of each type of data (e.g., library data, design data, simulation results, etc.)? Where are the caches? There are lots of decisions. Depending on your tools, it may be difficult to change your architectural choice later. The benefits are tremendous, but you also want to be correct as possible on your initial implementation. To do that, you need information on all the optimization parameters you have at your control on AWS – Amazon EC2 Instance Types, Operation System Optimization, Networking, Storage, and Kernel Virtual Memory. There is a lot to learn about and control. Do you know what an AMI is?

In addition to superior design data management solutions, information is exactly what ClioSoft has been preparing for its customers. The information shared in the previously mentioned blog was quite helpful. Now ClioSoft has followed that up with this webinar collaboration with AWS. Of course, ClioSoft is in the AWS partner network.

Speaking for AWS in the webinar is David Pellerin, the AWS Head of Worldwide Business Development. Dave has an interesting background. He has been with Amazon for more than seven years. He has worked in a variety of fields, including accelerated and reconfigurable computing, data center and cloud services, HPC software development tools, field-programmable gate arrays, financial computing, life sciences, and health IT. Dave has also authored several books related to programming and design, including VHDL Made Easy. Clearly, he understands EDA, too.

Also speaking in the webinar is Karim Khalfan, VP of Application Engineering at ClioSoft. I have known Karim for a very long time, and I appreciate that not only does he have a deep understanding of design data management, but that he also has a knack for making these complex issues easy to understand. Adding Dave’s experiences in textbooks, I think everyone will be able to learn a lot from this webinar.

Also Read

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

For EDA Users: The Cloud Should Not Be Just a Compute Farm

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NXP Pushes GHz Performance in Crossover MCU

NXP Pushes GHz Performance in Crossover MCU
by Bernard Murphy on 11-20-2019 at 6:00 am
Categories: AI, Automotive, IoT, Security

RT1170 system

I first heard about NXP crossover MCUs at the 2017 TechCon. I got another update at this year’s TechCon, this time their progress on performance and capability in this family. They’ve been ramping performance – a lot – now to a gigahertz, based on a dual-core architecture, M7 and M4. They position this as between 2 and 9X faster than competitive solutions, certainly a major performance advantage.

Quick refresher on why they’re doing this. MCUs used to be the staid but inexpensive and reliable cousins of the flashier processors you’d find in your phones. What you wanted in your car, appliances, printers and many applications wasn’t a lot of flash and features; you wanted reliability and low cost. Now thanks to the explosion in expectations for what everything and anything should be able to do, we now want very high performance and very low power, communications, human machine interfaces, voice recognition and face id everywhere. Still at very low cost.

Perhaps you could do this by scaling advanced processors down to MCU price levels (few $), but that’s a big stretch. And there are other considerations besides cost. Many MCU apps depend on real-time support and for that they have to run real-time operating systems rather than the Linux OS used by their up-market cousins. On top of that, requiring a large base of MCU application developers to switch OS would be impractical. Also, while product teams using MCUs want to take advantage of AI capabilities, they have limited resources and expertise. For all these reasons, NXP argues that it’s best to start with architectures built for MCU developers and grow them into supporting advanced features. Makes sense to me.

The dual processor approach follows a familiar big.little kind of theme, in which a high performance (1GHz) M7 core handles advanced applications only needing to run intermittently, such as smart speaker functions (audio pre-processing through echo cancellation, noise suppression, beamforming, etc). A lower-performance (400MHz), more power efficient core (M4) can handle lighter weight and standby tasks such as wake-word processing. In fact the M4 can handle more than that, according to Gowri Chindalore, Head of Strategy for embedded processing. He told me it can also handle fingerprint sensing, quick voice recognition and quick face id. The two cores are in separate power domains; on detecting a wake-word or gesture, the M4 wakes the M7 for phrase recognition, perhaps “hey it’s dark in here, turn on the lights”. Gowri said the system can support between 100 and 150 phrases.

NXP became one of the pioneers in machine learning (ML) programmability across a range of platforms when they introduced their eIQ ML software development environment. This can start from any of the standard ML trained network representations and map to differing targets, optimizing the mapping as needed to best suit the resources of a given target. All this without having to understand all the technical details of TensorFlow Lite, Glow and other models. Another plus for MCU developers who want the capability without a lot of extra training.

There are a few more important features. The RT1170 hosts a 2D GPU, an addition to earlier processors, so it can generate complex graphics for appliance and industrial systems. It’s also automotive-qualified, so think cockpit displays and graphical steering wheel controls. This MCU also provides a hardware root of trust (HRoT) through their EdgeLock subsystem (HRoTs are the way all serious hardware security is going now). EdgeLock provides secure boot, a range of cryptography options and a secure real-time clock, useful in many contexts eg forcing a timeout after an unreasonable delay.

One more point that has raised some questions: the RT1170 doesn’t use embedded flash but rather 2MB of (embedded) SRAM. This decision was apparently customer driven; customers didn’t want the performance hit or the cost of flash. To ensure there is no security problem as a result of this change, data is stored encrypted in SRAM and is decrypted on-the-fly in zero-cycles as it’s read into the MCU.

The RT1170 is built on 28nm FDSOI technology, providing all the low-power management features you need (power islands, low leakage) but still at a much more price-conscious level than you’d find in application processors or GPUs at more advanced FinFET nodes.

NXP sees this platform having multiple applications: industrial and retail (factory automation controllers, unmanned vehicles, building access controls, retail display controllers), consumer and healthcare (smart home, professional audio applications and patient monitoring systems) and automotive applications (in-vehicle HMIs and 2-wheeler instrument clusters). Lots of opportunities – we can’t all build our own custom devices, in fact most of us can’t; we need more solutions like this. You can learn more about the RT1170 HERE.

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Webinar – IP for securing automotive systems

Webinar – IP for securing automotive systems
by admin on 11-19-2019 at 10:00 am
Categories: Automotive, EDA, Events

Modern cars have about as much in common with their predecessors as modern cell phones have in common with dial up land-line phones. Cars now are loaded with a bevy of electronics, some of which serve the convenience of the driver and others are essential for vehicle operation and occupant safety. With the introduction of sophisticated electronics, comes the potential for security threats.

Cars often already have built-in cellular connections and will be expanding their interactions with external devices in the form of electronic keys, other vehicles, roadway instrumentation, traffic and routing information, over the air updates and more. With each of these communication channels comes the potential for vulnerability. Defending these systems against compromise is essential for preventing theft, nuisance, damage, and collision – with the threat of bodily injury or death.

Automotive system designers need to address the challenges of hardening and securing vehicles against these threats. Fortunately, there is IP available that can help provide the kinds of protection that vehicle systems need. Silvaco, a leading supplier of IP, will be offering a free webinar on the topic of “IP Solutions for Secure Autonomous Driving” on December 3 2019 at 10AM PST. The presenter is Conor Culhane, Senior Application Engineer at Silvaco. He specializes in embedded security solutions, and holds a BS in Computer Engineering from Georgia Institute of Technology.

His presentation will cover many aspects of building secure SoCs for automotive applications. Connected vehicles present a variety of attack surfaces. To help  counter this software upgrades must be secure and critical vehicle networks need to be physically isolated. Part and parcel of this is hardware identification for authentication and secure cryptographic key management.

The webinar will also cover security IP solutions from Silvaco that address the needs of this market. They offer security processors, cryptography, hashing and secure key management. They also offer modules that serve as runtime integrity checkers and DRAM protection. Lastly Silvaco has cypher engines for secure AES and public key engine accelerators.

While thieves may not be able to jump in and rub two wires together to steal cars anymore, clever malicious actors will be looking for other ways to steal or damage cars, or cause worse problems. System designers need to stay apprised of the latest developments in automotive security. This webinar will go a long way to providing this kind of information. Registration is available on the Silvaco web site.

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S2C Delivers FPGA Prototyping Solutions with the Industry’s Highest Capacity FPGA from Intel!

S2C Delivers FPGA Prototyping Solutions with the Industry’s Highest Capacity FPGA from Intel!
by Daniel Nenni on 11-19-2019 at 6:00 am
Categories: Prototyping, S2C EDA

In 2016 we published our book “Prototypical: The Emergence of FPGA-Based Prototyping for SoC Design” which began an incredible journey through ASIC prototyping. While we are working on an update to that book there is some recent Prototyping news that is worthy of praise.

First and foremost, S2C Inc. has just announced THE single most dense FPGA prototyping boards the industry has ever seen. Based on the new Intel Stratix 10 GX 10M FPGA, S2C has announced single, dual and quad FPGA configurations.

UPCOMING WEBINAR: Prototyping with Intel’s New 80M FPGA and S2C!

The Stratix 10 GX 10M FGA is the newest addition to Intel’s 14nm Stratix 10 Family and features up to 80 million ASIC gates (2.5x denser than Xilinx). Imagine that, more than 320M ASIC gates on a single board, wow!

And now that Intel 10nm is in high volume manufacturing I expect to see even higher density FPGAs coming out in 2020. The legendary Xilinx vs Intel (Altera) FPGA wars are back on, absolutely!

S2C Product Highlights:

  • Supports designs up to 80 million ASIC gates with a single FPGA, simplifying the prototyping effort for complex design.
  • Prodigy Logic System hardware facilitates comprehensive out-of-the-box prototyping, reducing time-to-prototyping.
  • Complete Player Pro prototyping software-stack streamlines Quartus-based FPGA design compilation, reducing prototype configuration time.
  • Supported by Prodigy MDM debug module, accelerating design debug.
  • Supported by a rich portfolio of Prototype Ready IP in the form of plug-play daughter cards, enabling rapid prototype platform bring-up.

The Single 10M Prodigy Logic System is optimized and trimmed to assure signal integrity and enable the best performance, supporting up to 1.4 Gbps for general-purpose I/O, and up to 16 Gbps for the high-speed transceivers.  Remote management capabilities are supported over USB or Ethernet, including FPGA configuration, power on/off/recycle, Virtue UART for debugging, system monitoring, as well as identification of the presence of specific Prodigy daughter cards, and remote test with the auto-detection technology.

“Intel’s Stratix 10 GX 10M FPGA is approximately 2.5 times larger than the current largest commercially available FPGA and is likely to be the highest-capacity single FPGA for the next 2 to 3 years.  Using the Stratix 10 GX 10M FPGA will significantly increase current SoC/ASIC design prototyping capacity, simplify the prototyping process and achieve a much lower cost per gate”, commented Toshio Nakama, CEO of S2C.  “Our immediate availability of the Single 10M Prodigy Logic System marks our strong commitment to deliver the best prototyping solutions to accelerate their software development and design validation.”

Single S10 10M Prodigy™ Logic System

The other interesting piece of Prototyping news is that Synopsys officially acquired DINI last week. Mike Dini has been a fixture on the prototyping scene for as long as I can remember. He could be seen at various conferences reading the newspaper in his 10×10 booth. Unfortunately, Dini spent most of 2018 in a legal battle with Cadence. The first filing was in June of 2017 and the resolution (in DINI’s favor according to my sources) was on 10/18/2018. David vs Goliath legal battles can really take the wind out of David’s sails/sales, been there done that. Synopsys now has one less competitor to worry about and Mike Dini has the Cadence settlement and the Synopsys acquisition cash. Congratulations on the exit Mike!

Also Read:

AI Chip Prototyping Plan

WEBNAR: How ASIC/SoC Rapid Prototyping Solutions Can Help You!

Are the 100 Most Promising AI Start-ups Prototyping?

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ITC shines light on new Mentor Test announcements

ITC shines light on new Mentor Test announcements
by Tom Simon on 11-18-2019 at 10:00 am
Categories: EDA, Siemens EDA

The 50th International Test Conference was just held in Washington DC, where papers, sessions, workshops and announcements addressing the increasing complexity and expanding use of semiconductors showed that innovations in test are crucial to design and product success. Test methodologies and even the scope of test have expanded over the lifetime of this event. If test methods had grown linearly with design size and complexity, today’s massive designs would be effectively untestable. At the same time test activity has moved from being a manufacturing step into something necessary throughout the life of the design in many applications.

The one major message here is that the scale and scope of test is expanding, and the industry is working to keep up and track these changes. Evidence of this is provided in announcements by Mentor during the ITC. The first of these deals with Mentor’s Tessent Connect, which provides much needed automation in hooking up hierarchical test elements. The benefits of hierarchical test are well understood. Each core can have test added during design. The result is easier scan insertion, better observability and quicker test pattern generation. Also, top level resources are conserved by applying IJTAG based on IEEE 1687. When there are design iterations, and there always are, only the blocks affected need to have test changes.

The downside is that a lot of manual effort is required to connect each core for the chip level test implementation. Tessent Connect helps automate the process of making these connections. Designers using Tessent Connect work at a higher level of abstraction that focuses on intent rather than the details of stringing together individual wires. This is useful especially when working in cross team environments. To help facilitate its adoption Mentor has also created a quickstart program for Tessent Connect to help with flow assessment and provide implementation services.

The second Mentor announcement at ITC was the introduction of the Tessent Safety ecosystem. They describe it as a comprehensive portfolio of best-in-class automotive IC test solutions from Mentor and links to its industry-leading partners. In applications such as automobiles, test now plays a major role during system operation. This has led to expanded use of Logic BIST, which can be used in chips throughout their life. For instance, ISO 26262 calls for regular and repeated testing of automotive systems during operation to detect failures so corrective action can be taken. These tests must be performed quickly and in such a way as to not interfere with overall system operation.

Mentor’s Tessent Safety ensures that tests are non-destructive to system operation and that tests are run much faster than alternative approaches. One new technology they are using is called Observation Scan Technology (OST), which includes IP that can be inserted selectively to boost observability. This translates into a 10X improvement in performance and helps reduce layout congestion. Mentor is also adding close links to their Austemper SafetyScope and KaleidoScope products.

Mentor is participating in the ARM Functional Safety Partnership Program, leveraging ARM Safety Ready IP, like the Cortex-R52 processor. There are many other aspects to the Tessent Safety ecosystem. A partial list includes analog test capabilities, memory BIST – at RTL or gate level, automotive grade ATPG and transistor level defect simulation. The level of rigor in the Tessent Safety ecosystem comes as no surprise given their long experience with automotive applications and their test expertise. The Tessent Connect and Tessent Safety announcements from this year’s ITC are available on the Mentor website.

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AMAT last to confirm foundry led recovery

AMAT last to confirm foundry led recovery
by Robert Maire on 11-18-2019 at 6:00 am
Categories: Foundries, Semiconductor Advisors, Semiconductor Services, TSMC
2 Comments

Good end to a weak fiscal year- and end to down cycle
As expected and well telegraphed by TSMC, LRCX, ASML & KLAC, AMAT put up a good quarter and guide as the last to report that the industry has turned the corner on the down cycle. While not a rip roaring recovery, its better to return to growth than continue a downward trend.

Results were at the high end of guidance coming in at EPS of $0.80 versus street of $0.76 and revenues of $3.75B versus $3.68B.  More importantly, guidance for the January quarter is for $0.87 to $0.95 on revenues of $4.1B +- $150M.

No surprise here- All driven by TSMC
Its quite clear that the hockey stick like huge uptick in TSMC spending focused on the end of year is the primary reason for AMATs strong outlook.  While Intel has been tepid at best and memory is still dead with display going nowhere, its TSMC that is carrying the entire load of the recovery. Their uptick is so strong it has been able to offset the weakness in other areas.

We would remind investors that Applied has one of the strongest relationships with TSMC of any equipment supplier, having TSMC been called :the house that Applied built”.  It is somewhat funny that whereas in the past relationship TSMC needed Applied to be a force in the chip industry, now the tables are turned and Applied has TSMC to thank for the recovery.

Running on 5 of 8 cylinders
Applied repeated what we have been saying for many months now, that this up cycle will be driven by foundry/logic.  Memory remains virtually dead and display treading water at best.

The question is when do those 3 cylinders- DRAM, NAND & Display start firing again? We certainly agree with Applied by saying its a question of when not if.

On the call the company was very careful, multiple times, not to comment on the shape or size of the recovery. The company also demurred on the question of a potential 2020 recovery of NAND and left out entirely the timing of a DRAM recovery.

Given that capacity has still been coming off line recently in memory it will be a fairly long time before memory spending starts up again.  In our view, its unclear if NAND will recover before the end of 2020.

Who benefits most from a Foundry/Logic recovery?
Given that this up cycle is very much led by foundry/logic with memory stuck in neutral, we think its appropriate to revisit who has the best exposure to foundry/logic of the big 4 semi equipment makers.

We think its clear that KLAC is likely the highest exposure to foundry/logic and historically has been viewed as the anti-memory play.  TSMC is spending a lot of money on process control keeping on their annual improvement cadence and KLA gets the lions share of that.

Applied is likely second in line to foundry/logic exposure with a long history of support of TSMC, but still very dependent upon memory for its business. Applied will see a mild recovery but really needs memory to kick back in.

ASML is likely third as it gets most of its EUV business from TSMC but still relies on DUV and memory as being volume buyers of scanners making up a huge part of purchases and most current profitability.

LRCX is fourth as it has historically been the poster child for the memory industry and saw huge upside from memory’s spending spree in the last up cycles. That said, even Lam is seeing an upturn given TSMC’s huge uptick.

The stocks
We have been positive on the stocks in the semi equipment sector calling for strong upside prior to the quarterly reports and urging investors to get in before Lam was the first to report.

We had also suggested at the time that after the stocks had their run up due to the positive reaction of the turn in the down cycle to an up cycle that we would be inclined to take some money off the table.

We think that post Applied quarter that lightening up may be prudent.

We have seen a strong run up across the board in all the stocks. The stocks are at all time highs in many cases and at all time highs in P/E ratios in most all cases. This is despite the fact that the recovery will be weak and slow with memory still dead.

The market seems to be pricing into the stocks a normal rip roaring semiconductor recovery when in fact we have a half baked, foundry/logic only recovery without any clear sight lines to a full recovery.

We are also concerned that there is not another near term upside for the stocks until they report the current quarter.  Though one could argue that the next upside surprise will be memory recovering but we feel that we are going into the seasonally weak Q1 when memory is at its normal nadir, so a memory recovery is several quarters away at a very minimum.

At this point given that the stocks are priced to perfection in a less than perfect environment we also have the macro risk of China and trade that still hangs over us. The China issue seems to have gotten marginally worse of late as the deal we thought we had now seems more elusive as the intellectual property transfer issues seems less than settled.

Applied has just hit an all time high, jumping almost 10% on well known “news” of a recovery. We have no problem taking some of our profits from the turn in the cycle off the table until we see a better upside/downside risk/reward profile. We think Applied remains a premier company in the space and put up a very good report however the valuation is a bit ahead of reality.

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Synopsys Fusion Compiler Delivers ARM Hercules-Samsung 5LPE Design

Synopsys Fusion Compiler Delivers ARM Hercules-Samsung 5LPE Design
by Daniel Nenni on 11-15-2019 at 10:00 am
Categories: EDA, Events, Synopsys

There were many interesting presentations at ARM TechCon this year besides the keynote addresses by Arm, which were truly stunning for content and production value. One very interesting presentation was the talk given in the afternoon of Wednesday, October 9, 2019, titled, Synopsys Fusion Compiler for Next Generation Arm Hercules Processor Core in Samsung 5nm Technology. The presentation was split into three sections given by Sudhir Koul, Director Engineering SoC Design, Samsung; Leah Schuth, Director, Technical Marketing, Arm; and Dale Lomelino, Sr. Applications Engineer, Synopsys.

Trying to implement a new processor on a new technology node is a substantial challenge. To make that work, a focused collaboration between the teams involved in the process rules, IP design, and EDA tools is mandatory. The first part of the presentations paid much attention to that aspect, the close interaction between the different teams at Samsung, Arm, and Synopsys. If you are going to try to implement this processor on this chip, then you will be receiving support from Samsung and Arm as well. But the support they can provide will have been enhanced, especially if you are using Synopsys tools, by the project discussed in the presentation. So, for the rest of this blog, I will focus on the EDA tools provided by Synopsys, as this is the key variable if you have already chosen the process and core you wish to implement.

The final portion of the presentation discussed the Synopsys implementation, which revolved around the Synopsys Fusion Design Platform, and its key component, the Fusion Compiler RTL-to-GDSII product. Fusion Compiler is a confluence of leading-edge technologies, previously deployed as standalone solutions, being deployed together atop a single, converged data-model – synthesis, place & route, and sign-off tools all together in a singular product. Synopsys is the EDA company with the richest tradition in providing synthesis technology – it was the technology foundation on which the company was initially built. The fusing of synthesis with P&R and sign-off tools on a single data model with a common interleaved optimization framework is what makes Fusion Compiler special.

Clocks have never traditionally featured in the synthesis space; logic optimization is done assuming ideal clocks with zero skew as a target. Arm-core designs – and many others – rely on clock skew to not only enable the high-performance numbers required in datacenter scenarios, but the very architecture demands it to optimize data timing into-and-out-of memory structures – like cache lookups – as part of the data-paths. By having a single data-model that all engines work off, Fusion Compiler can deploy concurrent-clock-and-data (CCD) optimization – traditionally a backend technology – in the early phases of synthesis to create offset or target skews and thus provide the optimization infrastructure with a better view of what is required during logical/physical implementation. Synopsys refers to this as “CCD Everywhere.” This technique implies that the logic and timing information, including clock skew, can be utilized to optimize the design at many different places within the toolchain. The approach more easily allows the use of “useful skew” when trying to meet timing requirements. But, it can also mean that knowledge of useful skew can allow a datapath to be de-prioritized to improve the performance on some other critical path. These are the types of trade-offs you can imagine inside the Fusion Compiler’s common optimization engines.

I do not want to imply that all the benefits in the Fusion Compiler come from the utilization of CCD technology. In the presentation, Synopsys also discussed other advanced technologies, including latency-aware placement (LAP), layer binning, layer promotion, and non-default routing (NDR) technologies.

NDRs are an especially interesting concept where signal nets can be made wider to lower their resistance, thereby improving timing. It effectively gives the layout tools access to an additional logical layer bin to which timing critical paths can be assigned. This concept sounds simple, but automating this feature is not trivial, and for that reason it is an interesting development.

Overall, I think that designers can take comfort from the efforts described in this presentation for two reasons: (a) if you want to implement the Arm Hercules processor in the Samsung 5LPE process, this project generated much information that these companies can share with you in order for you to implement your project efficiently; and (b) implanting any design in the 5LPE process with Synopsys tools should be easier since this project paved the path. Congratulations to Samsung, Arm, and Synopsys for pulling off this collaborative project.

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2020 Semiconductor Foundry Landscape Update!

2020 Semiconductor Foundry Landscape Update!
by Daniel Nenni on 11-15-2019 at 6:00 am
Categories: China, Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, Semiconductor Services, TSMC
5 Comments

When I first started working with the foundries 25 years ago I would have never imagined that I would make a career out of it, which I most certainly have. Fortunately, I recognized early on that not only are the foundries the cornerstone of the semiconductor ecosystem, they are also a very important economic bellwether, absolutely.

When I first started, a fabless company could use four different foundries (TSMC, UMC, SMIC, and Chartered) in a reasonably compatible manner. Generally, TSMC would be first to a process node so everyone started there and moved chips to the cheaper foundries for 2nd, 3rd, and even 4th source manufacturing. This was not really ideal for TSMC as they did all of the heavy process ramp work only to share the more profitable high volume manufacturing with competitors.

This all changed in 2011 at 28nm when TSMC followed Intel using High-k Metal (HKMG) gate-last technology. The other foundries followed Samsung in using a gate-first HKMG 28nm technology which did not yield as expected. TSMC then went on to dominate the 28nm node and has been dominant ever since.

The days of TSMC compatible processes are now long gone with the FinFET era and TSMC continues to lead the semiconductor industry with the first high volume manufacturing EUV FinFET implementation at 7nm, 6nm, and 5nm. TSMC will continue to use FinFET EUV technology at 3nm then move to GAA at 2nm. Samsung is still working on perfecting EUV at 7nm and 5nm before moving to GAA at 3nm. Intel 7nm will be EUV FinFETs but Intel 5nm will be horizontal nanosheets and CFETs for Intel 3nm . It is hard to bet against TSMC but I would not bet against Intel or Samsung either.

Bottom line:  The foundry business is thriving as systems companies do even more of their own chips and continue to push innovation to the limits of the fabless semiconductor ecosystem.

One of the reports I rely on for my foundry expertise is the IC Foundry Almanac published by the GSA in cooperation with IC Insights. The 2020 (12th) Edition is out now and it continues to reinforce my 20+ year belief that the foundries are in fact the cornerstone of the semiconductor industry.

The report itself can be purchased from the GSA Store. I have a copy so if you have questions I may be able to help in the comments section or contact GSA directly. It is definitely worth the price of admission if you really want to know what is happening inside the fabless semiconductor ecosystem. Here is the executive summary:

The importance of wafer foundries continues to grow in the integrated circuit industry. About 43% of worldwide IC sales to systems makers in 2019 were coming from products fabricated by third-party silicon foundry providers compared to 36% in 2014 and 24% in 2009. Foundry-made ICs are expected to account for more than 40% of total integrated circuit sales to systems makers through 2023, according to the 2020 edition of The Foundry Almanac, which is jointly produced by the Global Semiconductor Alliance (GSA) and IC Insights Inc. The 12th annual edition of The Foundry Almanac shows worldwide IC foundry sales increasing by a compound annual growth rate (CAGR) of 6.4% between 2018 and 2023. This foundry growth rate is

higher than the expected 4.8% CAGR for total IC sales in the same forecast period. Currently, pureplay foundry suppliers generate about 81% of total IC foundry sales with the remaining 19% coming from integrated device manufacturers (IDMs) that process wafers for other companies in addition to making their own products in internal fabs.

The first part of this report contains an overview of the semiconductor foundry segment, forecasts, and analysis of trends by IC Insights. Following the market forecast section, the GSA presents a summary of foundry wafer pricing trends and photomask costs based on industry survey results. This report also contains a listing of foundry-supplier information compiled by the GSA.

Among the key conclusions and highlights in The 2020 IC Foundry Almanac are:

  • Total IC foundry sales (by both pure-play foundries and IDMs) are estimated to declined 2% in 2019 to $69.6 billion after increasing 5% to reach a record-high $72.6 billion in 2018. The last time IC foundry sales dropped was in 2009, when the semiconductor industry was hit by a downturn year after the financial crisis in 2008 triggered a deep global recession. In 2019, foundry sales slid lower because of growing concerns about an economic slump, which cause system makers to reduce IC purchases, and by slower growth in China that was partly a result of its trade war with the U.S.
  • Foundry growth is expected to return in 2020 with total sales rising 6% and setting a new alltime high of $73.6 billion. Total foundry sales (by both pure-play and IDM suppliers) are forecast to grow 8% in 2021 and strengthen in the next two years to reach $96.6 billion in 2023.
  • Pure-play foundry sales in 2020 are projected to grow 8% to a record-high $60.8 billion after falling 2% in 2019 and rising 5% in 2018. Pure-play foundry sales are expected to grow by a CAGR of 7.0% between 2018 and 2023 to reach $81.2 billion, driven by strong demand from fabless IC companies, increased outsourcing by IDMs, and shipments of custom-designed integrated circuits to systems houses, such as Apple in the U.S. and Huawei in China.
  • Foundry revenues generated by IDMs making ICs for other companies are forecast to drop 2% in 2020 to $12.8 billion after declining about 2% in 2019 and growing 3% in 2018. IDM foundry sales are projected to rise by a CAGR of 3.1% in the 2018-2023 period to reach $15.4 billion in the final year of the forecast.
  • Wafer-fab process technology with minimum feature sizes below 40nm generated about 47% of pure-play foundry sales in 2019 (estimated at $26.8 billion). Process technology with minimum feature sizes of 40nm or greater accounted for 53% of total pure-play foundry revenue in 2019 (estimated at $29.7 billion). Pure-play foundry sales for ICs made with <40nm technology increased 5% in 2019, while revenue for devices made with ≥40nm processes declined by 8% in the year.
  • Capital expenditures by IC foundries (both pure-play and IDM suppliers) grew 7% in 2019 to an estimated $23.9 billion after falling 15% in 2018 from a record-high $26.4 billion in 2017. Foundry capex in 2019 is estimated to be the second highest level of spending in a year. In 2020, foundry capital spending is expected to show a modest 4-5% increase with some major pure-play foundry suppliers remaining cautious and keeping their capex flat in the year.
  • Foundry wafer-fab utilization rates slid lower in 2019 because of a slowdown in IC purchases due to increasing uncertainty about global economic growth in the year ahead. Fab-capacity utilization at the four largest pure-play IC foundries (TSMC, GlobalFoundries, UMC, and SMIC) collectively stood at an average of 82% in 2019, down from 89% in 2018 and 90% between 2015 and 2017. In 2019, the “Big 4” pure-play foundries increased their combined installed fab capacity by 4% to nearly 49.3 million 200mm equivalent wafers compared to about 47.6 million wafers in 2018.
  • Fabless customers are estimated to account for 66% of pure-play foundry revenue in 2019 with IDMs representing 15% and systems makers being 19% of total sales. In 2010, the sales split was 76% to fabless customers, 23% to IDMs, and just 1% to systems manufacturers. The share of systems makers directly buying foundry-made ICs has climbed with Apple using Samsung and TSMC to fabrication of its custom-designed processors in iPhones, iPads, and other products as well as some Chinese smartphone and end-equipment makers—like telecom giant Huawei—developing integrated circuits that are made by foundries.
  • Communications ICs represented an estimated 57% of total pure-play foundry sales in 2019, followed by 17% for “other” ICs (for such applications as automotive, industrial, and medical systems), 14% for computer ICs, and 12% for consumer-product ICs.
  • Customers based in the Americas accounted for 56% of estimated pure-play foundry sales in 2019, followed by those headquartered in the Asia-Pacific region at 32%, Europe at 6%, and Japan at 5% of the total. China’s share of the pure-play foundry market in 2019 is estimated at about 18%, which is four percentage points greater than the marketshare of customers in the rest of the Asia-Pacific region in the year.
  • Two Chinese chipmakers (SMIC and Huahong Group) are ranked among the top 10 IC foundries in 2019, based on dollar-sales estimates. In total, Chinese manufacturers accounted for an estimated 9.4% of worldwide pure-play foundry sales in 2019, down slightly from 9.6% in 2018. The marketshare of China’s pure-play foundries remains below the peak of 13.3% recorded in 2006 and 2007. Mainland Chinese companies in the pure-play foundry business are expected to have a marketshare of 10.3% in 2023.
  • Two IDMs (Samsung and Fujitsu) are among the top 13 IC foundry suppliers in 2019. The rest are pure-play foundries. Fujitsu is expected to fall out of the top ranking of foundries in 2020 after it sold the remaining majority interest in its 300mm fab in Japan to Taiwan-based UMC in the summer of 2019.
  • Worldwide IC foundry production capacity (at both pure-play and IDM foundries) grew by about 5% in 2019 to an estimated 80.4 million wafers (measured in 200mm equivalents). Pure-play foundry annual capacity grew by an estimated 5% to about 63.8 million wafers in 2019, while IDM foundry capacity increased 4% to an estimated 16.6 million 200mm-equivalent wafers in the year. The “Big 4” pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) accounted for an estimated 61% of total IC foundry capacity in 2019. Total foundry capacity (at both pureplay suppliers and IDMs) is forecast to rise 4% in 2020 to about 84.0 million 200mm-equivalent wafers, followed by another 4% increase in 2021 to 87.7 million in that year.
  • Overall, 200mm wafer fabrication pricing gradually increased from the second quarter of 2018 continuing through the second quarter of 2019 resulting in a 10% increase YoY. Furthermore, 300mm wafer fabrication pricing was relatively stable during the same period with a 2% decrease YoY. This reflects the stable demand for devices at older technology nodes using 200mm size wafers compared to newer technology nodes using 300mm wafers affected by the global slowdown.
  • GSA’s Wafer Fabrication Pricing Survey results show that participants still rely on older process nodes to maintain market share, as 49% of the capacity needs are at or above the 130nm node. Participants are also reporting an increase in demand for capacity at nodes below 50nm with 33% of participants needing capacity at these nodes compared to 24% last year.
  • 200mm mask costs per layer remained flat throughout 2018. 300mm mask costs per layer, driven by the 28nm node, increased throughout 2018, continuing through the second quarter of 2019. This could be driven by the increase in complexity of the designs run on 300mm wafers.
  • With the downturn in 2019, wafer fabrication capacity became more available, which was reflected by the outlook of GSA survey participants. 82% of GSA’s 200mm wafer fabrication survey participants and 70% of 300mm wafer fabrication survey participants are forecasting that wafer fabrication pricing will be trending lower in the next 6 months.
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SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!

SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!
by Swamy Irrinki on 11-14-2019 at 2:00 pm
Categories: IP, RISC-V, SiFive

We’re confirming seats in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga for the South American leg of our worldwide 2019 SiFive Tech Symposiums and Workshops. These five events will be focused heavily on academia, which is a key focus for SiFive. In fact, we are co-hosting these events with many of the most prestigious universities including the Polytechnic Schools of São Paulo (Poli-USP), the Federal University of Rio

Grande do Sul (UFRGS), the Universidad Católica del Uruguay (UCU), the University of Bueno Aires (UBA), the Universidad Industrial de Santander (UIS), and the Integrated Systems Research Group Onchip at Universidad Industrial de Santander. Our partners include Centro Interdisciplinar em Tecnologias Interativas (CITI-USP), the Department of Electronic Systems Engineering at the Polytechnic School of the University of São Paulo (PSI-EPUSP), and IEEE Uruguay and Colombia Section. We are very proud to have many renowned professors and researchers on the schedule to present.

All of the SiFive Tech Symposiums have been significantly instrumental in engaging the hardware community in the RISC-V ecosystem, and spearheading the emergence of new applications. We are constantly in awe of the brilliant minds that convene at these events. We thrive on watching intense conversations and the sharing of ideas between those already entrenched in RISC-V and others who still learning and exploring.

In addition to presentations by industry veterans and academic luminaries, there will presentations by the SiFive team on RISC-V developments tools, platforms, core IP and SoC IP.

Each event will feature a hands-on workshop that offers attendees the unique opportunity to configure their own RISC-V core and bring up on an FPGA.

Attendance is free, but registration is required.

Monday, November 18, 2019 View Agenda &amp; Register to Attend São Paulo, Brazil Polytechnic School of the University of São Paulo (Poli-USP)

Tuesday, November 19, 2019 View Agenda &amp; Register to Attend Porto Alegre, Brazil Federal University of Rio Grande do Sul (UFRGS)

Thursday, November 21, 2019 View Agenda &amp; Register to Attend Montevideo, Uruguay Universidad Católica del Uruguay (UCU)

Friday, November 22, 2019 View Agenda &amp; Register to Attend Buenos Aires, Argentina University of Buenos Aires (UBA)

Monday, November 25, 2019 View Agenda &amp; Register to Attend Bucaramanga, Colombia Universidad Industrial de Santander (UIS)

We look forward to seeing you!

About SiFive
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.