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Evolving Landscape of Self-Driving Safety Standards

Evolving Landscape of Self-Driving Safety Standards
by Bernard Murphy on 11-14-2019 at 5:00 am
Categories: AI, Arteris, Automotive, IP
1 Comment

Autonomous Vehicle

I sat in a couple of panels at Arm TechCon this year, the first on how safety is evolving for platform-based architectures with a mix of safety-aware IP and the second on lessons learned in safety and particularly how the industry and standards are adapting to the larger challenges in self-driving, which obviously extend beyond the pure functional safety intent of ISO 26262. Here I want to get into some detail on this range of standards because we’re going to need to understand a lot more about these if we want to be serious about autonomous cars.

Let’s start with some evolving requirements for functional safety, the topic covered by ISO 26262. The standard itself doesn’t specify what safety mechanisms should be used but it does require (in ISO 26262-2) that you need to deliver credible evidence that the safety mechanisms you provide are sufficient. This is a neat little twist – the burden is on you (and your customers and suppliers) to demonstrate functional safety no matter how complex your design may become.

And they are becoming a lot more complex. We now have designs in safety-critical systems (ASIL-D) in which not all IP components individually meet that expectation and cannot reasonably be expected to be brought up to that level. How can a system be at ASIL-D if parts of it are at lower ASIL levels, or even may be safety indifferent (QM)? The answer lies in being able to isolate and test those components regularly and if they fail to meet expectations, leave them isolated. This has also led to the concept of a fully ASIL-D safety-island which can initiate such testing and report problems back to command-central in the car, to be able to support fail-operational responses.

Another mechanism in this diagnostic framework is detecting errors through timeouts from requests to acknowledgement on the bus. Pretty reasonable that this would be a good method to look for misbehaving components. ISO 26262-2 defines a fault handling time interval, usually well within time to detect fault, but of course does not specify how this should be accomplished, just as it doesn’t specify the isolation and safety island mechanisms. These are design responses to the documented requirements.

Arteris IP FlexNoC Reliance supports all of these capabilities. DreamChip talked in an earlier panel about using Arteris IP NoC technology both to build a safety island, to provide the network between IPs naturally,  and to manage IP isolation and independent testing on that network. They also program and test timeouts for request/response per IP through their NoC safety features

So far this is purely functional safety. Safety Of The Intended Function (SOTIF), also know as ISO/PAS 21448, is a follow-on to 26262 with the goal of defining safety at the system level – think about software and ML certainly but also misuse or environmental factors. Safety concerns here are not necessarily determined by system failures; they could be determined by scenarios which weren’t considered in the design of the autonomous driving systems. A simple example might be driving on an icy road; SOTIF requires that these kinds of conditions be included threat modeling and risk mitigation.

SOTIF is certainly a start in the right direction, though Kurt Shuler’s feeling is that it is currently rather too philosophical to be actionable in engineering design and validation practices (Kurt is VP Mktg at Arteris IP). We’ll see how his view evolves in follow-on releases.

Another very interesting standard, sponsored by Underwriter’s Labs (UL) is UL 4600. What he likes about this is that it defines a standard of care for the design of an autonomous vehicle. This must be presented as very methodical documentation of:

  • Why the developer thinks the vehicle is safe
  • Why we should believe their argument
  • A list of #DidYouThinkOfThat? Cases which allow incorporating lessons learned

This isn’t a metric and doesn’t set absolute standards for what should be considered safe or what kind of tests should be run, but it does insist on a comprehensive list of safety cases with goals and claims which must be demonstrated to be supported by evidence. And a list of possible exceptions/cases not tested must be included (and can evolve). This is at minimum very auditable. I certainly think this is an important step.

These are the main standards Kurt thinks are important today for autonomous driving. Progress is being made though there’s still a lot of work to be done to more exactly determine how we should define safety in autonomous vehicles, much less how we should implement safety. But we’re advancing.

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Functional Safety Comes to EDA and IP

Functional Safety Comes to EDA and IP
by Daniel Payne on 11-13-2019 at 10:00 am
Categories: Accellera, Semiconductor Services

Every week I read headlines about the progress of autonomous vehicles, and the inevitable questions began to arise, like, “Just how safe is this AV?”, or “Is this new ADAS feature trustworthy?” The automotive industry has already setup the ISO 26262 functional safety standard, and we’ve blogged about that topic quite a bit on SemiWiki.  EDA vendors have begun to receive third party ISO 26262 qualification of their point tools, so that’s a reassuring step.

Our EDA industry has delivered RTL language standards over the years and Accellera is always at the center of these efforts, so the good news is that a standardization initiative was just announced for a Proposed Working Group (PWG) that addresses functional safety for EDA and IP.  They will be looking at how Failure Modes, Effect and Diagnostic Analysis (FMEDA) is applied to functional safety using EDA tool and semiconductor IP blocks.

Accellera issued a press release recently with quotes from Lu Dai the Chair of Accellera, and Martin Barnasconi the Technical Committee Chair. Any EDA or IP provider that is offering tools, IP and services to functional safety markets like automotive should consider attending the first meeting of this PWG, scheduled for December 6th in Germany at the NXP Semiconductor office, Schatzbogen 7, 81829 Munich.

You’ll need to first register for this event online here. To learn more about what this Functional Safety PWG is all about, read this. There are some 14 active working groups with members representing many leading companies, like: NXP, Intel, AMD, Mentor, Synopsys, Bosch-Sensortec, Maxim, NVIDIA and Xilinx.

If your expertise includes functional safety but your company isn’t part of Accellera, you can still participate in this new PWG, so why not be part of something that contributes to standardization. Instead of multiple EDA and IP vendors trying to forge independent routes to functional safety, it kind of makes sense to share best practices and even move towards interoperability.

Related Blogs

Background on Functional Safety Proposed Working Group
There is significant activity ongoing in the EDA community to enable functional safety as a part of the design and verification flow. There have been various discussions on the need for a standardized language or format to specify functional safety information and enable tool interoperability. The objective of the PWG is to explore the need for a unified approach to enable a functional safety solution.

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence; Mentor, A Siemens Business; and Synopsys.

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Package Reliability Issues Cost Money

Package Reliability Issues Cost Money
by Tom Dillinger on 11-13-2019 at 6:00 am
Categories: Ansys, Inc., EDA

Advanced packaging technology is enabling “More Than Moore” scaling of heterogeneous technology die.  At the recent EDPS Symposium in Milpitas, Craig Hillman, Director of Product Development, DfR Solutions, at ANSYS gave a compelling presentation, “Reliability Challenges in Advanced Packaging”.  The key takeaway messages from his talk were:

    • Package reliability analysis is often not considered during (initial) product development – “It does not always have a seat at the table.”, in Craig’s words.
    • Package reliability issues uncovered during product qualification cost BIG money. (more on that shortly)

Further, the rapid adoption of 2.5D and 3D heterogeneous packaging and the corresponding end target applications have exacerbated these issues.  These issues are more pronounced due to a combination of new materials, plus the extended thermal environments and required lifetimes of emerging markets.

Specifically, Craig highlighted two failure mechanisms that merit detailed modeling and simulation – dielectric cracking/delamination within the die, and fatigue/failure of the solder connections from die to package and package to PCB.

  • Low-K Dielectric Failure

For several process nodes, the interlevel dielectrics (ILD) between back-end-of-line (BEOL) metal layers have been utilizing a “low k” material (k being the standard nomenclature for the relative dielectric constant).

These dielectric materials typically utilize plasma-enhanced chemical vapor deposition of an organosilicate glass (OSG) or spin-coating of silicon glass in a gel-based solvent.  This dielectric is then etched to create the vias and metal trenches for the damascene copper metal deposition.  More recently, extreme low-k (ELK) and ultra low-k (ULK) materials have been incorporated into BEOL process modules.

The porosity of these ELK and ULK dielectrics is greater.  Correspondingly, the strain energy release rate is less.  In other words, these brittle materials are more prone to catastrophic cracking due to applied stress.  Fracture mechanics of materials includes both adhesive and cohesive analysis – adhesive is related to disparate material interfaces and cohesive is related to a fracture within the material itself.  Craig presented data indicating a greater susceptibility for cohesive ELK/ULK cracking within the dielectric layer, as illustrated below.

The figure below highlights an additional factor in the susceptibility of these new ILD materials to fracture.  The technology for die attach is transitioning from (lead-free) solder bumps to copper pillars, to provide tighter pad pitch and greater current density.  However, copper has a higher modulus of rigidity than solder.

As the package is subjected to thermal events, the Cu pillar transfers more mechanical stress into the ILD materials in the die than would a solder attach metallurgy.  As illustrated in the figure above, the interaction between (flip-chip) die, Cu pillar, underfill, and package substrate results in a complex combination of compressive and tensile forces on the ILD dielectric layers at the die edge, due to differences in the coefficient of thermal expansion (CTE).

Craig mentioned two additional mechanisms of interest related to dielectric fractures.

residual and applied stress

The fabrication and attach processes themselves likely result in some degree of residual stress in the ILD materials.  The thermal cycling of the part is thus an interaction between this initial material stress and the thermally-generated applied stress described above.  “The existing JEDEC qualification standards for thermal cycling (and temperature rate of change) may not necessarily be the worst case stress extremes.”, Craig indicated.  “There are potentially ranges other than -40C to 125/150C that would be preferable.  If the initial residual stress relaxes at high temperature, that could counteract the applied stress from material CTE differences.  Maybe -40C to <<125C would result in greater effective stress on the dielectrics.”

propagation of initial dielectric cracks

The probability and rate at which an ILD fracture results in a failure is increased significantly in the presence of an initial crack at the die edge, such as could arise during the process steps for individual die singulation from the wafer.  The figure below illustrates a cross-sectional finite-element mesh model for the die, top-surface overcoat, and package attach underfill materials with an initial crack present.

Craig expanded further upon these issues, “In addition to the ELK/ULK materials transition, packaging technology has also been evaluating new underfill materials.  The goal would be to utilize a material whose rigidity is less at high temperatures, to reduce the stress on the ILD.  Yet, these polymers have an intricate modulus of rigidity and CTE relation as a function of temperature that could aggravate rather than reduce the applied stress.  To further complicate the analysis, the Cu pillar and solder bump materials are subject to “work hardening”, where plasticity may reduce over time, due to repeated (limited) deformation occurring during thermal cycles.”

 

What has been the industry cost of reliability failures due to ELK/ULK cracking?

“Easily in the billions of dollars.”, Craig noted.  “At ANSYS, we’ve recently had 9 companies approach us seeking a simulation analysis solution to ILD cracking issues.”

How can the risk of ELK fracture be reduced?

Craig indicated, “There are (foundry and OSAT) design rules that are intended to mitigate the risk.  For example, the Cu pillar and top-level pad dimensions and spacing attempt to balance the desire for a high I/O density with the stresses transferred to the ILD layers.  Adhering to metal density/uniformity requirements on top-level interconnects, especially under the pad metal is also key.  And, the foundry will provide stringent guidelines for the (minimum) number of metal layers of different thicknesses in the overall interconnect stack – the process module for each metal layer has corresponding ILD features.  The number and location of low-k, ELK/ULK transitions in the stack is a crucial design consideration.  Yet, even with these design guidelines, the best solution to ELK/ULK reliability analysis is a thorough thermal-mechanical simulation of the material stackup, using a platform such as ANSYS Multiphysics.”

  • solder fatigue

Craig also briefly reviewed another, more well-known, reliability issue, related to the fracture of solder joint connections between the package and the board.  “Existing models of the strain applied to the solder joint are proving to be inadequate – companies are reporting a greater and earlier failure rate than predicted.”, Craig indicated.

“The classical 2D, planar approach to the analysis of CTE mismatch between package and board needs to be expanded.  Boards are subject to their own stresses, from the (dual-sided) component placement to the mechanical attachment to the product housing.  A tri-axial 3D application of stresses to solder joints is required for fatigue analysis.”  The figure below illustrates the contribution to solder joint stress from board deformation.

 “Again, extensive simulation modeling and analysis is required of this thermal-mechanical system, even down to the torque applied to the screws that attach the boards to the standoffs in the housing.”  The figure below shows an ANSYS simulation result – the color index on the board illustrates the degree of (Z-axis) deformation, while the table illustrates simulated versus measured solder joint fracture data in terms of allowed thermal cycles.

Craig concluded his presentation with the following commitment, “ANSYS is extending its Multiphysics scripting and material property modeling features to enable simulation of all artifacts that contribute to these package reliability failure modes.”  That was encouraging to hear – deferring reliability analysis to product qualification is increasingly a significant financial risk.

Here’s a link to Craig’s EDPS presentation slides – link.

Here’s a link to more information on ANSYS Multiphysics – link.

-chipguy

 

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A No-Fudge ML Architecture for Arm

A No-Fudge ML Architecture for Arm
by Bernard Murphy on 11-12-2019 at 5:00 am
Categories: AI, Arm, IP
4 Comments

Ethos applications

At TechCon I had a 1×1 with Steve Roddy, VP of product marketing in the Machine Learning (ML) Group at Arm. I wanted to learn more about their ML direction since I previously felt that, amid a sea of special ML architectures from everyone else, they were somewhat fudging their position in this space. What I heard earlier was that the vast majority of ML functions are still being run on standard smartphones. Since there are (or were?) vastly more of these than any other devices, that meant they already dominated ML usage. Which is true, but that’s not really a direct contribution to ML (same platform, different software) and it’s not where ML is headed.

In fairness I wasn’t considering Mali. GPUs are already prominent in ML (clearly evidenced by NVIDIA offerings). The high levels of parallelism on GPUs enable much faster neural net (NN) processing than on a traditional CPU. Still, the key metric for a lot of ML hardware, TOPS/W, is pushing for more specialized accelerators designed specifically for NN algorithms.

Arm didn’t have an entry in this field until they introduced their Ethos family, heralded earlier this year by the Ethos-N77 for premium applications. At TechCon they also announced Ethos-N57 for balanced performance and power and Ethos-N37 for performance in the smallest area. They see the N77 having applications in computational photography, top-end smartphones and AR/VR. N57 is for smart home hubs and midrange smartphones. The N37 is for DTVs (and I would imagine home appliances), entry-level phones and security cameras.

The architecture shows that this isn’t a bunch of MACs bolted onto a Cortex engine or even a respin of Mali. Arm details this as 4 primary functions around a bunch of SRAM (varying amounts depending on the core you use). The first function is a MAC engine supporting weight decompression and built in support to reduce multiplications in convolution by more than a factor of 2 (using the Winograd algorithm, in case you wanted to know). The second is a programmable layer engine. I couldn’t find a lot of detail on this but I think I get the concept. Networks are evolving fast, so hard-coded layers and layer types are not good; you need to be able to adapt the network in software without losing the performance advantages of the hardware. So you need configurability in convolution layers, pooling layers, activation models, etc.

The third function is a network control unit to manage traffic and control of all the other functions and the fourth is a DMA. In any other system this might be a ho-hum kind of block but in machine learning, this is central to performance and power efficiency. Vast amounts of data flow around these systems – images and weights in particular. AI accelerators live or die based on how effectively they can manage memory accesses on-chip to the greatest extent possible, without needing to go off-chip. The DMA controller, together with compression and other techniques ensures that 90% of accesses can be kept local.

Unsurprisingly Arm offer extensive software ecosystem support and libraries. They also offer support for a concept that is becoming increasingly popular in this domain – the ability to target such solutions starting from one of the mainstream NN networks across a broad range of platforms – Cortex, DynamIQ, NEOVERSE, Mali, Ethos and even 3rd-party platforms (DSPs, FPGAs and accelerators) – with suitable optimizations to take best advantage of the target platform.

I still buy that a lot of ML applications will continue to run on traditional Cortex platforms, but now I really believe Arm has an end-to-end IP story including real NN cores. You can learn more about the Ethos solutions HERE.

 

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Is the ASIC Business Dead?

Is the ASIC Business Dead?
by Daniel Nenni on 11-11-2019 at 10:00 am
Categories: Semiconductor Services
16 Comments

We covered the ASIC business in Chapter 2 of our book “Fabless: The Transformation of the Semiconductor Industry” using VLSI Technology and eSilicon as shining examples. Neither of which now exist. The ASIC business model was a critical steppingstone in the transformation of the semiconductor industry. Many systems companies started with ASICs only to become fabless systems companies who now dominate their market segments.

Apple for example. In fact Apple started with eSilicon for ASICs before moving to Samsung and finally acquiring and building teams internally. The SoC inside the Apple iProducts is second to none, absolutely, and it all started with eSilicon.

Inphi and Synopsys acquired eSilicon, it was formally announced today. The rumor had been swirling for weeks but the final bidder was yet to be determined.

Inphi to Acquire eSilicon, a Leading Provider of 2.5D Packaging, SerDes and Custom Silicon
SANTA CLARA, Calif., Nov. 11, 2019 (GLOBE NEWSWIRE) — Inphi Corporation (NYSE: IPHI), a leading provider of high-speed data movement interconnects, today announced that it has signed a definitive agreement to acquire eSilicon for $216 million in both cash and the assumption of debt.

“I am delighted with these transactions from Inphi and Synopsys, two extraordinary companies in their markets. Our engineering talent, IP and customer relationships in networking, data-center and cloud, telecom 5G infrastructure and AI will help enhance their respective offerings,” said Jack Harding, president and CEO of eSilicon. “I thank all our customers, employees, partners and investors for the unwavering support and commitment they have provided eSilicon over the years.”

“The Inphi team is excited to enhance our value proposition to our cloud and telecom customers with the addition of the eSilicon team and IP,” said Ford Tamer, president and CEO of Inphi. “eSilicon adds to Inphi world-class 2.5D packaging, SerDes, custom silicon and operations teams. Just as we successfully leveraged our Cortina and Clariphy acquisitions, eSilicon will advance our shared commitments in driving successful customer engagement, industry-leading innovation, and best of class execution.”

Synopsys to Acquire Certain IP Assets from eSilicon

Acquisition Will Expand DesignWare IP Portfolio and Add a Team of Experienced R&D Engineers to Serve Growing AI and Cloud Markets

“Today’s complex SoCs require a broad range of IP to address stringent performance, power and area requirements of advanced applications such as AI and cloud computing,” said Joachim Kunkel, general manager of the Solutions Group at Synopsys. “The acquisition of eSilicon’s IP will expand our portfolio and enable us to meet our customers’ need for high-quality IP across advanced FinFET process technologies from a single trusted supplier with common licensing terms and support infrastructure.”

The transaction, which is expected to close during Synopsys’ first quarter of fiscal 2020, is not material to Synopsys’ financials and is subject to Vietnamese regulatory approval and customary closing conditions. Terms are not being disclosed.

In other ASIC déjà vu moments, the once dominant IBM ASIC business (acquired by GlobalFoundries) was spun out and sold to Marvell in May of 2019:

“Our acquisition of Avera enables us to offer the complete spectrum of product architectures spanning standard, semi-custom to full ASIC solutions,” said Matt Murphy, president and CEO of Marvell.  “With their highly experienced design team and Marvell’s leading technology platform, we will be better positioned to capitalize on our expanding opportunity in wired and wireless infrastructure, starting immediately in the fast growing 5G base station market.  In addition, we are looking forward to furthering our successful partnership with GLOBALFOUNDRIES in the coming years and beyond.”

“This transaction is another example of our commitment to focus on our core business of providing differentiated foundry offerings as a manufacturing service provider, while establishing deeper relationships with customers who are leaders in their respective sectors,” said Tom Caulfield, CEO at GLOBALFOUNDRIES.  “With this deal and our growing strategic partnership with Marvell, we will forge new opportunities for the teams of both companies to leverage GF’s broad set of offerings to capitalize on the 5G infrastructure market as well as other opportunities.  We look forward to becoming a strategic provider for Marvell for decades to come.”

Under the terms of the agreement, Marvell will pay GLOBALFOUNDRIES $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months.  The transaction is expected to close by the end of Marvell’s fiscal year 2020 pending receipt of regulatory approvals and other customary closing conditions.

The “certain business conditions” mentioned above is a deal with Hauwei that is still in limbo.

And the ever popular Open-Silicon was acquired by SiFive in a somewhat secretive $60m 2018 transaction. Naveed Sherwani, co-founder and board member of Open-Silicon was appointed CEO of fabless chip company SiFive in 2017 and the rest as they say is history in the making.

There are dozens of services companies doing ASICs and it has never been easier for a systems company to do their own SoC with the mature EDA, IP, and Foundry businesses. And the semiconductor talent pool has never been deeper.

So the question is: Is the traditional ASIC business model dead?

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WEBINAR: Which ASIC Manufacturing Method is Right for You?

WEBINAR: Which ASIC Manufacturing Method is Right for You?
by Daniel Nenni on 11-11-2019 at 6:00 am
Categories: Delta, Events, Semiconductor Services

Minimizing ASIC production costs is the goal of every company. The problem is that this requires extensive knowledge. You must understand the technical intricacies and the financial implications of multiple activities like wafer production, packaging and QA activities such as electrical tests.

Generally, the more your company is involved in production activities, the lower your costs. However, taking full ownership over production is not always possible, nor financially wise. Which brings us to our next webinar in the SemiWiki Series:

Webinar: Choose the Right ASIC Manufacturing Model for Your Business

ASIC production is a part-science, part-art discipline which requires extensive knowledge. The many available options, which combine various 3rd party services and internal resources, require an understanding of the technical intricacies, the pros and cons, and the financial implications of each option. The more knowledge you have, the cheaper ASIC production can be for your company.

This webinar examines three common business models for hardware implementation including IC production and the financial impact of each. Using a real-life project case, it then identifies production volume break even points, distinguishing where one production model has an obvious financial benefit over another.

This webinar is in partnership with DELTA Microelectronics:

DELTA Microelectronics is a European company. We offer services ranging from design (front and back end), development of test solutions, production testing of components, wafer probing, failure analysis and logistics for the supply of components including purchasing of wafers and packaging. We allow the customer to get the most cost effective combination of services.

History
DELTA has been supporting microelectronics development since 1976, providing services to hundreds of successful integrated circuit projects for some of the world’s best-known OEMs/IDMs and fabless semiconductor suppliers. We are a business unit of DELTA Danish Electronics, Light & Acoustics that was established in 1941. DELTA Microelectronics is headquartered in Hørsholm, Denmark, and has an office in South Wales, UK.

Partners and in-house capabilities
A range of European and Far Eastern wafer and packaging partners enable DELTA to provide a full supply chain solution. DELTA has a large semiconductor test department where we can test wafers and components. Our test engineers ensure that the test hardware and software are customised to your chip. DELTA’s experienced ASIC design team is specialised in very low power chips, payment systems, RFID designs, sensor interfaces and optical chips.

ASIC Design Services
The lowest risk path to success.The advantages of ASICs and highly integrated system-on-chip solutions in terms of cost reduction and increase in performance can be , and we believe DELTA’s unique design-to-production flow offers you the lowest risk path to success. We start with an extremely rigorous specification process. During the design phase itself, we use our extensive library of proven circuit IP to speed up projects, and build detailed design review and verification steps into all our designs – at specification, net list, layout and sample stages.

ASIC manufacturing services
Our turnkey ASIC manufacturing services cover the complete cycle – from wafer procurement through packaging, assembly, test, qualification, supply chain management and failure analysis – or can handle a specific phase, based on your needs. We take pride in our high standards and total quality control that help our customers maximise yield and minimise risk of flawed components. With more than 30 years of supporting IC manufacturing, we have developed formal test procedures and quality management methodologies that assure our clients of the rigorous process their products receive. Our facilities are ISO 9001 certified for microelectronics design since 1999.

I hope to see you there!

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Google Gaining ADAS Ground

Google Gaining ADAS Ground
by Roger C. Lanctot on 11-10-2019 at 6:00 am
Categories: Automotive
1 Comment

Google’s Head of Android Auto Partnerships, Jens Bussman, joined me on stage last week in Munich at TU-Auto Europe to discuss Google’s progress and priorities in the global connected car market. The standing-room-only audience was treated to an overview of Google’s plans and some clarifications regarding its different assets being adopted across the industry.

Bussman, first of all, made clear that Google’s top priority was the ongoing proliferation of its Android Auto smartphone mirroring solution. This focus on Android Auto might have seemed surprising given recent announcements of imminent OEM adoption of Google Automotive Services (GAS) by Volvo Cars, Renault and General Motors. But Android Auto is where most of the current action lies for Google.

Bussman claimed a 98% adoption rate for Android Auto (for car companies and new cars shipped outside China, where Android Auto is not available). Given the fact that only BMW, Porsche, Lexus, and Infiniti have yet to adopt Android Auto, that 98% figure might be a smidgeon high. Of course, the figure is a moving target – moving toward 100% – as BMW (speaking later at the event) acknowledged its plans to eventually offer Android Auto and Nissan’s Infiniti has announced its own plans to make both Android Auto and CarPlay standard on its next generation infotainment systems shipping in 2020.

Android Auto has emerged as a convenient entry point for new connected car apps looking for the broadest possible multiple-OEM implementation. Bussman did acknowledge, though, that the growing roster of applications within Android Auto may ultimately pose a usability challenge.

Bussman noted that adoption of the Android operating system is Google’s second priority in the automotive industry. About a decade in to the process of introducing Android into in-dash infotainment systems, Android version Q now addresses a wide range of automotive usability issues ranging from multiple screens and hardware controllers to memory and power management.

Google has listened carefully to and collaborated closely with car makers and Tier 1 suppliers to overcome the operating system’s inherent shortcomings for automotive implementation. Bussman and I discussed the crowd-sourced approach associated with Linux versus Google’s more vertically-oriented and orchestrated modifications which tend to follow a regular annual cadence of updates.

Strategy Analytics anticipates a massive industry shift to Android OS adoption in infotainment systems that is now underway – as the industry shifts from Linux – now at its peak – to Android. Bussman acknowledged that Google has no plans to promote the use of Android for safety related systems, a proposition currently being explored by Linux proponents.

The shift in adoption momentum from Linux to Android reflects the gravitational pull of the massive and growing Android developer community and the growing perception of Android as a lower cost development option. It is the evolving cost advantage that is expected to win the day, OEMs say.

Perhaps most notable of all was Google’s third priority attributed to Google Automotive Services – the full portfolio of Google Services including Google Assistant, Google Maps, Google Places, and Search. Some industry observers see Google’s introduction of GAS into vehicle dashboards as the final straw via which Google takes control of OEM customers and their vehicle buying and usage decisions.

Bussman dispelled the notion that the implementation of GAS would represent a Google take over – in fact emphasizing the fact that Google is not in the user interface business per se and that car makers are free to create their own user interfaces. This is in contrast, of course, with Android Auto which has its own specific interface.

Further, although a deployment of GAS in a vehicle likely requires opening up in-vehicle application programming interfaces (API’s) for accessing vehicle functions, Google will provide various consent management elements intended to preserve driver privacy and data protection. Bussman insisted that Google GAS was not a vehicle data Trojan horse.

Other points of clarification from Bussman included the fact that Google Assistant is only intended for use with GAS, and that GAS has a standard license fee that is not contingent on the amount of data shared with Google by an OEM.  Bussman’s description of GAS implementations suggested that OE’s would preserve their platform development and deployment responsibility – suggesting that Google will have a Tier 2 role – but it is hard to see Google as a Tier 2 supplier.

One thing appears clear is that Google has formally emerged as an automotive Tier 1, coordinating and integrating in-vehicle content. Given the fact that Google is only supporting its operating system and platform for four years vs. the much longer periods of time normally insisted on by auto makers, it is likely that Google will not be displacing the current supplier eco-system which is more accustomed to accommodating standard auto industry practices.

The bottom line is that the proliferation of car connectivity has created a warm welcoming environment for Google, Android Auto, Android, and GAS. With software and services that require connectivity for regular updates and access to resources, Google may be the chief beneficiary of the connected car.

FOG – Fear of Google – remains a pervasive industry mood. But Bussman did his best to dispel the boogie-man reputation of the Mountainview Monster. Post-discussion conversations with TU-Auto Europe attendees suggests that a lingering sense of forboding remains.

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The New SemiWiki Job Board!

The New SemiWiki Job Board!
by Daniel Nenni on 11-09-2019 at 6:00 am
Categories: General

As a very experienced semiconductor job seeker/employer the most important lesson I have learned in 35 years is that getting the first interview is not so much WHAT you know as WHO you know. Networking really is the key to career success and SemiWiki 2.0 is all about networking, absolutely.

In fact, that is one of the reasons why I became a blogger. What I discovered when I started my career as a semiconductor ecosystem consultant is that I would spend more time looking for clients than actually doing the work which I found to be ridiculously inefficient. Once I started blogging and founded the SemiWiki platform I quickly established a sizable network that made consulting a very profitable career.

Given that, the first thing I would do as a job seeker, besides joining SemiWiki, is to focus on networking. Target specific companies and build a network of people who can assist you in that job search. In my experience the most successful job search is when you find a job before it is posted and the flood gates of resumes open. If not, sometimes applying for that first job opening leads to others so always persist. That is what networking is all about, building a career knowledge base and using it to your advantage.

As SemiWiki approaches its 9th anniversary and celebrates more than 3 million unique visitors we are happy to now include a job board in collaboration with our sponsoring companies who of course we are intimately familiar with. If you click on the Job Board icon in the header you can then search using keywords, location, or company name.   This is open to all job seekers, registered SemiWiki members or not. The SemiWiki job board will be updated daily with new opportunities.

If you are a SemiWiki member then please use the jobs forum discussion area to seek help with specific companies or openings. SemiWiki has more than 40,000 registered users and as a member you can also use the SemiWiki private email system for further discussions.

The best person to start with is me of course. I have the widest network inside the semiconductor ecosystem that you will ever experience. I am also a LinkedIn power user. If I don’t know the right person for your job search inside a company, I certainly know someone who knows the right person.

The semiconductor industry is transforming once again which leads to new career opportunities for semiconductor professionals. If you are relatively new to the industry download our book Fabless: The Transformation of the Semiconductor Industry. If you have questions drop me an email on SemiWiki and we can schedule a call to discuss. The same goes for experienced semiconductor job seekers. Let’s talk about the latest semiconductor industry transformation and how to leverage it for career growth.

The internal mantra for SemiWiki is “For the greater good of the semiconductor industry”. That is why we do what we do, absolutely. Regardless of your experience or circumstance, everyone needs support during a job search so let’s work together for the greater good.

Let’s start the conversation in the comments section and go from there…

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Mentor Adds Circuit Simulators to the Cloud using Azure

Mentor Adds Circuit Simulators to the Cloud using Azure
by Daniel Payne on 11-08-2019 at 6:00 am
Categories: Siemens EDA

Mentor and Azure

Most EDA tools started out running on mainframe computers, then minicomputers, followed by workstations and finally desktop PCs running Linux. If your SoC design team is working on a big chip with over a billion transistors, then your company likely will use a compute farm to distribute some of the more demanding IC jobs over lots of cores to get your work done in a reasonable amount of time. A clearly emerging trend is to consider running EDA tools in the cloud on an as-needed basis, because the cloud scales so easily, and you don’t have to buy all of that hardware and hire an IT group to support you.

I’ve been watching this cloud trend for several years now, and each quarter I see more EDA companies partnering with the major cloud vendors to help IC design teams get their work done smarter and faster than ever before. Mentor for example has cloud-enabled several EDA tools:

In this blog I’m focused on that last bullet point where Mentor recently announced that circuit design engineers can now simulate their SPICE netlists in the Azure cloud, scaling to 10,000 cores. The biggest application of this scaling would be for the task of library characterization flows, effectively shortening the wait time.

I spoke with Sathish Balasubramanian from Mentor last month to better understand why design teams need something like SPICE simulators in the cloud.  He talked about engineering teams using their own compute resources with maybe 200-300 cores, typically running library characterization for a week. Sathish then noted that the same library characterization workload could be run in the Azure cloud on up to 10,000 cores, reducing the compute time to about an hour.  OK, that sounds compelling to me.

Since library characterization and other AMS circuit simulation verification jobs are only run at certain times during a project, it starts to make sense to use a cloud-based vendor like Microsoft with their Azure offering, loaded with either Eldo or AFS circuit simulators.

Mentor has addressed the list of concerns that come up with running EDA tools in the cloud:

  • Security
  • Setup
  • Managing EDA tool licenses
  • Data transferral

I then asked Sathish a set of questions:

Q: Why choose Azure?

A: It’s all based on customer demand, Mentor also has a relationship with Amazon Web Services. Microsoft is a close partner with Mentor.

Q: What is the learning curve like?

It’s quick, like a couple of hours to setup the Azure environment and get started. Customers first setup their Azure account, then start deploying the characterization workload. We have  a configuration already setup for using Mentor library characterization tools, based on our Solido technology.

Q: Can I mix another vendor’s characterization tools with Mentor circuit simulators in the cloud?

A: At this time it’s an all-Mentor EDA tool flow in Azure.

Q: How efficient is it using Azure for circuit simulation jobs?

A: We can use up to 10,000 cores with a 91% linear scaling results, and it took some effort to reach that milestone.

Q: Who are the first customers of this cloud offering?

A: They are top 10 semiconductor companies and foundries, stay tuned for customer quotes.

Q: How do you manage all of those licenses?

A: The EDA tool licenses use Mentor’s FlexLM system, and then Microsoft has their pricing based on how many total CPU cycles you use.

Q: How do I find out about pricing?

A: Just contact your local Mentor Account Manager.

Q: Does Mentor use the cloud in developing EDA tools and running regression testing?

A: Yes, we are users of Azure internally too.

Summary

One classic way to approach a large, compute intensive challenge like SPICE circuit simulation is to divide and conquer, and Mentor’s use of Microsoft Azure to scale up to 10,000 cores for Eldo and AFS tools sure looks like a smarter way to go, compared to building up an internal compute farm.

EDA tools started out with mainframe computers, the early progenitor of cloud-computing, and now with vendors like Microsoft we’ve returned to centralized computing again because it makes sense for peak EDA tool run requirements.

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Webinar – 3D NAND Memory Cell Optimization

Webinar – 3D NAND Memory Cell Optimization
by admin on 11-07-2019 at 10:00 am
Categories: EDA, Events

Flash memory has become ubiquitous, so much so that it is easy to forget what life before it was like. Large scale non-volatile storage was limited spinning disks, which were bulky, power hungry and unreliable. With NAND Flash, we have become used to carrying many gigabytes around with us all the time in the form of cell phones, USB drives, camera SD cards, even laptops. NAND Flash has been a key enabler for dozens of devices that we use on a daily basis. Because they work so well, they have become taken for granted. In one respect this is a good thing, the best technology is that which blends into our lives and does not stand out glaringly.

Yet, the design of 3D NAND devices is complex and requires a great deal of care and consideration. Designers of 3D NAND memories struggle to balance competing requirements in the design of the memory cells. One area that is particularly interesting is the design of the select gate transistor. When optimized properly it is able to drive the bit in question but will not affect adjacent bits.

Silvaco is planning a webinar on November 21st at 10AM PST that will cover the challenges found in designing optimized 3D NAND. Silvaco will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory cell with a focus on the select gate transistor. The end result will be a simulation of the 3D NAND cell operation that includes read/program, erase and program disturb error.

The presenter will be Dr Jin Cho, Principal Application Engineer at Silvaco. Prior to joining Silvaco he has over 15 years of experience in process/device management, including 14/10nm logic technology development. He also has managed a TCAD group for future device development technology. He holds a PhD. From Stanford University.

This technically oriented webinar will thoroughly explore the specifics of 3D NAND design and should be extremely informative. Registration and more details about the webinar are available on the Silvaco website.