Accellera
WP_Term Object
(
    [term_id] => 14325
    [name] => Accellera
    [slug] => accellera
    [term_group] => 0
    [term_taxonomy_id] => 14325
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 3
    [filter] => raw
    [cat_ID] => 14325
    [category_count] => 3
    [category_description] => 
    [cat_name] => Accellera
    [category_nicename] => accellera
    [category_parent] => 386
    [is_post] => 1
)

Semiconductor IP Security Issues

Semiconductor IP Security Issues
by Daniel Payne on 05-26-2019 at 4:46 pm

Every morning I read the headlines from SemiWiki, CNN, LinkedIn and my Twitter feed, and it seems like every week that I read about another security breach that makes me wonder if anything online is secure. Companies try to harden their web sites, IT infrastructure and even their electronic products from being exploited or tampered with. Every article that you read about the IoT and connected devices is sure to mention security. Now let’s take the next step and say that you are designing a new SoC and intend to use hundreds of IP blocks, many from 3rd party vendors, so how do you know that each IP block will function properly and securely once integrated into a system?

I know that in the software world that we get new updates to improve the security of so many things, like: Operating Systems, desktop apps, mobile apps. Even my bike computer and cycling power meter have updates to fix bugs and make them more secure. Every semiconductor IP company has a process for making each IP block secure, but what about the entire industry?

Thankfully our industry has a well-known standards body, Accellera, and they have recently formed an IP Security Assurance Working Group.

Brent Sherman from Intel is the Chair, along with Mike Borza from Synopsys as the Vice Chair, so this looks like a solid start to tackle this concept of IP security across our semiconductor industry. You may even want to join this working group, so begin the process.

DAC 56 is coming up in June, so you should consider attending a luncheon and panel discussion on this timely topic of IP security assurance. The event is planned for Monday, June 3rd from Noon to 1:30PM in Room N246 in the Las Vegas Convention Center. It’s easy to register online here.

DAC56

Accellera Chair Lu Dai will kick off the panel, and it should be lively and informative. The following speakers are panelists:

Brent Sherman
Brent Sherman, Intel
Lei Poo
Lei Poo, Analog Devices
Serge Leef, DARPA
Serge Leef, DARPA
Andrew Dauman
Andrew Dauman, Tortuga Logic
Adam Sherer
Adam Sherer, Cadence

I’ve worked at companies with both Serge Leef and Andrew Dauman, so these panelists are smart, experienced and articulate on the topic of IP security.

Summary

Exploitable vulnerabilities can be mitigated in semiconductor IP, so Accellera is forging ahead with an IP Security Assurance Working Group to create a standard that our industry can define and follow. Visit their web site and plan to attend the DAC luncheon and panel discussion to learn and participate.

Accellera

Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.