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March 19, 2020December 27, 2023

5G Infrastructure Opens Up

5G Infrastructure Opens Up
by Bernard Murphy on 03-19-2020 at 6:00 am
Categories: 5G, Automotive, Ceva, China, IP

It seemed we were more or less resigned to Huawei owning 5G infrastructure worldwide. Then questions about security came to the fore, Huawei purchases were put on hold (though that position is being tested outside the US) and opportunity for other infrastructure suppliers (Ericsson, Nokia, etc) has opened up again.

Building 5G baseband systems (what goes in the cell tower and beyond the tower) is immensely complicated. The baseband divides into 3 units – remote radio units (RRUs) which connect directly to the antennae, a distributed unit (DU) which sits at the base of the tower, which in turn connects to a central unit (CU) to manage connections to multiple DUs.

Incidentally wireless technologies, particularly cellular, breed acronyms like rabbits. I’ll introduce a few here. For example, that thing from Apple or Samsung on which you make calls? It’s not a cellphone, it’s a UE (user equipment).

A 5G RRU needs to deal with sub-6GHz signals and above 6GHz, including millimeter wave. Wi-Fi (802.11ax) and legacy LTE are supported, so RRUs must support multiple radio access technologies (RATs – see what I mean?). The RRU should handle massive MIMO (multi-input, multi-output) reception and transmission, together with beamforming to optimize signal strength. Most of the rest of the processing is handled in the DU and CU.

The base station part of the network in principle sits in that box at the bottom of the cell tower, handling more advanced communication functions and connecting through backhaul to central stations which manage call routing. Except all that is changing. It turns out that having a lot of dedicated electronics for each tower is an expensive proposition for the network operators, especially if demand varies significantly through the day (as it does in metro areas for example).

That has driven variation in who does what, and where, in radio access networks (RANs – from the CU do the DUs to the RRUs). The first switch was to centralized RANs (C-RAN) where almost everything except the RRUs move to central offices. That’s now evolving to virtualized RANs (V-RAN) where there is more flexibility to move functions around. There’s even discussion on an open RAN standard (O-RAN).

Through these systems, the various flavors of 5G must be supported. There’s enhanced mobile broadband (eMBB), the high bandwidth version which will allow you to view 4K TV on your phone or enjoy mobile gaming, VR, MR, etc. Ultra-reliable low latency communication (URLLC) is what you need for safety-critical applications in your car or in medical functions – fast, low bandwidth but dependable latency. Other applications include machine to machine communication (MMC) and fixed wireless access (FWA).

Sailing briefly into acronym-free waters, all these flavors require a lot of multi-core and multi-thread support along with ability to aggregate and flexibly manage traffic from and to multiple targets. Like virtualized job management in data centers except that here you are dealing with high bandwidth communication, all of it requiring a pretty high QoS and some of it requiring guaranteed QoS. (Sorry – I promised no acronyms – QoS = quality of service)

Finally, the 5G standard continues to evolve. Release 15 just came out, release 16 is expected in a few months and release 17 is planned for next year. Anyone planning to hardwire 5G baseband is dead before they start. All of these solutions have to be software based (software defined radio – SDR).

CEVA has just released their XC16 DSP, a core designed specifically for baseband and designed in close partnership with a leading equipment vendor. They’ve also announced that Nokia and ZTE have adopted this platform. This is starting to look more like a horse race again. And meantime you’ve learned more cellular acronyms than you ever wanted to know.

You can learn more about the XC16 HERE.

Also Read:

Using IMUS and SENSOR FUSION to Effectively Navigate Consumer Robotics

A Bundle of Goodies in Bluetooth 5.2, LE Audio

Glasses and Open Architecture for Computer Vision

March 18, 2020May 4, 2022

COVID-19 and Semiconductors

COVID-19 and Semiconductors
by Bill Jewell on 03-18-2020 at 10:00 am
Categories: Semiconductor Intelligence, Semiconductor Services
3 Comments

The threat of COVID-19 (coronavirus) is continuing to spread. As of March 17, the World Health Organization (WHO) reported 179,111 confirmed cases and 7,426 deaths. WHO declared COVID-19 a pandemic as of March 11. Many countries have imposed severe restrictions to slow the spread of the disease, ranging from banning of large gatherings to near-total lockdowns.

According to Digitimes, the top five notebook computer brands (HP, Lenovo, Dell, ASUS and Apple) saw combined shipments in February 2020 drop 40% from January and drop 38% from a year ago. Digitimes also reported electronics production in China is quickly returning towards normal. However, production declines were steep in the first two months of the year. The National Bureau of Statistics of China reported combined January and February 2020 production of mobile phone units was down 34% from a year ago. The total value of Chinese industrial production in January and February was down 13.5% from a year ago.

What will be the effects of COVID-19 on the global economy, and more specifically electronics and semiconductors? It is too early to tell. Much depends on how quickly the disease can be contained and when life for most people can return to relatively normal. Regarding electronics and semiconductors, the two key factors are supply and demand. Supply has been severely disrupted in the short term. Even as China moves back toward more normal production levels, many other countries have severe restrictions which could impact electronics production – including Italy, Germany, France, the U.S., South Korea and Japan. Some factories are closed. Others have reduced staffing levels as employees self-quarantine or stay home to take care of children whose schools are closed. Even if COVID-19 is contained by the end of June, production in the second half of the year will not be fully able to compensate for lost production in the first half.

The demand side is a different story. Certainly, many households will see a reduction in income due to lost workdays. Other households with employees working from home and those with sick leave to cover lost work time will not see a reduction in income. These households could have more discretionary income (income after taxes and necessities) than previously. Many restaurants, bars, movie theaters and other entertainment venues are closed. Many clothing stores are closed. Travel for pleasure is severely curtailed. With spending on these areas severely cut back, households will have more discretionary funds. Much of this extra money will be saved due to the current economic uncertainty. However, some of the money will be available to spend on durable goods such as electronics.

An interesting case is the trend in the United States after the terrorist attacks on September 11, 2001 (9/11). After the attacks, air travel was severely disrupted. The International Air Transport Association estimated air travel demand was down by over 31% in the five months following the attacks. Much of the money people would have spent on air travel and other vacation expenses was spent on consumer goods.

The chart below shows U.S. personal consumption expenditures change versus a year ago from 1Q 2001 through 2Q 2002 using data from the U.S. Bureau of Economic Analysis (BEA). The U.S. was in a recession from March 2001 through November 2001 primarily due to the collapse of the internet bubble. Electronics showed slower growth or declined. PCs and peripherals went from growth in 2000 to declines in 2001. Communications equipment (including mobile phones) and televisions went from double digit growth in 2000 to single digit growth in 2001. However, a shift is apparent beginning in 4Q 2001, the first full quarter after the 9/11 attacks. Air transportation expenditures, already declining in 2Q 2001, declined 28% versus a year ago in 4Q 2001. Expenditures on hotels and motels followed a similar trend. Consumers shifted their spending toward automobiles and electronics. New auto expenditures, which had been in a year on year decline since 4Q 2000, jumped 20% in 4Q 2001. Communications equipment and televisions accelerated from 4% growth in 3Q 2001 to 10% and 8% growth respectively in 4Q 2001. PCs and peripherals were in decline for the first three quarters of 2001. In 4Q 2001 the rate of decline slowed and positive growth returned in 1Q 2002.

The trend in spending is also confirmed by the change in 4Q 2001 versus 3Q 2001. The numbers are seasonally adjusted, so 4Q seasonal trends are taken out. The change in consumer expenditures from 3Q 2001 to 4Q 2001 was 26% for new automobiles, 5.3% for communications equipment, 4.4% for televisions, and 2.2% for PCs and peripherals. Total consumer expenditures were up 1.6%. Meanwhile air transportation was down 9% and expenditures for hotels and motels were down 6%.

During the internet boom, the world semiconductor market peaked at $55.3 billion in 3Q 2000, according to World Semiconductor Trade Statistics (WSTS). The market fell to $30.6 billion in 3Q 2001, a 45% decline. The 4Q 2001 market was basically flat with 3Q at $30.5 billion. Quarter to quarter growth returned in 2002, with 4Q 2002 up 23% from a year earlier. The recovery in the semiconductor market coincides with the electronics boom in the U.S. in 4Q 2001. Other factors also drove the semiconductor recovery, but the post 9/11 strong growth in electronics and automobile spending was certainly a major contributor.

Could a similar trend result when the world economy begins to recover from COVID-19? It is certainly a possibility. Even when the risks of infection decrease, people will still be reluctant to travel. Fear of COVID-19 may also delay returns to restaurants and entertainment venues. People could spend more of their money on electronics, most of which can be enjoyed in the safety of the home.

Electronics and semiconductors will certainly see significant declines in the first half of 2020 due to supply constraints and a falloff in demand. Assuming COVID-19 is contained by the end of 2Q 2020, supply and demand should return to normal levels. As mentioned above, demand could possibly exceed normal levels in the second half of 2020. In February, we at Semiconductor Intelligence forecast 2020 semiconductor market growth of 7%. With the current uncertainty, we are not ready to offer a new forecast, but 2020 will most likely be a year of decline as was 2019.

Also Read:

Semiconductor Recovery in 2020?

CES 2020: still no flying cars

Semiconductor CapEx Warning

March 18, 2020January 12, 2021

Machine Learning for EDA – Inside, Outside and Everywhere Else

Machine Learning for EDA – Inside, Outside and Everywhere Else
by Mike Gianfagna on 03-18-2020 at 6:00 am
Categories: AI, Cadence, EDA

Artificial intelligence (AI) is everywhere. The rise of the machines is upon us in case you haven’t noticed. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making breakfast. We hear a lot about the macro, end-product impact of this technology, but there are many more back-stories about the revolution. Of particular interest to SemiWiki readers is what all this all means for chip design, chip verification and EDA.

I got a chance recently to chat with Paul Cunningham at Cadence about this topic. For those of you who don’t know Paul, he is a Corporate Vice President and General Manager at Cadence. He’s been there for almost nine years, overseeing everything from front-end to back-end to system verification products. With a diverse background like this, we had a lot of ground to cover during our conversation.

We started at 30,000 feet. How does EDA impact AI/ML design and how does AI/ML technology impact EDA? Paul discussed how Cadence approaches these requirements. It turns out there are three separate and distinct areas of focus at Cadence and they’re all important.

Regarding the impact AI/ML has on EDA tools, there are actually two parts to consider. EDA tools are faced with solving a lot of intractable problems that utilize heuristics to manage. Estimating congestion or parasitics for a large digital design early in the place and route flow are examples. In these cases, AI/ML can contribute to better data and a better chip layout as a result. These improvements are really invisible to the user—the tool just delivers better results. Cadence calls this “ML inside”.

The other impact AI/ML has on EDA tools has to do with the design flow. As everyone knows, chip design is an iterative process, with many parts of the design team collaborating to get the best result possible. There are many, many trial runs in the interest of the best layout, most complete verification, lowest power and so on. This process can extend over several months. In this context, AI/ML can be used to analyze the vast amounts of data each iteration produces with the goal of learning as much as possible from a given iteration or set of iterations. This process can reduce design time by essentially working smarter as opposed to harder. This process is quite new as it looks to productize designer intuition to make a design flow more efficient. Cadence calls this “ML outside”.

Paul went on to highlight the significance of ML outside. Up to now, EDA tools have a huge number of input parameters, but none of them capture the history and learning of the tool usage for the problem at hand. Said another way, the tool has no memory of its prior use. ML outside can change all that, creating a fundamentally new type of tool flow.

The third area of focus moves from tool-centric to ecosystem-centric. That is, how can you help to enable the chip and system design ecosystem to add AI/ML to their products? Paul explained that the term, ecosystem, is quite broad in this context and also quite important to the Cadence strategy. Foundries and certain IP suppliers play an important part of course. But design challenges have grown past hardware and Cadence also needs to look at how their verification products interface with software systems like Android, Windows and Linux to deliver a holistic debug capability.

We also discussed the wide variety of markets that all need assistance adding AI/ML to their products. Mobile, automotive, data center and mil/aero are just a few of many examples. What are the demands each of these markets presents? Does each need fundamentally new and different tools, or is it more about the flow? It turns out all chips need basically the same tools to get to tapeout, but the stress points the tools experience and the way the tools need to be tested against other parts of the ecosystem are quite different. If you consider the demands of a very small, ultra-low power chip vs. the demands of a massive data center processing chip, you’ll get the idea. The long life of an automotive chip vs. the relatively short life of a cell phone chip also shed light on the diversity of the problem.

So, supporting a broad range of markets is more about optimizing and testing tools and flows than it is about developing different tools for different markets. Fundamental to this strategy is the development of robust tools that support multiple use models of course. Paul provided a memorable analogy here that is worth repeating, “a Land Rover and a Ferrari are both cars, they’re just optimized and tested to be good at different things.”

Our final topic touched on what future AI/ML chips will look like. Paul felt strongly that a collection of custom, optimized processors will always deliver superior performance for AI/ML algorithms than an off-the-shelf product. So, the future of compute in this context is heterogeneous. Having spent a good part of my career as an ASIC supplier, I couldn’t agree more. This view of the future suggests vibrant growth for both EDA and semiconductor as the number of special purpose AI/ML processors explodes. I’ll leave you with that optimistic thought.

If you’d like to learn more about the AI/ML solutions Cadence offers, visit the AI / Machine Learning page on the Cadence website.

March 17, 2020March 25, 2022

Webinar on Tools and Solutions for Analog IP Migration

Webinar on Tools and Solutions for Analog IP Migration
by Tom Simon on 03-17-2020 at 10:00 am
Categories: EDA, Events, MunEDA

The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog designs there are many more steps and essentially the design will have to be reoptimized to meet its performance specifications before it can work. A lot of companies wade into the waters of analog porting only to realize too late that they are actually stuck in a muddy and complex process.

At that point a couple of well-known and perhaps over used platitudes are apropos – “There is no substitute for experience” and “Use the right tool for the job.” Fortunately for designers looking to smooth out the process of porting analog designs, MunEDA has tons of experience in this area and has a set of tools ideally suited to the task. Their upcoming Webinar titled EDA Tools and Solutions for Analog IP Migration, Optimization and Verification comprehensively covers the entire process and includes information about many of the particulars that can make or break the process. The webinar will be offered on March 26^th at 10AM Pacific Time. MunEDA Vice President of Products & Solutions Michael Pronath will be presenting. His deep understanding of the topic and lucid presentation style make the entire flow understandable.

There are three stages, as alluded to in the webinar title. The first is porting the schematic, which is done by the MunEDA Schematic porting Tool (SPT). As Michael will point out in the webinar, it makes the tricky parts flow smoothly and reduces manual effort in many places. It helps maps new cell names for each of the devices used in the design. Rules can be set for mapping pins and pin locations. New device parameters can be set using expressions. The webinar shows the user interface for these operations. MunEDA has learned through experience many of the subtle issues that arise and have added features to SPT that work through them automatically.

At this point the user has a topologically correct schematic, but one that will not function properly or meet its specs. The circuit now needs optimization and tuning. Michael will show how the MunEDA WiCkeD tool suite is used to size and tune the circuit. For instance, some of the device geometry characteristics that need adjustment are: W, L, fins, fingers, R, C, etc. Also, device threshold values can be set. The goal is to meet specs over all PVT corners with optimal yield, power, area and reliability. Michael will show the user interface and illustrate how to run their optimizer to arrive at design that meets specs and is optimized according to the design criteria. The process is iterative but is managed automatically. He will include several examples from their major customers that show the effectiveness of the flow especially when there are design tradeoffs to be made.

MunEDA has a suite of analog verification tools that are used in the final step – verification. Michael will start by doing a fast corner search to find the worst-case corners. He uses their Worst-Case Operation (WCO) tool for this. It can find the worst-case condition for every spec and structural constraint. He will show the tool and explain some details of its operation.

Michael then will cover Monte Carlo Analysis (MCA) and how their solution generates quantile plots that visualize the probability distributions. The UI also makes it easier to link to the actual simulation runs that the user might be interested in. Another useful set of information they can provide is parameter influence analysis. Parameter sensitivity information is useful for understanding design behavior.

Lastly the webinar will discuss high sigma analysis. MunEDA’s high sigma WCA uses powerful optimization that work across a wide range of sigma values to quickly find the worst-case point for the design. Their solution scales to large designs through the use of advanced machine learning techniques.

It’s extremely rare to find a single source for a solution to such a complex problem. MunEDA has done an excellent job of integrating all the needed elements. The webinar covers each step and goes into the details about how and why. Be sure to check out the replay HERE.

Also Read:

56th DAC – In Depth Look at Analog IP Migration from MunEDA

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Schematic porting – the key to analog design reuse

March 17, 2020July 6, 2020

Innovation in Verification March 2020

Innovation in Verification March 2020
by Bernard Murphy on 03-17-2020 at 6:00 am
Categories: EDA

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.

We welcome comments on our blogs and suggestions for new topics if they’re based on published work.

The Innovation

Our next pick is End-to-End Concolic Testing for Hardware/Software Co-Validation. The paper was presented June 2019 at the ICESS conference. The authors are from Intel Hillsboro and Portland State University.

“Concolic” is a combination of concrete and symbolic, a method to increase coverage in very complex systems through an intermingling of direct code execution/simulation (at the instruction level) and symbolic analysis. Symbolic can do a more general analysis than direct (like formal), while direct execution helps bound these to be near realistic execution paths and can be used to handle libraries/IP inaccessible to symbolic analysis.

The authors earlier build on their own concolic platform, Crete, which they have described in an earlier paper, there applied only to analysis of software utilities. Crete first traces conventional execution through instruction sequences and states, in this instance tracing the system and each IP (here modeled as a virtual model), then flattening that hierarchy into a combined trace.

In the current paper, the trace is instrumented with assertions and symbolic values at hardware/software interfaces. The instrumented trace is then submitted to a concolic analysis. Interesting new traces discovered in this flow, where they violate an assertion for example, can be fed back to directed simulation for further analysis.

Concolic methods are already used in software testing, for example Microsoft reported use of these methods in testing Windows 7. Development and advances we have seen are so far academic or in-house.

Paul

This is an intriguing paper and mature in the scale and type of system they use to analyze their method (a complete mini system with OS, Driver, virtual E1000 Ethernet adapter and virtual 8051 CPU). I like that they consider realistic challenges and limitations. For example, they have thought about how to handle address translation from virtual to physical. Generally, they have pretty robust and scalable ways to instrument verification through callbacks inserted into the instruction stream.

I see a conceptual similarity with constrained random simulation. Constrained-random is a semi-random generation of traces in which each trace is discrete, where a single testbench can generate many traces. Conversely, concolic takes a single discrete trace and abstracts/symbolizes parts of that trace.

I have a couple of thoughts. First, to enable concolic simulation initial analysis must capture virtual model states along the trace. How will this work if you’re using commercial virtual platforms? Should it be an ecosystem play? Virtual component providers may need to offer a mechanism for save/restore in support of concolic methods.

The other point (which the authors fully acknowledge), is that to become really valuable, this testing needs to be able to work with multiple threads/interleaving traces (multiple IPs running concurrently). That will be a harder problem and got me thinking again about portable stimulus, about how you might randomize or explore that space of different concurrent traces. Could we extend PSS / Perspec into concolic? That would be an intriguing direction. Again, I would be interested in helping anyone in academia who wants to explore this idea further.

Finally, they found a couple of real bugs in QEMU, impressive in a well-tested model. I’d like to know more about these, also their take on what made concolic uniquely suited to finding these bugs, versus other approaches such as randomized testing.

Jim

First, I like the idea of system level testing coming together in a unified verification suite.

This area is probably too early stage to be talking about investment potential. When it does reach more maturity, it looks like a technology rather than an independent tool. I get the impression that there will be a million of these good ideas. We’ve already discussed a couple in earlier blogs. Great for verification but the verification team isn’t going to want to see more and more tools.

Maybe we should look at these as widgets that sit inside the primary verification platform. Maybe follow Paul’s idea that PSS is the cockpit where you pull down different apps depending on what kind of verification coverage you’re looking for.

A very simple software example to illustrate a plus for concolic testing over randomized testing is:

int foo(…) { …

if (img.magic != 0xEEEE) return -1;

if (img.h > 1024) return -1;

return img.sz / img.h;

}

This can trigger an error on the division if img.h is 0. Randomized testing has to survive two branches and have the correct value of img.h to trigger that error. Concolic can justify a method to get past both branches, and through symbolic simulation can consider all cases for img.h. Randomization is much simpler in many cases, but concolic can be more effective in threading a path through these complex cases. I see definite value in improving branch coverage in this way for security, maybe also safety and more generally functional reliability.

To see the next paper, click HERE.

To see the previous paper click HERE.

March 16, 2020September 29, 2020

5G SoCs Demand New Verification Approaches

5G SoCs Demand New Verification Approaches
by Mike Gianfagna on 03-16-2020 at 10:00 am
Categories: 5G, EDA, Siemens EDA

Lately, I’ve been cataloging the number of impossible-to-verify technologies we face. All forms of machine learning and inference applications fall into this category. I’ve yet to see a regression test to prove a chip for an autonomous driving system will do the right thing in all cases. Training data bias is another interesting one to quantify. The list can get quite daunting.

Mentor recently published a new white paper on the challenges of verifying 5G SoCs. It turns out this is another one of those impossible-to-verify technologies. The good news is Mentor outlines a method in their white paper on how to make this one possible. Let’s start with some background on 5G networks – why are they so hard to verify?

This is the first topic of the Mentor white paper. When 4G was developed, the systems were defined by essentially three major vendors. The standards weren’t open and connections were established with fixed cabling. So, cellular operators sourced equipment from these major vendors and 4G became a reality. Figure 1, from the white paper illustrates what this looked like.

With the rise of applications such as connected vehicles (think cars, planes, trains, construction equipment farm tractors and so forth) and all the other connected devices that comprise IoT, the data volume for cellular networks has exploded. That spawned the need for 5G and as everyone knows, 5G networks are being brought up by many carriers in all parts of the world right now. There is an important “twist” in the way the network is being implemented, however.

This time, the cellular operators took control and defined open standards, allowing many new companies to build the hardware and software required for 5G networks. 5G technology is also quite a bit more challenging to implement than 4G. For example, signal transmission requires an array of up to 64 X 64 multiple-input/multiple-output (MiMo) antennas that can support the beamforming required for 5G signals.

Landscape and population density variations (think cities vs. rural areas) will also need customization to work correctly, creating many hardware/software configurations. To help alleviate this issue, an alliance of telecom industry companies created the Open Radio Access Network (O-RAN) standard. Figure 2, from the white paper illustrates what this new environment looks like.

So, with 5G we have many new vendors (both hardware and software), a variety of use cases and configurations and evolving 5G standards. A lot of the new products for the 5G market have, at their core, a mission critical SoC. It is the verification of those SoCs, in the challenging environment described that is discussed in the new Mentor white paper.

The white paper focuses on the litany of challenges to develop robust and re-usable tests for these SoCs. The outline of the problem includes solid verification suites that can be run before silicon is available on prototypes of the hardware and after silicon is available on the real system. Due to the size of the 5G ecosystem, these test suites need to be shared to ensure interoperability.

Pre-silicon verification requires more than a standard RTL flow – emulation is required to run the requisite number of tests at speed. Mentor’s Veloce® Strato™ emulator is well-suited to address this requirement and that is explored in the white paper. Once silicon is available, the focus moves to verification of the chip in the lab and in the field. Here, Mentor offers its X-STEP™ platform. This product is focused on the unique needs of the 5G market and can be used for either data generation or data capture.

The white paper goes into much more detail on these topics and others as well. If you are engaged in design of 5G SoCs, you will want to learn about Mentor’s 5G SoC design and verification flow for pre- and post-silicon. You can access the white paper here.

March 16, 2020July 6, 2020

Will the Q1 Haircut become Covid-19 Crew Cut in Q2?

Will the Q1 Haircut become Covid-19 Crew Cut in Q2?
by Robert Maire on 03-16-2020 at 5:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

Corona impact growing exponentially in chip food chain
YMTC in Wuhan may be “patient zero”
Q1 revenue haircuts may turn into Q2 crewcuts
Working from home really doesn’t work

When does a haircut become a crew cut in revenues?
All the major semiconductor equipment makers took a significant haircut to their Q1 revenue and EPS guidance based on expected impact from Covid-19.

In addition to the haircut, the companies likely built in enough of a buffer to handle most eventualities however the impact of Covid-19 is likely well beyond what their expectation was over a month ago.

Lam, not wanting to ruin their recent analyst day, had an opportunity to update on business outlook, but declined.

We are getting close to pre-announcement season and would not be surprised to get a few companies laying out the negative impact of Covid-19 on their business. We expect this in both the semiconductor and semiconductor equipment companies as well as their sub-suppliers.

We think that given the progression of the pandemic on a world wide basis that Q2 numbers could get a crew cut rather than the haircut coming out of Q1. Given that Q1 is likely worse than expected for most companies and the stocks are in virtual free fall there is almost zero downside in trashing Q2 numbers…its not going to make the stocks go down any more than they already are.

Most companies were looking at an up Q2 after a normally seasonally slow Q1 but now flat may turn out to be optimistic for many.

Unfortunately it is still too early to call as things have not fully run their course and continue on a downward trajectory. Perhaps the bigger concern will now be if the damage done by Covid-19 can be contained within the calendar year as almost every company had originally projected.

Working from home doesn’t really work
A number of large silicon valley firms have already told employees to work from home. For a lot of companies employees with a laptop and phone can be just as effective wherever they are located. There is not that much hard core manufacturing left in the valley with semiconductor equipment being an exception. Yesterday, Lam Research told employees to work from home and our drive past the Lam parking lot confirmed that .

The problem is that there are a lot of employees at Lam, Applied, KLA and others that screw together tools or need to be in a lab to do R&D with sophisticated equipment, that can’t work from home. We have also heard of sub suppliers working from home as well. We would also expect Applied Materials and KLA and others to follow Lam’s lead. The problem is that work from home doesn’t work all that well for tool makers as someone has to crate it up and put it on the truck before the end of the quarter.

While Q1 may be somewhat “in the bag” already, given that we are mostly through the quarter , Q2 is more of an open question.

Much like our recent report about access to fabs being controlled and complicated by the virus, the tools makers would not like to have an infected employee take down a production line building tools.

YMTC suppliers will get first impact
YMTC, the Chinese memory maker, conveniently located in the epicenter, Wuhan, of the Covid-19 outbreak will likely see the largest impact of any fab. Right now, YMTC is not a huge supplier of memory product to the world market as they are still ramping technology….however they are a big buyer of semiconductor equipment tools and will likely have more impact on what they buy rather than what they sell.

If we look at all the rapidly expanding business done in China by chip equipment companies, YMTC is at the top of the list so it will be impactful.

We will also be looking to see how quickly they come out of it and get back to their ramp of technology.

Still getting worse before it gets better
Much like the cyclicality that the semiconductor industry goes through, things continue to slide downward for a while before bottoming and turning.

As we are in uncharted territory with the virus, its unclear whether this is a “V” shaped, “U” shaped or the dreaded “L” shaped bottom.

We are hoping and expecting a somewhat “V” shape but the virus may echo around the planet such that the echoes and collateral damage may continue long after the virus itself burns out.

Stocks- Probably still early to go back in the water
After a crash dive on Monday followed by a “dead cat bounce” on Tuesday we are back to a free fall on Wednesday that has erased the dead cat bounce gains.

This manic depressive behavior could go on for a while and its likely safer to watch from a distance.

We had suggested that the stocks and the market overall were way ahead of themselves and likely made them even more vulnerable to events and we got a big event. Everyone seemed to know that valuations had gone too far but everyone was too busy enjoying it while it lasted.

Given all the collateral damage, and echoes of the pandemic it is likely to take a lot longer for the stocks to recover than the rapid run up in valuations we experienced over the past quarters and years .

From a semiconductor & semiconductor equipment perspective the risk of a government legislated embargo on business with China or severely limited “licensed” business has fled everyone’s collective memory.

It would be a case of very bad luck if just when we start to get over the pandemic that the government would step in and halt sales that just restarted.

Like getting over a bad case of the flu only to walk outside and get hit by a truck.

But that would never happen……..

March 15, 2020February 15, 2023

The Need for Low Pupil Fill in EUV Lithography

The Need for Low Pupil Fill in EUV Lithography
by Fred Chen on 03-15-2020 at 10:00 am
Categories: Lithography
2 Comments

Extreme ultraviolet (EUV) lithography targets sub-20 nm resolution using a wavelength range of ~13.3-13.7 nm (with some light including DUV outside this band as well) and a reflective ring-field optics system. ASML has been refining the EUV tool platform, starting with the NXE:3300B, the very first platform with a numerical aperture of 0.33. With the current NXE:3400B platform, a pupil fill ratio lower limit of 20% (without loss of light) is now possible, offering improved contrast for smaller features [1]. In this article, the basic reasons behind this improvement are presented.

Illumination locations in the pupil

The pupil is essentially an aperture or window through which the specified angles of illuminating the EUV mask go through. The center angle is along the optical axis, which naturally folds throughout a reflective optical system, and also happens to be at a 6 degrees with respect to the normal to the mask. A pupil can be represented as an assembly of points, whose x and y coordinates are the sine of the angle made with the optical axis in x and y directions, respectively.

Optical projection systems basically operate on spatial frequencies, which in turn are indicators of feature pitches (spatial frequency = 1/pitch). Images containing larger pitches, more isolated features, will have a wide range of spatial frequencies, including very low ones. Images containing the densest features, smallest pitches, will have only the highest spatial frequencies. When the spatial frequency is too high, it will be cut off by the numerical aperture of the final lens (or mirror in the case of EUV). The numerical aperture is essentially a low-pass filter. In order to retain these high spatial frequencies, it would be necessary to shift the illumination, selecting pupil points which are off-center. This shifts the target spatial frequencies away from the cutoff edge of the numerical aperture.

Stochastic Effect of Large Pupil Fill

Complex 2D patterns will contain both minimum pitches and much larger pitches. In that case, it is necessary to check each point in the pupil for what images will result from an illumination from that point.

Figure 1 shows an example for where minimum pitch is 28 nm, and there are larger pitches of 84 nm in x and 168 nm in y. The wavelength is taken to be 13.5 nm, the numerical aperture to be 0.33.

Figure 1. Images from two different neighboring source points in the pupil. The target pattern is on the lower left. Although quite similar, the two images are distinctly different. In a realistic exposure condition, both would be represented by very small fractions of the total dose.

The images produced by two neighboring source points were shown to be similar but still different. Assuming a conventional illumination condition with sigma=1 (maximum on NXE:3400B [2]), uses the entire displayed collection of source points, and represents the largest possible pupil fill. Under this condition, the images represented by these two selected source points are only supported by 1-3% of the dose applied at the wafer. Hence there are few photons emanating from these points (<1 mJ/cm2, <1 photon/nm2), which aggravates the shot noise.

If fewer differently diffracted images need to be added up together to form the final image, this would reduce the stochastic impact. Presumably, instead of the conventional illumination using all the displayed points, only a certain optimized subset would work. This is the basic principle behind source-mask optimization (SMO) [3]. Naturally, the pupil fill is thus reduced. Ideally, only one diffracted image will be used, with all the exposure dose going there. However, the pupil fill fraction may go very low, even as low as 1-3% if we used one of the two source points used above as examples. On the current NXE:3400 systems, pupil fill fractions below 20% will result in loss of throughput [2].

Rotation Sensitivity for Dense Features

For a 0.33 NA and central wavelength of 13.5 nm, dense features with pitches of 40 nm or less can only be resolved by illuminations at wide enough angles, i.e., angles that deviate far enough from the optical axis. As an example, a 28 nm vertical line pitch can only be resolved by a distribution of angles indicated by the blue dots in the left part of Figure 2.

However, since the EUV optical system is reflective, it requires a ring-field to minimize aberrations. This, in turn, requires the exposure field to be shaped like an arc. The pupil is rotated azimuthally through this arc across the field, in some reported cases by over 24 degrees [4, 5].

Figure 2. Left: Dipole illumination for 28 nm vertical line pitch. Right: after 18 degree rotation at a different slit position, some illumination points are outside the originally allowed range. This would lead to more background light washing out the image. A reduced pupil fill (including points only within the dotted lines) avoids this outcome.

The right part of Figure 2 compares the original illumination distribution with after an 18 degree rotation. Some points in the original illumination distribution have now been rotated outside into the forbidden illumination zone. These illumination points will now degrade the final image, as they no longer let the required spatial frequencies pass through to the wafer. They only contribute background light. Hence, to avoid this, a subset of the original distribution (marked by the dotted lines) should be used. However, this pupil fill will be less than 20%.

Alternatively, to use a larger pupil fill, the rotation range can be reduced by limiting the field width [6]. Instead of the full 26 mm width of the exposure field, half of it or less can be used instead. The tradeoff here is that the scanner now must make more exposure field stops across the wafer, and this also limits throughput.

Conclusions

The need for pupil fill reduction can now be understood as conferring benefits of reduced impact from stochastics and pupil rotation in EUV lithography. However, with the likely need to go to pupil fill ratios of <20%, throughput concerns cannot be ignored.

References

[1] A. Pirati et al., Proc. SPIE 9776, 97760A (2016).

[2] M. van de Kerkhof et al., Proc. SPIE 10143, 101430D (2017).

[3] A. E. Rosenbluth et al., Proc. SPIE 4346, 486 (2001).

[4] https://sst.semiconductor-digest.com/2014/02/the-impact-on-opc-and-sraf-caused-by-euv-shadowing-effect/

[5] R. Capelli et al., Proc. SPIE 10957, 10950X (2019).

[6] https://www.linkedin.com/pulse/forbidden-pitch-combination-advanced-lithography-nodes-frederick-chen/

This article first appeared in LinkedIn Pulse: The Need for Low Pupil Fill in EUV Lithography

There is No Easy Fix to AI Privacy Problems

There is No Easy Fix to AI Privacy Problems
by Matthew Rosenquist on 03-14-2020 at 8:00 am
Categories: AI, Security
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Artificial intelligence – more specifically, the machine learning (ML) subset of AI – has a number of privacy problems.

Not only does ML require vast amounts of data for the training process, but the derived system is also provided with access to even greater volumes of data as part of the inference processing while in operation. These AI systems need to access and “consume” huge amounts of data in order to exist and, in many use cases, the data involved is private: faces, medical records, financial data, location information, biometrics, personal records, and communications.

Preserving privacy and security in these systems is a great challenge. The problem grows in sensitivity as the public becomes more aware of the consequences of their privacy being violated and misused. Regulations are continually evolving to restrict organizations and penalize offenders who fail to respect users’ rights. British Airways was, for example, recently fined $228 million by the European Union for privacy violations.

There is currently a fine line that AI developers must walk to create useful systems to benefit society and yet avoid violating privacy rights.

For example, AI systems are an excellent candidate to help law enforcement rescue abducted and exploited children by identifying them in social media posts. Such a system would be relentless in scouring all posts and matching images to missing persons, even taking into account the likely changes of years passing by, something impossible for humans to accomplish accurately or at scale. However, such a system would need to do facial recognition analysis on every picture posted in a social network. That could identify and ultimately contribute to tracking everyone, even bystanders in the background of images. Sounds creepy and you may likely object. This is where privacy regulations and ethics must define what is allowable. Bringing home kidnapped kids or those who are forced into sex trafficking is very worthwhile but still requires adherence to privacy fundamentals, so greater harms aren’t inevitably created.

To accomplish such a noble feat, a system would need to be trained to recognize the faces of children. For accuracy, it would require a training database with millions of children’s faces. To follow the laws in some jurisdictions, the parents of each child in the training data set would need to approve the use of their child’s image as part of the learning process. No such approved database currently exists and it would be a tremendous undertaking to build one. It would probably take many decades to coordinate such an effort, leaving the promise of an efficient AI solution for finding kidnapped or exploited children just a hopeful concept for the foreseeable future.

Such is the dilemma of AI and privacy. This type of conflict arises when AI systems are in training and also when they are put to work to process real data.

Take that same facial recognition system and connect it to both a federal citizen registry and millions of surveillance cameras. Now, the government could identify and track people wherever they go, regardless if they have committed a crime, which is very Orwellian.

But innovation is coming to help – federated learning, differential privacy, and homomorphic encryption are technologies that can assist in navigating such challenges. However, they are just tools and not complete solutions. They can help in specific usages but always come with drawbacks and limitations, many of which can be significant.

Federated learning (aka collaborative learning) makes possible the training of algorithms without local data sets being exchanged or centralized. It’s all about compartmentalization, which is great for privacy, but it difficult to set up and scale. Additionally, it can be limiting to data researchers that are desperate for massive data sets containing the rich information needed for training AI systems.
Differential privacy takes a different approach, attempting to obfuscate the details by providing aggregate information but not sharing specific data, i.e., “describe the forest, but not individual trees”. It is often used in conjunction with federated learning. Again, there are privacy benefits but it can result in serious degradation of accuracy for the AI system, thereby undermining the overall value and purpose.
Homomorphic encryption, one of my favorites, is a promising technology that allows for data to remain encrypted yet still allow useful computations to be done as if they were unencrypted. Imagine a class of students being asked who is their favorite teacher: Alice or Bob. To protect the privacy of the answers, an encrypted database is created containing the names of individual students and the corresponding name of their favorite teacher. While in an encrypted state, calculations could be done, in theory, to tabulate how many votes there were for Alice and for Bob, without actually looking at the individual choices by each student. Applying this to AI development, data privacy remains intact while training can still proceed. Sounds great, but in real-world scenarios, it is extremely limited and takes tremendous computing power to accomplish. For most AI applications it is simply not a feasible way to train the system.

For now, there is no perfect solution on the horizon. It currently takes the expertise of and committed partnerships between privacy, legal, AI developers, and ethics professionals to evaluate individual use-cases to determine the best course of action. Even then, most of the focus is placed only on current concerns and not on applying a more difficult strategic viewpoint of what challenges will emerge in the future. The only thing that is clear is that we need to achieve the right level of privacy so we can benefit from the tremendous advantages that AI potentially holds for mankind. How that is achieved in an effective, efficient, timely, and consistent manner is beyond what anyone has figured out to date.

March 13, 2020April 26, 2022

SPIE 2020 – Applied Materials Material-Enabled Patterning

SPIE 2020 – Applied Materials Material-Enabled Patterning
by Scotten Jones on 03-13-2020 at 10:00 am
Categories: Events, Lithography, Semiconductor Services, TechInsights
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2020 SPIE Media Briefing Full Slides for Scott Jones Page 16

I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement.

At IEDM Applied Materials (AMAT) tried to put together a panel across the entire semiconductor ecosystem on how to shrink the technology. Authors note, you can read my write up on the panel here.

There is a need to look at all of the factors when shrinking with the latest focus being power, performance, area and cost (PPAC). On the panel TSMC also mentioned the need to consider time. Part of AMAT is announcing is simplification of processes that helps with cost and time by eliminating steps.

The three pieces to the announcement are:

Square spacers
Lateral etching
Selective processing

Square spacers

SAxP is a widely used patterning technology with Self Aligned Double Patterning (SADP) and Self Aligned Quadruple Pattering (SAQP) being the most common. The basic premise is to create a mandrel pattern and then deposit sidewall spacers on the edges of the mandrel to double the pitch. Typically, these sidewall spacers have rounded top edges. When running SAQP, one way to compensate for the rounded top edges is to deposit two mandrels and use the spacers to define the second mandrel but this adds process complexity.

In the past people have tried to control the spacer top edge rounding by optimizing the etch and have added a second mandrel but this increases cost and complexity. AMAT has changed the spacer material to get square spacers allowing them to reduce the number of process steps. Figure 1 illustrates the conventional double mandrel SAQP process (top) and square spacer SAQP process (bottom).

Figure 1. Square Spacer SAQP Versus Double Mandrel SAQP.

Providing square spacers can reduce major process steps from 15 to 11 because the square spacer is high enough quality to be the next mandrel. You do lose some ability to have multiple critical dimensions (CDs) with this technique.

Lateral Etch

SAxP processes create lines and spaces with double the pitch for SADP and quadruple the pitch for SAQP. The resulting lines need to be cut in the orthogonal direction. The distance between the cut line ends is referred to as tip to tip (T2T) and there is a fundamental trade-off between the line-space pitch and the T2T.

AMAT’s new lateral etch process enables lateral etching with control of the direction so they can reduce T2T. Figure 2, illustrates the ability to reduce T2T by etching preferentially in one direction.

Figure 2. Reduction in T2T by Lateral Etching.

During the call I suggested to Regina that this lateral etching technique could be useful for 3D NAND stair step etching where shrinking lateral dimensions without reducing the photoresist could potentially reduce the number of masks required and she agreed that could be very interesting.

Selective Processing

Edge Placement Errors (EPE) is a serious problem particularly for complex multi-patterning schemes where the interaction of multiple masks adds together to drive up EPE.

Previous selective materials grew up and out creating a kind of mushroom structure limiting their use to thin films. The new selective deposition from AMAT grows up allowing thicker films. The new selective deposition material is also etch selective to titanium nitride (TiN) hard masks so selective patterns can be created where etching is selective to TiN and then to the new material eliminating EPE and allowing for maximum size of critical features like vias providing lower resistance.

An example of the process would be:

The wafer already has a metal pattern on it.
Selective deposition creates tall layers over the existing metal pattern.
Gap fill deposition fill between the tall features and up over the top of the features and is then planarized by CMP.
Deposit TiN hard mask.
Metal lithography defines the pattern for the next metal layer.
Etch the metal pattern into the TiN and into the gap fill film, this expose the underlaying selective deposition film wherever the current metal pattern overlaps the previous metal pattern.
Via lithography opens where the vias will be formed, this mask can be oversized because the vias will be self-aligned.
Etch the vias, the via pattern is constrained by the TiN metal hard mask in one direction and only etch out where the selective deposition material is exposed creating vias that are self-aligned to the original metal layer.

Figure 3 illustrates the EPE and cost advantage of the self-aligned process.

Figure 3. Selective Processing Enable EPE and Cost Improvement.

Conclusion

The three process innovations described here improve process latitude, reduce cost and time and improve performance.

Square spacers eliminate process steps in SAQP processes reducing cost and process time.
Directional etch improves T2T spacing enabling more compact layouts improving cost.
Selective processing reduce EPE and enables maximum via sizes improving performance.

Also Read:

LithoVision – Economics in the 3D Era

IEDM 2019 – Imec Interviews

IEDM 2019 – IBM and Leti