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Low Energy Electrons Set the Limits for EUV Lithography

Low Energy Electrons Set the Limits for EUV Lithography
by Fred Chen on 03-25-2020 at 6:00 am

Low Energy Electrons Set the Limits for EUV Lithography

EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.

Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon. Photoelectrons initially released by EUV absorption are expected to be ~ 80 eV, and release energy by further ionization, producing secondary electrons [1]. The photoelectrons and secondary electrons can lose energy by plasmon generation as well [2]. Electrons with energies as low as 1.2 eV can still expose resists [3]. Dissociative electron attachment (DEA) can also occur at very low energies [4]. Consequently, the image is affected by the “blur” resulting from the spread of these electrons. An example is shown below in Figure 1. Even a few nm blur or a few nm blur difference can degrade the sub-20 nm image’s sensitivity to dose variations.

Figure 1. Secondary electron blur is modeled as a Gaussian function involved with the original non-blurred image, fitted with a Gaussian as well [5].

How far can the electrons travel?
A simple Monte Carlo simulation demonstrates that a fairly wide spread of electron paths is possible even with a low mean free path. In Figure 2, four simulation runs are shown, each representing 30 collisions of an electron, where the electron travels 1 nm in a random direction between collisions (including mostly elastic (no energy lost or gained) and inelastic low energy (<0.1 eV) transfers with phonons [6]), is shown to lead in some cases to travel distances approaching 10 nm. The “r” result is the net distance (regardless of direction) from the original starting point, treated here as (0, 0, 0) , i.e., r=sqrt(x^2+y^2+z^2).

The distribution of distances is shown in Figure 3. The mean final travel distance was 5.1 nm with a standard deviation of 2.25 nm, while the mean max distance was 6.5 nm with a standard deviation of 1.5 nm. Even with a limited sampling (N=20), the distribution of travel distances covers a fairly wide range of nanometers.

Figure 2. Simulations of electrons going through 30 collisions, mostly elastic, the remaining assumed to be low energy transfers to phonons [6].

Figure 3. Distribution of final and maximum travel distances after 20 simulation runs using the conditions of Figure 2.

Increasing or decreasing the travel distance between collisions will naturally increase or decrease the net travel distance as well. The inter-collision distance of 1 nm is comparable to the step size used in other recent related work [7, 8]. Measurements of resist loss from low energy electrons are also in excess of 1 nm [3, 4]. Of course, more collisions accumulated will lead to a wider range of travel distances as well. Another possibility to consider is net positive charge at the starting position, which might slow down further migration by Coulomb force attraction. Recent work, however, suggests this could be negligible [8].

Takeaway Thoughts
For a fully rigorous and complete EUV resist model, in addition to the aerial (photon-only) image input, we need to have the accurate representation of low energy electron blur. These simulation runs hint that it is somewhat oversimplified to have a fixed electron blur value. It is more prudent to consider a range of blur values. This is better for giving the process variation (PV) bands.

Appendix (Technical Note):
Simulations are run on an Excel sheet. Starting point (0, 0, 0). Random spherical coordinate system angle theta (0 to 180 deg) and phi (0 to 360 deg) selected using RANDBETWEEN function, while jump step is fixed (1 nm for this article). Jump = (jump step * sin(theta) * cos(phi), jump step * sin(theta) * sin(phi), jump step * cos(theta)). This is iterated 30 times for the runs in this article.

References
[1] J. Torok et al., “Secondary Electrons in EUV Lithography,” J. Photopolym. Sci. and Tech. 26, 625 (2013).

[2] G. Denbeaux et al., “The role of secondary electrons in EUV resist,” EUVL Workshop 2014.

[3] I. Bespalov et al., “Key Role of Very Low Energy Electrons in Tin-Based Molecular Resists for Extreme Ultraviolet Nanolithography,” ACS Appl. Mater. Interfaces 12, 9881 (2020).

[4] B. Sun, “Low-energy electron-induced chemistry of PMMA,” Master of Science thesis, July 2014.

[5] https://www.linkedin.com/pulse/from-shot-noise-stochastic-defects-dose-dependent-gaussian-chen/

[6] B. Ziaja, R. A. London, and J. Hajdu, “Ionization by Impact Electrons in Solids: Electron Mean Free Path Fitted Over a Wide Energy Range,” J. Appl. Phys. 99, 033514 (2006).

[7] H. Fukuda, “Localized and cascading secondary electron generation as causes of stochastic defects in extreme ultraviolet projection lithography,” J. Micro/Nanolith. MEMS MOEMS 18(1), 013503 (2019).

[8] L. Wiseheart et al., “Energy deposition and charging in EUV lithography: Monte Carlo studies,” Proc. SPIE 9776, 97762O (2016).

 

Related Lithography Posts


Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
by Mike Gianfagna on 03-24-2020 at 10:00 am

Screen Shot 2020 03 14 at 5.36.37 PM

I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration between Synopsys and ANSYS to solve them, you have a real winner in my view. The details of how industry-leading extraction and analysis tools from ANSYS are tied to industry-leading implementation tools from Synopsys are clearly worth a look.

You can view this webinar on Tuesday, March 31, 2020 at 10AM Pacific time. Mark that on your calendar. The registration link is included, above.  I’ll repeat it later. Let’s first review who’s presenting at this webinar and what they’ll cover.

The first speaker is Rahul Deokar, director of marketing and business development for the Synopsys Fusion Design Platform, with focus on signoff products, including RedHawk Analysis Fusion. Rahul begins his presentation with a review of the technology trends and associated challenges and dangers presented by things like dynamic voltage drop and power integrity. He then presents Redhawk-SC and discusses its capabilities to effectively deal with the problems under discussion.

Rahul then describes RedHawk Analysis Fusion, a two-year project to combine the analysis capabilities of ANSYS RedHawk with the implementation capabilities of Synopsys ICC II/Fusion Compiler. Signoff quality analysis with a native integration to an industry-leading implementation flow at the block, subsystem and full-chip levels. This really got my attention.

Getting into more details, Rahul explains the benefits of block-level signoff accuracy, robust place & route optimization and the ability to access the latest distributed processing capabilities of RedHawk-SC. Rahul then summarizes the added features in the new release of RedHawk Fusion. The list is quite extensive and impressive. He also covers the power integrity design flow that is enabled by RedHawk Fusion. To give you a feeling for the what’s included, I’ll just mention one of the many capabilities covered:

Dynamic Power Shaping: optimizes peak current and reduces dynamic voltage drop via clock scheduling.

All the capabilities presented are illustrated with real design examples, including case studies of a 7nm design. To whet your appetite further, machine learning is also employed in the release.

Marc Swinnen then presents the details of ANSYS RedHawk-SC, their next-generation product for 7nm and below. Marc is the director of product marketing at ANSYS. The next-generation architecture for RedHawk was developed about four years ago and it’s called SeaScape – RedHawk-SC is based on it. Marc explains that the motivation for this new platform was two-fold:

  • Address the capacity requirements resulting from the dramatic increase in analysis at advanced nodes
  • Extend IR-drop analysis to handle the multi-physics considerations of new effects such as electromigration, inductance and thermal gradients

Marc explains that SeaScape uses the same approach for data organization that is used by big data and artificial intelligence tools. Marc goes on to detail the distributed architecture of SeaScape. The discussion is quite impressive and improvements in speed, capacity and efficiency are substantial. Marc also discusses chip-package co-analysis, a critical item for advanced 2.5 and 3D packaging.

Rahul then presents the results of actual customer designs using RedHawk Fusion. Several application areas, all at advanced nodes and from different parts of the world are covered. The webinar concludes with a Q&A session that shines more light on the types of designs this flow can be used on.

The depth of detail presented during this webinar, along with the unique collaboration of two major design tool suppliers make this webinar a must-see. You can register for the webinar here. Don’t miss this one.

Also Read:

Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Navigating Memory Choices for Your Next Low-Power Design

Hybrid Verification for Deep Sequential Convergence


Mentor Masterclass on ML SoC Design

Mentor Masterclass on ML SoC Design
by Bernard Murphy on 03-24-2020 at 6:00 am

ML algo design

I was scheduled to attend the Mentor tutorial at DVCon this year. Then coronavirus hit, two big sponsors dropped out and the schedule was shortened to three days. Mentor’s tutorial had to be moved to Wednesday and, as luck would have it, I already had commitments on that day. Mentor kindly sent me the slides and audio from the meeting and I’m glad they did because the content proved to be much richer than I had expected.

Lauro Rizzatti  and Steve Bailey provided an intro and confirmed my suspicion that this class of solutions is targeted particularly at hardware accelerators. Could be ML, video, audio, wireless algorithms, any application-specific thing you need to speed up and/or reduce power in an edge device. Maybe a surveillance product, which had been getting by with a low-res image and ML software running on a CPU, now you must move to 4K resolution with faster recognition at the same power. You need a hardware accelerator. For this tutorial they use TinyYOLO for object recognition as their demo platform.

Russ Klein came next with a nod to algorithm design (in TensorFlow using Python) then algorithm partitioning and optimization. Sounds like a big yawn, right? Some basic partitioning, changing bus widths and fixed-point sizes, tweaking here tweaking there?

Wrong – very wrong.

This may be the best tutorial I have seen on the topic, from explanations of the mechanics behind convolution to how that maps into implementation. Not just for toy implementations, but through stepwise improvements all the way up to arrays of processing elements, close to the state of the art.

The process starts with a TinyYOLO algorithm running in TensorFlow executing on a laptop. This reads camera frames within a video feed, a scene of some kind, and aims to recognize certain objects – a dog, a bike, a car – and output the same scene feed with labeled bounding boxes around those objects. He noted that a single inference requires 5.2B floating point operations. It’s not practical to do this in software for real time recognition response.

They ran profiling on the software and of course all those multiply-accumulate (MAC) operations stuck up like a sore thumb, so that’s what they want to drop into hardware. Since this is a pitch for high-level synthesis (HLS), they want to convert that part of the algorithm to C++ for later synthesis to RTL.

But not all at once.

Russ and following speakers emphasized the importance of converting and verifying in steps. They break their neural net up into 9 stages and replace each stage, one at a time in the Python flow with a C++ implementation, verifying as they go. Once those all match, they replace all those stages and verify again. Now they can experiment with architecture.

Each stage come down to a bunch of nested loops; this is obviously where you can play with parallelism. As a simple example, an operation that in software might take 32 cycles can be squished into 1 cycle if the target technology makes that feasible.

Next is a common question for these 2D convolutions – what are you going to optimize for in on-chip memory? These images (with color depth) are huge, and they’re going to be processed through lots of planes, so you can’t do everything in local memory. Do you optimize to keep feature maps constant, or output channels constant, or use a tile approach where each can be constant over a tile but must change between tiles? Each architecture has pros and cons. Experimenting with different options in the C++ code, to first order, is just a matter of reordering nested loops.

However which option really works best relates in performance and power directly to on-chip memory architectures. Russ talked about several options and settled on shift registers, which can nicely support a sliding 3×3 convolution window and allow multiplies within that window to run in parallel.

Ultimately this led them to a processing element (PE) architecture, each element containing shift registers, a multiply and an adder. They can array these PEs to get further parallelism and were able to show they could process ~700B operations per second running at 600MHz. Since 5.2B operations are required per inference, that’s ~7ms per inference by my math.

There was also an interesting discussion, from John Stickley, on the verification framework. Remember that the goal is to always be able to reverify within the context of the original TensorFlow setup – replace a stage in the Python flow with a C++ equivalent or a synthesized RTL equivalent and reverify that they are indeed equivalent.

They run the TensorFlow system inside a Docker container with an appropriate version of the Ubuntu OS and TensorFlow framework, which they found greatly simplifies installation of the AI framework and the TinyYOLO (from Github), along with whatever C++ they were swapping in. This also made the full setup more easily portable. C++ blocks can then become transactors to an emulation or an FPGA prototype.

There’s a huge amount of detail I’m skipping in this short summary. You can get some sense or the architecture design from this link, though I hope Russ also write up his presentation as a white-paper.


Reducing Your ASIC Production Risk!

Reducing Your ASIC Production Risk!
by Daniel Nenni on 03-23-2020 at 10:00 am

Delta Managing the ASIC Supply Chain

Managing the ASIC manufacturing is one of the biggest challenges of chip projects.

Building an ASIC supply chain requires specific expertise. Throughout the process you’ll be confronted with hundreds of decisions that will require specific knowledge in order to be addressed correctly, avoid costly mistakes and lose time. How should your ASIC be designed for testability? Which packaging technology will ensure the optimal performance? How to
optimize test throughput and build up for volume production? How to quickly identify the root cause of failures?

Below highlights of some key points. For the full content, read the full paper, 5 Best Practices for Successfully Managing an ASIC Supply Chain.

Plan for Problems
With ASIC manufacturing, things may go wrong, and in most cases, they do. A design can change midway through the ASIC development process; an RF wire bond issue may be discovered; and yield may drop due to an unknown reason.

Analyse in advance the risks associated with your specific ASIC development project and make sure that both you and your partners clearly understand the risks and have a corrective action plan. Consider issues like response time, service, and relationship between vendors.

Aim for Just-in-Time Manufacturing
ASIC manufacturing can present a dilemma for smaller companies. On the one hand, producing larger quantities allows reduced costs and improved quality. On the other hand, producing larger quantities requires handling ASIC stock with special conditions.

Start by analysing the longevity and cumulative volume expectations of your product. Then, assuming you don’t have the facilities, resources and conditions to store chips, try to plan for ‘just-in-time’ ASIC delivery.

Start with Quality, Then Price
At some point, every company that markets a product containing ASIC faces the manufacturing dilemma – how to go into production using the cheapest, most efficient and highest quality methods? Is it using an external full-turnkey partner or taking full ownership and working directly with semiconductor suppliers (Customer Owned Tooling, or COT model).

Each model has pros and cons. As an earlier stage company, cutting production costs may be one of your priorities. Nevertheless, you still need to focus on your design core competencies rather than take the full burden of manufacturing. Best is if you can find a hybrid, ASIC to COT model, which offers the best of both worlds.

Learn More
Read the full e-book, 5 Best Practices for Successfully Managing an ASIC Supply Chain

 


Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
by Mike Gianfagna on 03-23-2020 at 6:00 am

FINAL2 Digital FF iSpatial Flow hi res

Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one reason why a recent press release from Cadence regarding the new release of their digital full flow caught my attention.

The press release details the features of the new digital full flow release, which further optimizes power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and AI. According to the press release, “the flow features multiple industry-first capabilities including unified placement and physical optimization engines plus machine learning (ML) capabilities, enabling design excellence with up to 3X faster throughput and up to 20% improved PPA.”

Another key feature of the new release is iSpatial technology, which Cadence defines as follows: “The iSpatial technology integrates the Innovus™ Implementation System’s GigaPlace™ Placement Engine and the GigaOpt™ Optimizer into the Genus™ Synthesis Solution, providing techniques such as layer assignment, useful clock skew and via pillars. The iSpatial technology allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database.”

There are many significant capabilities discussed and results presented in the press release.  I’d like to focus on the ML capabilities. In my previously mentioned post about Cadence, Paul Cunningham detailed the strategies Cadence uses for ML deployment.  One was “ML inside”, where heuristic algorithms improve thanks to ML and another is “ML outside” where tools learn from prior runs in order to improve future results. It’s interesting to watch a strategy be used in an actual product, and it seemed to me this press release was announcing just that regarding AI/ML.

I got a chance to speak with Kam Kittrell, senior product management group director in the Digital & Signoff Group at Cadence about the press release and my hunch about AI/ML strategy implementation.  It turns out the “unified placement and physical optimization engines plus machine learning” are primarily an application of “ML inside”, allowing the tool to do a better job predicting things like downstream delays and congestion. There is also an element of “ML outside” here as well since the flow can train with the details of a particular user’s design – things like libraries and delay settings, so the optimization takes on a design-specific focus. Hearing about a comprehensive strategy on AI/ML one week and then seeing it in action the following week is noteworthy.

The press release includes detailed quotes from MediaTek and Samsung executives about how ML is used for real designs and what results are delivered. Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence also comments on the impact the new flow release is having on customers. Another memorable quote came from Kam during my discussion with him. Regarding the importance of PPA optimization, which is an industry-wide focus, Kam pointed out that “millions of dollars are spent on tens of picoseconds”. I felt this comment accurately captured the dramatic numbers that characterize SoC design.

You can learn more about Cadence digital design and signoff capabilities here. You will find lots of good resources, including a discussion of all the steps in the design flow as well as videos and relevant articles.

 


A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law

A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law
by Daniel Nenni on 03-22-2020 at 10:00 am

Cover Predicting Trends

Wally Rhines is one of the most prolific speakers the semiconductor industry has ever experienced. Wally is also one of the most read bloggers on SemiWiki.com, sharing his life’s story which is captured in his first book: From Wild West to Modern Life the Semiconductor Evolution.

On April 2nd at 10am PDT we will host Wally on a live webinar for a presentation on his second book which will be made available for download during the event. There will also be a live Q&A. If you cannot attend the live version a link to the replay will be sent to all registrants. If you are not available to attend and want to ask Wally a question please include it in the comments section and I will make sure it gets answered. This is a must attend event, absolutely!

REGISTER HERE FOR REPLAY

Let’s start with Wally’s updated biography, yes he has a Wikipedia page, followed by the book introduction:

Wally Rhines is widely recognized as an expert in business value creation and technology for the semiconductor and electronic design automation (EDA) industries.

Dr. Rhines was CEO of Mentor Graphics (a “Big Three” EDA company with $1.3B+ revenue) for 24 years, has served on the boards of four public companies, managed the semiconductor business of Texas Instruments (TI), and is a spokesperson, writer and highly-sought-after speaker for the high-tech industry delivering more than twenty keynotes per year.

Dr. Rhines currently serves as CEO Emeritus of Mentor, a Siemens Business, consults for investors, corporations and the U.S. government on strategic directions, value creation and technology and serves on public and private boards.

Business achievements include major turnarounds, both at Texas Instruments, through his creation and management of the digital signal processing business, and at Mentor, where he managed more than 3X growth in revenue and a 10X increase in enterprise value before acquisition by Siemens AG.

Dr. Rhines’ technical expertise includes semiconductor design, process engineering and manufacturing as well as financial modeling of trends and value creation.

He has been deeply involved in global business development including projects in China and India.

As CEO and Director, he has managed businesses through difficulties including unfriendly takeover attempts, favorable outcomes for both the company and the activists, with three of the world’s leading activist investors, and volatile economic and business cycles.

He continues to seek new opportunities to grow businesses, particularly through private equity, consulting and personal investing.

https://en.wikipedia.org/wiki/Wally_Rhines

REGISTER HERE FOR REPLAY

Predicting Semiconductor Business Trends After Moore’s Law

Introduction
In 1952, AT&T sold licenses to patents and basic know-how for their newly developed solid-state transistor technology to any buyer willing to pay $50,000. As a result, the companies who chose to commercialize this technology competed on a level playing field with no initial competitive barriers such as patents or existing market share. They created what soon became the most significant example of a free market business operating in a world economy. Regulations for this new industry didn’t exist and the new companies created a hotbed of new ideas, new business approaches and financial growth. It was the “Wild West” of business. As a result, the semiconductor industry today provides the most significant example in recent history of free economics in worldwide commerce.

Without a formal licensing process, IBM’s development of the Winchester disk drive had a similar effect beginning in 1956. Over the next thirty years, the number of companies competing in the hard disk drive business peaked at eighty-five. Clayton Christensen of Harvard University did a study of the disk drive industry because it could be analyzed using nearly ideal conditions of supply, demand and free market economics (see Christensen, Clayton, “The Innovator’s Dilemma: When New Technologies Cause Great Firms to Fail”, Harvard Business Review Press, May 1, 1997.)

He used disk drive companies as a surrogate for other industries in the same way that biological researchers use fruit flies. Fruit flies are born, mature, reproduce and die in 24 hours so you can study biological effects over many generations. Christensen’s thesis was that the disk drive industry provided a research vehicle similar to fruit flies in that these companies were founded, grew and went out of business in a very short period of time.

The semiconductor industry exhibited life cycles that were longer than the disk drive industry but had the same free market characteristics. Over time this unfettered competition followed trends in a worldwide market that could be quantified and used to predict the future. Over the past forty years or more, I’ve collected data and made presentations showing how the actual economics and technology of the semiconductor industry can be used to predict its future direction and magnitude. This book is built upon excerpts of presentations made during the last thirty years that analyze the business and technology of the semiconductor industry. In most cases, the figures in the book are copies of the original slides as they were presented during one or more of those presentations. In general, they show how predictable the semiconductor industry has been. They should also provide insight into the future of the industry.

—Dr. Walden Rhines, December 2019

REGISTER HERE


Semiconductor COVID-19 Update!

Semiconductor COVID-19 Update!
by Mark Dyson on 03-22-2020 at 10:00 am

COVID 19 Semiconductors SemiWiki

Last week whilst China started to recover from COVID-19 outbreak, the rest of the world was seriously impacted by the growing number of cases as the number of cases and deaths outside of China grew higher than in China. With the rise, many governments around the world belatedly put in measures to prevent the further spread of the virus, ranging from lock downs to closing borders. This had a serious impact on the whole business world including semiconductors.

Here in South East Asia, on Monday evening, Malaysia announced it was implementing a Movement Control Order effective from March 18th until March 31st. This would restrict the entry of non Malaysians into the country, and prevented Malaysians from travelling outside of the country as well as restricted movement within the country, to prevent the spread of the virus. The order also instructed the shutdown all but essential businesses to close, amongst other measures. This affected the semiconductor industry in both Malaysia and Singapore.

Initially the semiconductor industry was not on the essential industry list for Malaysia, and so companies prepared to shutdown by Wednesday 18th. Then just before midnight on the 17th, the government added electronics and semiconductors to the essential industry list but companies were only allowed to operate with minimum workforce, so companies scrambled to restart operations, and get the workforce back though not with a full workforce.

The order also impacted Singapore’s semiconductor industry as over 300,000 Malaysians cross the border every day to work in Singapore, many of whom work in the semiconductor industry. On Tuesday when workers arrived at work, they were told to go home and pack for 2 weeks and come back before midnight whilst companies scrambled to find accommodation for the workers for 2 weeks. This caused huge jams on the Causeway. Whilst not all could arrange or not all employees wanted or could stay in Singapore most companies managed to secure enough workforce to maintain production.

Whilst the rest of the world goes into lock down, China is slowly opening up again from it’s lockdown. Xiaomi announced that 80% of it’s supply chain is operational ahead of it’s new 5G phone launch. Also Hon Hai (Foxconn), one of Apples main suppliers, is reported to have begun re-opening it’s factories in Wuhan, after it received approval from the local government.

Whilst China is recovering, and reporting zero local cases, there are still a lot of precautions being taken in China to prevent the re-occurrence of the virus, and the Chinese are taking these in their stride.

Elsewhere in Asia, Taiwan, Singapore and Hong Kong have managed to so far “contain” the outbreak by implementing the lessons learnt from SARS. All the countries started to put in place measures from mid January and although the countries are seeing an increase in the number of cases, most of these are imported and so far have managed to keep the number of new cases per day to double digits, unlike many other countries around the world which are seeing exponential rises.

In Taiwan they are using big data to help contain the outbreak, they have linked their health insurance service the immigration data so they know where people have travelled, and they have fixed the price of face masks and people use their insurance cards to buy their allowance from allocated pharmacies across the island, who can check if the person has used their allowance nad also where they have travelled. As a result most people have access to face masks and most people working in companies wear them all the time at work and outside. Despite these precautions it can not totally stop the spread, TSMC reported that one of their workers was infected this week and they quarantined their co-workers.

In Singapore the government raised the alert level to DORSCON Orange very early on February 7th after just 29 cases were reported, this caused fear amongst it’s neighbouring counties that Singapore was a danger country but by raising the level so early they have prevented the numbers to grow exponentially so far. Singapore has been diligently following a process of contact tracing for every person affected by the virus, to track down and quarantine people that they have been in contact with. Over 5000 people have been quarantined to date, many of them already released without catching the disease. They also have been strictly enforcing restrictions and have imposed severe penalties on those and their employers that break the restrictions. Here is an article from the BBC that explains the level of detail that Singapore goes through to contain the virus.

The impact on the economy is forecast to be very severe. Market research company IDC has evaluated various scenarios based on how long the outbreak lasts as to the impact on the world semiconductor market. They say there is a 80% chance that the market will contract in 2020 compared to 2019 instead og the previously expected growth. The most likely scenario is that world semiconductor market revenue will decrease -6% in 2020.

Whilst SEMI has published a blog on the latest market indicators which are generally already pointing down.

Over 150 companies have reported earning hit due to COVID-19 many of which are semiconductor and electronics companies.

Mobile phone sales in February are reported to have collapsed -38% yoy dropping from 99.2million a year ago to only 61.8million in Feb 2020. With Samsung reporting slow initial sales of it’s newly launched S20 flagship phone. Samsung have told shareholders that the coronavirus pandemic would hurt sales of smartphones and consumer electronics this year, while demand from data centers would fuel a recovery in memory chip markets.

Sales in the auto industry have also been badly hit and now car manufacturing plants around the world are shutting down as supply chains dry up, with all the major automakers in US and Europe declaring temporary shutdowns and halt production. This doesn’t bode well for those companies that rely on the automotive market.

With so many people working from home there are many warnings out about the dangers of hackers seeking to take advantage and infiltrate companies during this outbreak. At Cisco the numbers of security support requests to support remote workforces have jumped 10x in the last few weeks.

Business is business and keeps economy afloat but without healthy workers there is no business, so please do follow all the restrictions to stop the spread not just to the letter of the law but also follow the spirit behind the restrictions. Yes the restrictions can put some temporary hardships on your life but if we all follow them then we can beat this virus, it’s better than ignoring them and having worse consequences. This is a good video explaining the need for social distancing, and how by following it can help avoid deaths. With all the advice to stop touching your face, you still touch it. Here is an video by the BBC that explains the reasons why we touch our face and gives ideas how to stop yourself. Also here is a simple guide to the COVID-19 symptoms and how to prevent catching and spreading the disease.

So please stay safe out there and behave as if you already have symptoms even if you feel fine. Let’s not spread this virus and together we can beat it.

Related Blog


The End of Mobility as We Know It

The End of Mobility as We Know It
by Roger C. Lanctot on 03-22-2020 at 8:00 am

The End of Mobility as We Know It

The hideous reality of the coronavirus has exposed the hideous realities of the mobility industry with sobering implications for all. At its core, mobility is about moving people in the safest, most efficient, and cost effective ways and suddenly citizens around the world are being told to stop moving and stop congregating.

Ride hailing operators Uber and Lyft have suspended carpooling. Uber also offered drivers suffering symptoms two weeks of paid leave. Both moves reflected the fig leaf-flinging efforts of governments to forestall the pandemic’s spread and mitigate its impact.

The transportation proposition of an app-based taxi ride delivered by an itinerant non-employee driver has finally fully been exposed for all its frailty. There is no protection for driver or passenger in a pandemic. There is no commitment to a particular level of service or safety. There never was.

Uber took the further step of suspending fees for food delivery and Lyft stopped hiring drivers in order to preserve what little demand was left for current drivers. But whatever they may announce, these profit-less operators are looking more precarious than ever.

The onset of COVID-19, though, has called into question the appropriateness of getting into any car that isn’t your own with someone you don’t know – either a driver or a driver and another passenger. This has further called into doubt the wisdom of public transportation itself and the hygiene associated with flying in airplanes or checking into hotel rooms.

The impact has been immediate and will have both long and short-term consequences. For the travel industry as a whole, the onset of the COVID-19 pandemic has been stunning as hotels are closing while local governments consider requisitioning them for hospital space.

Airlines in the U.S. are seeking government bailouts while Italy prepares to nationalize Alitalia – and France considers similar measures for Air France. Rental car companies, dependent as many are on airport traffic, have looked on helpless as business has evaporated.

The underlying goal of most mobility operators as well as regulators, legislators, and transportation authorities for the past five years has been to increase the number of passengers in both public and private conveyances to reduce congestion and emissions. With economic activity grinding to a halt there is now no congestion and satellite photography has shown us all that emissions are suddenly less of a problem globally – but especially in hard hit areas. The skies are clearing.

It’s hard to find such nuggets of good news in the morass of misery unfolding around the world. Multiple tolling agencies have closed or gone virtual suspending toll collections or shifting immediately to electronic tolling. And the price of gasoline is plunging along with everything else – so that’s good news, right?

Public transit agencies have been especially hard hit – confronted as they are with the need to maintain operations while simultaneously seeking to discourage crowding. This has resulted in service cutbacks and contradictory efforts to limit the use of transportation services to medical or personal necessity – suggesting that public transportation will primarily be transporting sick people. That, alone, should serve as a sufficient deterrent to crowds on the platforms and at bus stops.

Car sharing, ride hailing, and taxi operators have begun disinfecting their vehicles between rides – and even used car sales operations have begun offering disinfection as a service. The final nail in the transportation coffin has been the widening stoppage of vehicle production – as was seen in China two months before (where manufacturers have recently begun ramping back up).

With public transportation winding down, micromobility has taken on greater appeal, which is likely to cause municipalities to reconsider their limitations on shared scooters and bikes. For automotive-centric operators the challenge remains one of disinfecting and distancing where possible – but the stress of a multiple-month shutdown may be challenging for taxi and rental car companies.

Car sharing and ride hailing operators with significant leverage are likely to see their prospects for profitable operation or even survival severely tested. Consolidation among taxi operators seems inevitable. Uber may see it fit to sell off its India operations to Ola – both companies are Softbank investments.

The concept of autonomy in the form of robotaxis has its appeal – but not in the context of a shared space with no provision for cleaning and disinfecting the vehicle between rides. We humans are good for something, after all. We’ll be thinking a little differently about sharing rides in the future.

Car makers are still advertising new car sales, but many new car dealers around the world have suspended operations. These developments highlight the behavioral sacrifices and compromises we normally routinely make to move en masse to work and play. In a few months we will be asking ourselves to rekindle those damaged instincts and rejoin the literal human race – the herd – to get where we need to go.

Things will look the same, but they will never be the same. There will be more gloves and more masks and, maybe, more politeness. Let’s try to remember what this period right now is like when, a year from now, we are once again getting into a dodgy looking taxi or crammed into a subway or tram.

With a little luck and foresight these public transportation spaces may be a little cleaner as operators embrace the heightened expectation for disinfection and safety. We really should have been paying attention to these issues all along. Who can forget their first visit to Tokyo and the gloved handed taxi drivers with their cars with self-opening and closing doors. I’m looking forward to that future while I hunker down to ride out the pandemic.


TSMC 32Mb Embedded STT-MRAM at ISSCC2020

TSMC 32Mb Embedded STT-MRAM at ISSCC2020
by Don Draper on 03-20-2020 at 6:00 am

Fig. 1. Cross section of the STT MRAM bit cell in BEOL metallization layers between M1 and M5.

32Mb Embedded STT-MRAM in ULL 22nm CMOS Achieves 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150C and High Immunity to Magnetic Field Interference presented at ISSCC2020

1.  Motivation for STT-MRAM in Ultra-Low-Leakage 22nm Process

TSMC’s embedded Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) offers significant advantages compared to Flash Non-Volatile Memory (NVM).  Flash requires 12 or more extra masks, is implemented in the silicon substrate and is page mode write alterable.  STT-MRAM on the other hand is implemented in the Back-End-Of-Line (BEOL) metallization as shown in Fig. 1, requires only 2-5 extra masks and is byte-alterable.

This implementation in TSMC’s 22nm Ultra-Low-Leakage (ULL) CMOS process has a very high read speed of 10ns, and read power of 0.8mA/MHz-bit. It has 100K cycle write endurance for 32Mb code and 1M cycle endurance for 1Mb data. It supports data retention for IR reflow at 260C of 90 seconds and 10 years data retention at 150C.  It is implemented in a  very small 1transistor-1resistor (1T1R) 0.046 mm2 bit cell and has a very low leakage current of 55mA at 25C for the 32Mb array equivalent to 1.7E-12A/bit when in Low Power Standby Mode (LPSM).  It utilizes a sensing scheme with per-sense amp trimming and 1T4R reference cell.

 

Fig. 1. Cross-section of the STT-MRAM bit cell in BEOL metallization layers between M1 and M5.

2.  1Transistor-1Resistor MRAM Bit Cell Operation and Array Structure
To reduce parasitic resistance on the write current path, a two-column common source line (CSL) array structure is employed as shown.

Fig. 2. Schematic of the 1T1R bit cell in the array of 512b column with the 2-column CSL

The word line is over-driven by a charge pump to provide sufficient switching current of hundred’s of mA for write operation requiring the unselected bit lines to be biased at a “write-inhibit voltage” (VINHIBIT) to prevent excess voltage stress on the access transistors of the  unselected columns of the selected row. To reduce bit line leakage of the access transistor on unselected word lines, the word line has a negative voltage bias (VNEG). The biasing of the array structure for reading, write-0 and write-1 is shown in Fig. 3.

Fig. 3. Cell array structure biasing for word lines and bit lines for read, write-0 and write-1 operations.

3.  Read Operation, Sense Amplifier and Word-Line Voltage System
For fast, low-energy wake-up from LPSM to enable high-speed read access, a fine-grained power gating circuit (one per 128 rows) with a two-step wakeup is used as shown in Fig. 4.  The power switch consists of two switches, one for the chip power supply VDD and the other for a regulated voltage from the Low Drop-Out (LDO) regulator supplying VREG.  The VDD switch is turned on first to pre-charge the WL driver’s power rail, then the VREG switch is turned on to raise the level to the targeted level, which achieves fast wake-up of <100ns while minimizing the transient current from VREG LDO.

Fig. 4. Fine-grained power gating circuit (one per 128 rows) with two-step wake-up.

The Tunnel Magnetoresistance Ratio (TMR) house curve shown in Fig. 5 is the ratio between the antiparallel resistance state Rap to the parallel resistance state Rp  as a function of voltage, showing lower TMR and smaller read window at higher temperatures.

Fig. 5 House curve of TMR showing the reduced window for read at 125C

The resistance distributions of the Rap and the Rstates which, when including the bitline metal resistance and the access transistor resistance, determine the total read-path resistance showing the proportional reduction in the difference between the two states which the sense amp needs to measure to determine the bit value, as shown in Fig. 6.

Fig. 6. Distribution of resistance values for the anti-parallel Rap and the parallel Rp states and including the metal bit line and access transistor resistances showing the proportional reduction in the difference between the two states that needs to be detected by the sense amp.

To sense the resistance of the MTJ, the voltage across it during read must be clamped by transistors N1 and N2 to a low value to avoid read-disturb  and is trimmed to cancel the sense amp and reference current offset. The reference resistance is formed by the 1T4R configuration  R~(Rp +Rap)/2  + R1T as shown in Fig. 7.

Fig. 7.  Sense amp with trimming capability showing the read clamp voltage on transistors N1 and N2  to prevent read disturb. Reference R~(Rp +Rap)/2  + R1T

This configuration is able to achieve a read speed of less than 10ns at 125C as shown in the sensing timing diagram and shmoo plot Fig. 8.

Fig. 8.  Sensing timing diagram and read access shmoo plot at 125C.

4.  MRAM write operation
MRAM write of the parallel low resistance state, Rp and the higher resistance anti-parallel state Rap requires bi-directional write operation shown in Fig. 9. To write the Rap state to the Rp requires biasing the Bl to VPP, the WL to VREG_W0 and the SL to 0 to write the 0 state.    To write the 1 state, writing the Rp  state  to the Rap  state  requires current in the other direction, with the BL at  0, the SL at VPP and the WL at VREG_W1.

Fig. 9. Bi-directional Write for the parallel low resistance state, Rp and the higher resistance anti-parallel state Rap

For data retention during IR reflow at 260C for 90sec, an MTJ with a high energy barrier Eb is needed. This requires an increase in the MTJ switching current to hundreds of mA needed for reliable writing.  The write voltage is temperature compensated and a charge pump generates a positive voltage for selected cells and a negative voltage for unselected word lines to suppress bit line leakage at high temperatures. The write voltage system is shown in Fig. 10.

Fig. 10 Showing the over-drive of the WL and BL/SL by the charge pump and the temperature compensated write bias

Temperature compensation for write voltage is required for operation with a wide temperature range.  The write voltage shmoos from -40C to 125C are shown in Fig. 11 where the F/P blocks show fail at -40C while passing at 125C.

Fig. 11. Showing requirement for temperature compensation during write.

A BIST module with standard JTAG interface implements self-repair and self-trimming to facilitate test flow. The memory controller TMC implementing the Double Error Correction ECC (DECECC) shown in Fig. 12.

Fig. 12. BIST and Controller for self-repair and self-trimming during test and implementing DECECC.

The TMC implements the smart write algorithm which implements bias setup and verify/retry time for high write endurance (>1M cycles). It contains read-before-write to decide which bits need to be written and dynamic group-write to improve write throughput, multi-pulse write with write verify and optimizes write voltage for high endurance. The algorithm is shown in Fig. 13.

Fig. 13. Smart write algorithm showing dynamic group write and multi-pulse write with write verify.

5.  Reliability Data, Key Features and Die Photo

Fig. 14.  The write endurance test shows that the 32Mb chip access times and the read currents are stable before and after 100K -40C write cycles.

Fig. 15.  The write endurance bit error rate is less than 1 ppm at -40C after 1M cycles.

Fig. 16. The increased thermal stability barrier Egoverning temperature dependence of data retention shows more than 10 years data retention at 150C, 1ppm.

Magnetic field interference is a potential concern in many applications for spin-based STT-MRAM. The solution is a 0.3mm thick magnetic shield deposited on the package as shown in Fig. 16 showing that in a field strength of 3500Oe of a commercial wireless charger for mobile devices the bit error rate of 100 hour exposure can be reduced from >1E6ppm to ~1ppm. Also, more than 10 years of data retention at 125C was shown at a magnetic field of 650 Oe.

Fig. 17. Sensitivity to a magnetic field of 3500 Oe reduced by a factor of 1E6.

Conclusions
The 22nm ULL 32Mb high-density MRAM has very low power, high read speed, very high data retention and endurance  suitable for a wide range of applications. With a cell size of only 0.0456mm 2 , it has a read speed of 10ns and a read power of 0.8 mA/MHz/b and in low-power standby mode (LPSB) it has leakage less than 55mA at 25C, equivalent to 1.7 E-12 A/bit leakage. For 32Mb code, it has an endurance of 100K cycles and for 1Mb data >1M cycles.  It has a capability of 90sec data retention under IR reflow at  260C and a long-term retention of > 10 years at 150C. The product spec is shown in Fig. 18 and die photo in Fig. 19.

Fig. 18.  Summary table of N22 MRAM specification and die photo.

Fig. 19.   32Mb high-density MRAM macro in the 22nm Ultra-Low-Leakage CMOS process.


Hyper-Scaling Of Data Centers – Environmental Impact Of The Carbon ‘Cloud’

Hyper-Scaling Of Data Centers – Environmental Impact Of The Carbon ‘Cloud’
by Stephen Crosher on 03-19-2020 at 10:00 am

Stephen Crosher Moortec CEO Square High Res

It is predicted that by 2030 energy consumption attributable to data centers will make up a staggering 8% of the world’s total usage!

As we move in to 2020 it’s clear that every sector of industry, including the semiconductor industry, will have a responsibility to address growing environmental concerns. We should be aware that as our sector underpins the growth in AI, 5G telecommunications, crypto-currency and high performance compute applications, it is predicted that by 2030 energy consumption attributable to data centers will make up a staggering 8% of the world’s total usage. Data centers are fast becoming one of the big consumers alongside lighting, domestic heating/cooling and transportation.

What will happen next?
My prediction for 2020 is that we will see greater governmental involvement in how carbon emission targets are levied upon different industrial sectors, technology applications, and in particular, data centers. As the so called ‘evolved economies’ around the world gradually respond to the pending climate crisis I believe we could see a growth in data centers being located in ‘less evolved’ economic regions where emission levels are scrutinised less and incentives for reduced energy consumption are less apparent.

Today, we know that there is a vicious cycle to data center energy consumption. Approximately 40% being consumed through high performance compute activity, which in turn generates heat at the chip, board and system levels. However, a further 40% of energy is being consumed through subsequent cooling and thermal management. As society demands more computational capacity, so a two-fold energy demand is generated.

Taking responsibility…
For the semiconductor industry and associated technologies to grow responsibly we need seek innovative ways to reduce our energy consumption, hence optimise from the physical chip level up to overall data center deployment.

By understanding and accurately measuring thermal, supply and process conditions deep within our semiconductor devices we are able to control and therefore reduce overall data center consumption. By also harnessing mission mode in-chip analytics for optimisation, we can invoke further reduction to our carbon ‘cloud’ emissions. So in 2020, I believe that narratives from environmentalists like Greta Thunberg and subsequently the action taken by governments around the world, will see the semiconductor industry respond by helping to tackle our new existential challenge.

To read previous “Talking Sense with Moortec” Blogs click HERE

Watch out for our next blog entitled Talking Sense with Moortec … Key Applications for In-Chip Monitoring which will be dropping late March!

About Moortec
Moortec have been providing innovative embedded subsystem IP solutions for over a decade, empowering customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm and 5nm. Moortec in-chip sensing products support the semiconductor design community’s demands for enhanced performance optimization and increased device reliability, helping to bring product success by differentiating the customers’ technology. With a worldclass design team, excellent support and a rapidly expanding global customer base, Moortec are the go-to leaders in innovative in-chip technologies for the automotive, consumer, high performance computing, mobile and telecommunications market sectors.

For more information please contact Ramsay Allen ramsay.allen@moortec.com, +44 1752 875130, visit www.moortec.com and follow us on Twitter and LinkedIn.