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System Level Flows for SoC Architecture Analysis and Design – DVCON 2020

System Level Flows for SoC Architecture Analysis and Design – DVCON 2020
by Daniel Nenni on 02-21-2020 at 6:00 am
Categories: CircuitSutra, Intel Foundry, Semiconductor Services

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As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.

System Level Flows for SoC Architecture Analysis and Design

Speakers:
Swaminathan Ramachandran – CircuitSutra Technologies Pvt. Ltd.
Umesh Sisodia – CircuitSutra Technologies Pvt. Ltd.
Prassana Sadananda Rao – Intel Corp.

Organizer:
Umesh Sisodia – CircuitSutra Technologies Pvt. Ltd.

This workshop covers the latest trends and best practices in the domain of ESL methodologies for SoC Architecture, Co-Design, Co-Verification & raising the abstraction of chip design through High Level Synthesis. These advanced flows are enabled by using C, C++, SystemC, TLM2.0 along with traditional RTL flows.

Talk 1: Defining a SystemC Methodology for your Company
Swaminathan Ramachandran, CircuitSutra Technologies

As SystemC gains popularity in the fields of architecture evaluation, virtual platform development, SoC level verification, etc., more teams and companies want to explore, experiment and deploy it for their modeling use cases. While SystemC library provides the vocabulary and the nuts and bolts to build a useful and diverse set of models, it is sometimes too low level to be immediately useful. What is needed is a SystemC library analogous to Boost libraries in C++, for building blocks like memories, buses, registers, timers, etc. along with the infrastructure to quickly stitch them together into a working platform asap. Most of the Semiconductor companies who have successfully deployed SystemC, have developed their own tool independent methodology on top of SystemC, and they use it together with advanced modeling tools from EDA vendors. Such a library usually starts with basic building blocks, and over a period of time becomes a very rich collection of re-usable modeling components that can be re-used across various IP models, SoC variants, Modeling Use cases, business units, etc.

Any company looking to adopt SystemC in their flows should carefully conceptualize the development of such a methodology inhouse and can learn from the best practices being followed in the Industry. In this presentation, we will talk about what should be the content of such a methodology/library and how it should be conceptualized.

CircuitSutra has worked with leading semiconductor companies for more than a decade now and has participated in modeling projects from the stage of experimentation to pilot projects and to widespread adoption. We have an in-depth understanding of the best practices followed in the modeling domain.

Talk 2: System Flows in a “hybrid” Environment – Intel’s  Approach
Prassana Sadananda Rao – Intel Corp.

The validation of SOCs at System level with full FW/SW stack in the pre-silicon stage itself is essential to accelerate SW readiness, improve RTL quality and overall shorten the product development cycle.

SoC FPGAs and Virtual Platforms (VP) are amongst the standard de-fact pre-Si solutions, However, each comes with its pro and cons: SoC FPGA has RTL accuracy but is available only after SoC integration is completed. VP arrives early but is more of an architectural model rather than RTL instantiation.  To address this problem, our work describes an alternative leading-edge solution that starts at IP level itself. Single IP FPGA integrated into Virtual Platform (i.e., Hybrid IP-FPGA). Such a solution has the advantage of being available as soon as VP is ready. At the same time, it provides the IP RTL design with the necessary system-level context (i.e., interaction with FW/SW/Drivers of other components) which allows an early validation of IP design in an integrated environment instead of in isolation/standalone mode.

As a case study, we would present the results achieved on a complex PCI IP responsible for audio and sensing processing being integrated into one of the latest Intel SoC platforms. The IP was mapped to an IP FPGA, the SoC is modeled as a loosely timed Virtual Prototype and a hybrid layer plays the role of the glue logic for the two technologies. The overall Hybrid IP FPGA solution is proven to have a production level maturity that allowed the validation of complex system-level flows, such as security handshakes and power state transitions (reboot, S3, S4, and S5). Our case-study utilized only production-level SW/FW (the same that will be used on the real silicon) and enabled a tight interaction between the FPGA and other IPs of the platform thus exercising system-level flows which would be only visible when silicon is in the lab. This work set the foundation for making VP as the backbone of standalone IP RTL integration and candidates the proposed methodology as a breakthrough player in the pre-Si validation strategy of new SoC programs.

We will also discuss the challenges we faced while developing such a new methodology. In particular, the extra requirements that the VP model must satisfy to seamlessly integrate the hardware of the FPGA. As an example, the logic associated with the low-level hardware signals crossing the cutline of the two technologies must be modeled on VP with RTL accuracy in order to cope with FPGA expectations. Our future focus will be on developing VP interfaces in a scalable way to productize and scale such hybrid technology over a large set of different IPs.

Talk 3: Using High-Level Synthesis to Migrate Software Algorithms to Semiconductor Chip Designs
Umesh Sisodia, CircuitSutra Technologies

High-Level Synthesis (HLS) raises the abstraction of chip design beyond RTL. It enables the implementation of design functionality in high-level languages like C++/SystemC, and generates corresponding RTL using HLS tools. Synthesizable C++/SystemC code for design is very concise as compared to equivalent RTL code for the same design. Moreover, simulation of C++/SystemC models is much faster compared to RTL simulation. This allows significant productivity gains in the design and verification process.  HLS also allows separation of functionality from architecture constraints and technology parameters, thus permitting code re-use across different variants of semiconductor chips, or across FPGA and ASICs.

HLS flows are more effective for algorithm centric designs. Nowadays we see new chip design requirements for emerging domains like 5G, Deep Learning, Vision, Image Processing, Speech, Audio processing etc. In these domains, there are many algorithms implemented in software, and several of these are available as open source.

In this talk, we will present an HLS based methodology to quickly migrate a software algorithm implemented in plain C/C++ to a hardware implementation in RTL for semiconductor chips (FPGA or ASIC). We will also cover a verification flow that allows the reuse of the original test suite of the software algorithm to verify the synthesizable C++/SystemC model as well as the final RTL. The untimed C++/SystemC models are also suitable to be used in Virtual Platforms, that allows embedded software development much before the chip is designed.

This methodology accelerates the pace of innovation, enables faster rollout of new chips, permits experimentation by quickly trying out the functionality in software and hardware, and taking high-level architecture decisions much earlier in the cycle.

Talk 4: SystemC Methodology for RISC-V Ecosystem
Umesh Sisodia, CircuitSutra Technologies

SystemC is a C++ library created for design and verification at the SoC and system level. It is widely used in the industry for system-level modeling, virtual prototyping, hardware-software co-verification, architecture & performance modeling, high-level synthesis, and functional verification.

RISC-V is an open-source processor ISA. Given that RISC-V ecosystem is in a nascent stage, yet there is widespread interest in the industry to explore the usage of RISC-V for various use cases. A robust modeling eco-system is necessary for the successful adoption of a new ISA, and in this context, a need exists for SystemC modeling infrastructure for RISC-V ecosystem. In this presentation, we will talk about some essential components required for anyone trying to deploy SystemC based methodologies for their RISC-V project.

CircuitSutra is an Electronics System Level (ESL) design IP and services company, headquartered in India, having development centers in Noida and Bangalore, and serves the customers worldwide. It enables customers to adopt advanced methodologies based on C, C++, SystemC, TLM, IP-XACT, UVM-SystemC, SystemC-AMS, Verilog-AMS. Its core competencies include Virtual Prototype (Development, Verification, Deployment), Architecture & Performance modeling, Co-simulation, Co-emulation, HLS, SoC & System verification.

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Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability

Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability
by Tom Simon on 02-20-2020 at 10:00 am
Categories: EDA, Events, Magwel

PTM-ET Sidecut view

PowerMOS devices play a major role in a variety of power converter and control circuits. Some examples of their applications include PMICs, or boost and buck converters. Often these are used in mobile and IoT devices to convert battery voltages to circuit operating voltages.

Due to their size and internal complexity PowerMOS devices have to be analyzed as hundreds or perhaps thousands of smaller devices, connected by a complex web of metallization. The first and most significant effect of this is non-uniform switching, with gate voltage varying across the device during device turn on. This in turn leads to Ids concentrating in some areas and not others.

Transient electrical analysis is capable of showing detailed gate voltages and current densities during the transitions, when devices typically experience their highest power draw. However, there is a second dimension to the problem that influences the electrical analysis – intrinsic device behavior is temperature dependent. As a result, device current values will rise as temperature rises, and the reciprocal is true, temperature will rise as more current flows. In the worst case, this vicious cycle may lead to temperature related device failure if the metal melts and shorts out the junction.

The thermal dynamics depend of the properties of the die, the surrounding package and even the board. Uncoupled electrical and thermal analysis will have difficulty converging on an accurate solution at each time step during circuit operation.

Analysis tools are needed to thoroughly model the internal behavior of these complex devices during their operation. Magwel’s PTM-ET tool combines joule heating in the metal interconnect and device junctions with other heat sources and sinks to determine device thermal behavior during circuit activity. PTM-ET concurrently simulates the interdependence between electrical behavior and thermal behavior. PTM-ET’s unique concurrent and dynamic simulation of devices in their packaging with user provided stimulus provides an accurate picture of circuit operation over time.

With the information from PTM-ET, designers can make sure that the optimal packaging has been selected, keeping costs down and also ensuring device reliability. Another advantage of electro-thermal co-simulation is that it can help identify hot spots in the device and guide the placement of sense or replica devices.

Magwel offers a free webinar reply covering the topic of concurrent electro-thermal analysis for PowerMOS devices with the goal of understanding impacts on device operation. The talk by Allan Laser, Magwel Field Application Engineer, discusses the challenges of modeling device behavior and predicting the effects of thermal and electrical factors. Magwel’s PTM® tools work off of device layout and foundry supplied intrinsic device models and produce a comprehensive look at PowerMOS devices.

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Bridging the Gap Between Design and Analysis

Bridging the Gap Between Design and Analysis
by Mike Gianfagna on 02-20-2020 at 6:00 am
Categories: Cadence, EDA, Events
2 Comments

PCB design challenges

At the recent DesignCon 2020 in Santa Clara, Cadence introduced a new product, Sigrity Aurora. You won’t find a press release about this announcement. Rather, Brad Griffin, product management group director at Cadence, presented Sigrity Aurora in the theater at the Cadence booth. This one caught my eye and deserves some discussion. DesignCon has become a system-oriented event. Think chip, package, PC board and chassis. This breadth of problem-solving has created a large and very diverse show floor and technical program.  Relevant, real-world system design challenges are treated here. If you missed it, I highly recommend catching DesignCon next year.

Sigrity Aurora is a product that addresses the signal and power integrity (SI/PI) challenges associated with high-performance PCB design.  The question posed by Brad in his presentation was quite simple – how many times do you iterate between design and analysis in a PC board design?  That is, iteration between the PCB designer and SI/PI engineer? I can tell you from first-hand experience this kind of back-and-forth can waste a lot of time. If you’re not careful, you tie up a very valuable and scarce resource, the SI/PI expert.

The disparate expertise of a PCB designer and an SI/PI engineer contribute to the challenges here. So does a disparate tool flow with lots of conversions and mapping. In his theater presentation, Brad posed a way to address all these issues. What if you had a single vendor solution that could address: schematics, re-route signal and power integrity (SI/PI) analysis, placement, routing, in-design SI/PI analysis and final signoff?

It turns out Cadence has the product breadth to offer such a solution, and that was the essence of the announcement. Thanks to their Sigrity product line, Cadence has an extensive set of analysis engines to address tasks such as screening technology (impedance and coupling checks), return path checking, SI analysis (reflection and crosstalk) and PI analysis (IR drop).

And thanks to the new Sigrity Topology Explorer, pre-route and signal net extraction can be one to support what-if analysis.

The punchline of Brad’s presentation was that all of this capability can now be delivered through the popular Cadence Allegro PCB editing and routing technologies with Sigrity Aurora, which can read and write directly to the Allegro PCB database. A powerful set of analysis engines with a tight and efficient integration to a familiar implementation flow. The applications of such a tool are diverse and significant.  A few scenarios were illustrated in Brad’s presentation as follows.

Screening technology for electrical rules checks (no models required)

Impedance analysis screening:

  • Same requirements on stack-up
  • Global view of results more accessible
  • Look for outliers

Coupling analysis screening:

  • No SI model required
  • Electrical coupling is more accurate than geometrical methods
  • Global view of results

Return path screening:

  • Report nets with possible return path problems
  • Use a figure of merit such as return path quality factor
  • Return path visualization

Signal integrity technology (driven by industry-standard IBIS models)

Reflection analysis output:

Crosstalk analysis output:

Power integrity technology (driven by Allegro PowerTree technology)

IR drop analysis output (IR drop vision can be displayed as voltage, IR drop, or current density):

 

 

 

 

And pulling it all together, system-level simulation for signoff

If you’re engaged in high-performance PCB design, this comprehensive design flow is definitely worth a look.

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Huawei Sends Unmistakable Message

Huawei Sends Unmistakable Message
by Roger C. Lanctot on 02-19-2020 at 10:00 am
Categories: Automotive
4 Comments

Huawei Sends Unmistakable Message

A funny thing happened on the way to Barcelona for the annual Mobile World Congress (MWC) event scheduled for this week. The event organizer – the GSMA – exhibitors and attendees were forced to come to terms with the risk of contracting and spreading the coronavirus – COVID 19.

Several large European, South Korean, and U.S. telecommunications and technology companies made the earliest choice not to attend the event, while Chinese telecommunications and technology suppliers cautioned against hysteria. In the midst of a global technology trade war and the onset of 5G network technology promising massive commercial opportunities for upgrading network gear and handsets, LG and Ericsson were the first two companies to opt out of MWC.

Ericsson rival Nokia announced its own exit from the event days later and a cascade of cancellations followed. But it seemed that Chinese suppliers of equipment, with the exception of early exiter ZTE, were among the most hesitant to cancel – certainly not the first.

The slow decision of Huawei to cancel its participation in MWC, in particular, is an ominous coda to the termination of the 2020 event. Of all technology companies in the world, Huawei ought to have been the first to cancel, particularly considering the company has operations in Wuhan, in Hubei province at the epicenter of the epidemic – the impact of which is still unfolding.

Even after dozens of companies had opted out of MWC in the interest of the health and well-being of their employees and the public in general, Huawei appeared to stay the course. The company noted its own internal measures to quarantine employees and limit travel for those already affected by the virus. But, surely, the announced MWC departures of arch rivals Ericsson and Nokia might have served notice to senior management that it was time to shut down attendance plans.

Unique among all MWC attendees, Huawei was making its decisions while under a political spotlight facing allegations of being a threat to national security from the U.S.  In fact, the U.S. continued to raise these concerns in the past week with European partners during the Munich Conference – a point of contention with European allies less obsessed with potential security threats posed by Huawei.

But Huawei’s behavior during the MWC cancellation brouhaha was telling. Crass commercial interests were clearly prioritized over the safety of Huawei employees or fellow MWC exhibitors or show attendees. It is enough to bring to mind the spate of employee suicides at Foxconn – attributed to unbearable working conditions.

By its decision not to cancel its MWC participation Huawei sent a clear signal to the entire telecommunications and technology industry that commercial interests were paramount. The European Union may be standing by Huawei in the face of U.S. pressure to limit implementation of Huawei 5G equipment on the continent, but Huawei’s lack of concern over the potential spread of COVID 19 – death toll now approaching 2,000 – is a clear warning sign for all and a failure of Huawei’s management.

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High-Level Synthesis at the Edge

High-Level Synthesis at the Edge
by Bernard Murphy on 02-19-2020 at 6:00 am
Categories: AI, EDA, Siemens EDA
1 Comment

AI Traditional Hardware Solutions

Custom AI acceleration continues to gather steam. In the cloud, Alibaba has launched its own custom accelerator, following Amazon and Google. Facebook is in the game too and Microsoft has a significant stake in Graphcore. Intel/Mobileye have a strong lock on edge AI in cars and wireless infrastructure builders are adding AI capabilities to small cells and base stations for 5G. All of these applications depend on a lot of flexibility and future-proofing for long-term relevance in rapidly evolving environments.

But there are many applications, probably accounting for the great majority of units, for which power, cost or transparent use models are much more important metrics. An agricultural monitor in a field in the middle of nowhere, a microwave voice controller, traffic sensors distributed across a large city. For these a general-purpose solution, even a general-purpose AI solution, may be overkill. An application-specific AI function would be much more compelling.

Pre-AI times, you would immediately think of a hardware accelerator – some function that would do whatever it had to do but much faster than running a software equivalent on the CPU. That’s pretty much what an AI accelerator does. It may still be software driven but not in the same way as a general-purpose CPU. Software is developed in Python on a big platform such as TensorFlow or Torch then compiled through multiple steps onto the target accelerator.

Therein lies the magic. That accelerator can be as wild as you want it to be as long as it stays within the general bounds of a neural net architecture. It may support multiple convolution engines, each in turn supported by SRAM for the accelerator as a whole, along with local memories to optimize access for a preferred ordering of operations.

It may support specialized functions for common operations such as pooling. For speed and power, it will commonly support different word widths at different stages of inference and specialized optimizations in handling sparse arrays. These are both hot areas of innovation in neural net architectures, some architects even experimenting with single-bit weights – if a weight can only be 1 or 0, you don’t need multiplication in convolution and sparseness increases!

The challenge in all of this is that you have so many knobs you can turn that it becomes difficult to know where to start or if you have really explored the full space of possibilities when you want to commit to a final architecture. Compounding the problem, you need to test and characterize over a large range of large test-cases – big images, speech samples and so on.

Running the majority of your testing in C rather than RTL is just common sense since it will run orders of magnitude faster and it’s easier to tune than the RTL. Also, neural net algorithms map well through high-level synthesis (HLS), so your C model can be more than a model – it can be the implementation from which you generate the RTL. You can explore the power, performance and area implications of choices you are considering – multiple convolution processors, local memories, word widths, broadcast updates. All with a fast turn-around time, allowing you to more fully explore the range of possible optimizations.

Mentor has just released a white paper with a nice intro on some of the architectural tradeoffs in building such accelerators. You can register to get the paper HERE.

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KLA Blows Away Competition in the Semiconductor Metrology/Inspection Market

KLA Blows Away Competition in the Semiconductor Metrology/Inspection Market
by Robert Castellano on 02-18-2020 at 10:00 am
Categories: Information Network, Semiconductor Services

KLA Blows Away CompetitionC1

KLA saw its share of the semiconductor metrology/inspection market increase from 52% in 2018 to 56% in 2019.

As a background, KLA manufactures and sells equipment used to monitor many of the 400 to 600 processing steps in the manufacturing of semiconductors, starting with a bare wafer, such as silicon, to a completed device. The company makes metrology systems used to measure parameters such as thin film thickness or linewidths, and inspection systems used to detect defects and monitor abnormalities in production.

Except for a small percentage of sales of non-metrology/inspection equipment that came with the acquisition of Orbotech, KLA generates nearly 80% of revenue from metrology/inspection.

According to The Information Network’s report entitled “Metrology, Inspection, and Process Control in VLSI Manufacturing” KLA was the only company among competitors to demonstrate positive growth in 2019. This report analyzes 17 different segments of the overall sector, and there are individual leaders in each of the segments. KLA, of course, with a dominant market share, leads many of the segments.

As shown in the chart below, KLA grew 2% in revenues in 2019. It’s closest competitor, Applied Materials had revenue growth of -10.1% in 2019.

ASML, the dominant lithography market leader, is the leader in the electron beam inspection segment, yet its share of the overall decreased year-on-year 23.3% in 2019.

Nanometrics and Rudolph Technology announced that their merger was finalized in 4Q 2019, (new company named Onto Innovation), but I kept them separated in this chart. Rudolph Technology’s revenue dropped 18.3% YoY and Nanometric’s revenue dropped 16.7% YoY in the metrology/inspection sector.

In the overall metrology/inspection market, KLA increased its share from 52% in 2018 to 56% in 2019. Hitachi High Technologies’ share of the market in 2019 decreased from 10.4% in 2018 to 9.1%. Next was Applied Materials market share decreased from 10.1% to 9.1%.

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IBIS-AMI Back-Channel System Optimization in Practice

IBIS-AMI Back-Channel System Optimization in Practice
by Mike Gianfagna on 02-18-2020 at 6:00 am
Categories: Cadence, EDA, Events

Picture1 1

I recently spent some time at DesignCon 2020 in Santa Clara. For those who haven’t attended this show in a while, you need to go. It’s no longer a small event focused on chip design. It has grown into a true system-level conference, with a broad ecosystem represented on the show floor and in the technical sessions. Ecosystem is an important concept regarding DesignCon.  Many of the technical papers present a collaboration between two or more companies to achieve a particular system design goal.

The first presentation I attended at the show fit this model quite well, with Cadence Design Systems and Marvell Semiconductor presenting a joint modeling and optimization project. The session started at 8:00 AM and the room was almost full – a good indicator of interest in the topic.

Let’s start by unpacking the title of the presentation. IBIS (I/O Buffer Information Specification) is a standard to describe IC input/output analog characteristics. The Algorithmic Modeling Interface (AMI) added the ability to describe the signal processing (algorithmic) portions of channel in a standard way, along with the analog portion. The goals of this work target the development of models that are interoperable, portable, flexible, high-performance, accurate and secure. The addition of a back-channel interface (BCI) specification allows simulation of channels that employ link training, which involves optimizing transmitter characteristics based on receiver observations, sent as messages over the channel.

The presentation included remarks from Steven Parker (senior staff engineer at Marvell) and Jared James (principal product engineer at Cadence).  Their remarks focused on modeling a 56G PAM4 SerDes that was designed by the GLOBALFOUNDRIES team prior to their acquisition by Marvell. Methods to achieve interoperability between different tools using the IBIS-AMI standard were discussed, along with an overview of using the BCI to implement simulations of back-channel optimization. The figure below shows the process flow to implement back-channel training.

From a big picture point of view, the figure below illustrates the predicted improvements in channel performance based on the use of link training.

Results (with and without BCI)

Cadence developed a SerDes model for its Sigrity SystemSI technology using IEEE constructs.  The Marvell model was built using internal tools. Marvell then modified its model to conform to the constructs used by Cadence and a system simulation was then built using the Cadence tools for transmit and the Marvell tools for receive. An excellent example of the cross-platform compatibility offered by IBIS-AMI. Some of the lessons learned from this work include:

  • The need for a command acknowledge function to determine the specific command that caused limits of calibration for the receiver to be reached
  • Consistent command sequence numbering to ensure commands remain in order
  • Setting the timing of commands correctly – too little time and the transmitter may not be able to react, too much and there will be dead time, extending simulation runs

And some comments on potential interoperability improvements:

  • Protocol compatibility improvement: develop de-facto standards to support popular training schemes
  • Open source an API for available models that describes the interface to the model and its files
  • A more general specification from IBIS to handle a broader range of applications

The work presented has been used successfully on several projects. Inter-vendor interoperability can be achieved with proper planning and coordination. This work has broad application going forward, including support for the emerging chiplet market.

 

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The First SiFive Tech Symposiums of 2020 are Fast Approaching – We’ll be in San José, Costa Rica, and Mexico City This Month

The First SiFive Tech Symposiums of 2020 are Fast Approaching – We’ll be in San José, Costa Rica, and Mexico City This Month
by Swamy Irrinki on 02-17-2020 at 10:00 am
Categories: IP, RISC-V, SiFive

Central America and Mexico Tour SiFive SemiWiki

We’re confirming seats for our first two SiFive Tech Symposiums in 2020. The first will take place in San José, Costa Rica on February 25, and the second will be in Mexico City, Mexico, on February 28. Just like our 2019 symposiums, these events are designed to engage the global hardware community in the RISC-V ecosystem, and to further promote the revolution that’s taking place within the semiconductor industry.

We’re proud to have Western Digital is our co-host in Costa Rica, and the Computing Research Center at CIC-IPN is our co-host in Mexico. Both events will feature presentations on RISC-V development tools, platforms, core IP and SoC IP, as well as talks about the exciting opportunities stemming from RISC-V, and the leading-edge research taking place in academia. Both events will also include a hands-on workshop where attendees will have the opportunity to configure their own RISC-V core and bring up on an FPGA.

Attendance is free, but registration is required.

San José, Costa Rica

Co-located with LASCAS 2020

Mexico City, Mexico

Instituto Politécnico Nacional/National Polytechnic Institute of México

The learn more about other SiFive Tech Symposiums taking place throughout the world in 2020, please visit the website, and check back often for updates. We look forward to seeing you soon!

About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 500 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

About SiFive
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.

 

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Mentor at DVCON 2020!

Mentor at DVCON 2020!
by Daniel Nenni on 02-17-2020 at 6:00 am
Categories: EDA, Siemens EDA

DVCon 2020 SemiWiki

Are you ready for the premier conference for functional design and verification of electronic systems?

Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies.

This year at DVCon, you’ll find Mentor experts featured prominently throughout the conference program discussing the latest in Portable Stimulus, UVM, Formal, CDC, Low- Power Verification, High-Level Synthesis, and much more.

A full list of Mentor activities, can be found here.

SPONSORED LUNCHEON
Optimizing Time to Bug, Don’t Panic!!!
Thursday, March 5 | 11:45am – 12:45am | Sierra

Come join Tom Fitzpatrick, Strategic Verification Architect at Mentor, a Siemens Business, as he explores the myriad factors that contribute to verification complexity and how the changing landscape of electronics will expose new challenges in the continuing quest to find and eliminate bugs as early and effectively as possible.

FEATURED TUTORIAL
Application Optimized HW/SW Design & Verification of a Machine Learning SoC
Thursday, March 5 | 8:30am – 11:30am | Donner

This tutorial walks through the process of migrating an algorithm from generic software to a hardware implementation customized to the specific requirements of your system; making intelligent trade-offs between hardware and software along the way. It will explain the tools and techniques needed to go from “Software to Systems” and cover a broad range of solutions including simulation, emulation, prototyping, and High-Level Synthesis to design and verify SoCs and the software that runs on them.

FEATURED PANEL
Predicting the Verification Flow of the Future
Wednesday, March 4 | 1:30pm – 2:30pm | Oak/Fir

Moderator Jean-Marie Brunet from Mentor, a Siemens Business, will take a panel of verification experts on an exploration of what the verification environment of the future will look like. They will attempt to predict the longevity of simulation and formal verification and determine how far emulation will be able to extend through the entire verification flow. The role of standards will be addressed, as will when analog will have a place in digital functional verification.

SHORT WORKSHOPS
How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity
Monday, March 2 | 3:30pm – 5:00pm | Oak

Mind the GAP(s): Closing and Creating GAPS between Design and Verification
Thursday, March 5 | 1:00pm – 2:30pm | Siskiyou

PAPER SESSIONS
Designing PSS Environment Integration for Maximum Reuse
Tuesday, March 3 | 9:00am – 10:30am | Fir

UVM – Stop Hitting Your Brother Coding Guidelines
Tuesday, March 3 | 3:00pm – 5:00pm | Oak

Multi-Level Replay of VIP Models in Isolation from Original Design Verification Environment to Enhance Protocol Analysis and Debug
Tuesday, March 3 | 3:00pm – 5:00pm | Fir

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and Now UPF 3.1: The Big Q “Which is the Right Standard for My Design?”
Tuesday, March 3 | 3:00pm – 5:00pm | Monterey/Carmel

Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification
Tuesday, March 3 | 3:00pm – 5:00pm | Monterey/Carmel

Systematic Methodology to Solve Reset Challenges in Automotive SoCs
Wednesday, March 4 | 3:00pm – 4:30pm | Monterey/Carmel

Scalable Reset Domain Crossing Verification Using Hierarchical Data Model
Wednesday, March 4 | 3:00pm – 4:30pm | Monterey/Carmel

SystemVerilog Constraints: Appreciating What You Forgot in Class to Get Better Results
Wednesday, March 4 | 3:00pm – 4:30pm | Oak

POSTER SESSIONS
Tuesday, March 3 | 10:30am – 12:00am | Gateway Foyer

4.3 – Covergate: Coverage Exposed

4.8 – How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros

4.11 – Are You Safe Yet? Safety Mechanism Insertion and Validation

4.14 – Deadlock Verification for Dummies – The Easy Way Using SVA and Formal

EXHIBIT FLOOR
You’ll find Mentor experts in booth #404 presenting daily theater sessions and running the latest Enterprise Verification Platform demos across Emulation, Low Power, Formal, Portable Stimulus, High-Level Synthesis, Verification IP, Debug, and more!

Mentor has pioneered technology to close the design and verification gap to improve productivity and quality of results. Catapult High-Level Synthesis for C-level verification and PowerPro for power analysis; Questa for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus; Veloce for hardware emulation and system of systems verification, unified with the Visualizer debug environment.

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The Tech week that was February 10-14 2020

The Tech week that was February 10-14 2020
by Mark Dyson on 02-16-2020 at 10:00 am
Categories: China, Semiconductor Services, Silicon Photonics

Semiconductor Weekly Summary 1

The new coronavirus outbreak or COVID-19 outbreak, as it is now officially called, continues to dominate the news again this week as currently there is no end forecast to the outbreak, and infection numbers continue to rise. This will have an impact on semiconductor supplies in the coming months and into Q2 as the necessary restrictions to try to contain the disease cause Chinese companies struggle to be allowed to reopen after the extended Chinese new year holiday and to also get workers allowed back from other parts of China, especially for the smaller companies. This will have a knock on impact not just on semiconductor supplies from China in the coming months but also on supplies of materials and consumables to non Chinese semiconductor manufacturing companies. Let’s hope the COVID-19 outbreak comes under control soon and all my colleagues and acquaintances and families stay safe and healthy throughout this difficult period.

Chinese leading wafer foundry SMIC said on Friday that it will double its capital spending in 2020 and expects revenue to grow 10% despite the COVID-19 outbreak, but SMIC did also warn that the worst may yet be to come from the COVID-19 outbreak as implications ripple through the supply chain.

The impact of the COVID-19 outbreak is also being felt worldwide as the organizers of Mobile World Congress 2020 have cancelled this years event. Although the event is being held in Barcelona, most companies have travel restrictions in place and too many companies pulled out of the event.

US lighting companies are expecting delayed product supply due to the COVID-19, with US companies Cooper Lighting Solution and Satco both posting notices to their customers on possible interruption of supplies.

A survey by LEDinside magazine on the impact of COVID-19 on the Chinese LED industry showed that only 28% of companies think they will still make a profit despite the COVID-19 outbreak, whilst 38% think they will make a loss. If companies are allowed to resume production on Feb 17th 44% of companies expect the work resume rate to 50~70%, whilst 27% of companies expect the work resume rate to be below 50%.

In other news…

Whilst last year was a challenging year for most semiconductor companies, TSMC managed to buck the trend especially in the 2nd half. In recognition of last year’s record revenue, TSMC ‘s board has approved to pay TSMC’s 45,000 employees an average annual bonuses of US$33,000. The bonus will be paid in July. The total bonus amount to be paid out is 1.7% lower than 2018 as it reflects the 1.7% lower profit margin last year. TSMC’s board also approved a US6.7billion budget for advanced process and capacity expansion this year.

Taiwanese foundries and backend subcons published their monthly revenue figures last week. TSMC continued the trend from 2nd half last year.  TSMC posted monthly revenue of US$3.45billion (NT$103.7billion) up 0.4% on sequentially and up almost 33% yoy. This is the 6 straight month that TSMC has posted revenue of over NT$100billion.

Number 2 Taiwanese foundry UMC also had a good month recording revenue of US$4.67million for January up 19.5% yoy, and up 5% sequentially. UMC has also announced it will invest US$500million to expand capacity in its Chinese Xiamen 12inch Fab to boost capacity to 250k/month by mid 2021.

Specialist foundry Vanguard (VIS) was down though with the revenue dropping 8.9% sequentially to US$79million, and down 7.2% yoy. This was due to lower shipments over the Chinese New Year period.

Assembly and Test subcon ASE Technology holdings which includes both ASE and SPIL subcon groups reported monthly revenue for it’s ATM business of US$730million, which was down 5% sequentially but up 20.7% yoy.

Applied Materials, the market leader semiconductor equipment manufacturer gave an optimistic outlook for the semiconductor industry indicating companies are planning to spend more on capex in 2020. Applied Materials reported quarterly revenue for fiscal Q1, which ended Jan 26th, of US$4.16billion, up 11% yoy, the first increase in 5 quarters. They are forecasting US$4.34billion for fiscal Q2, which is up 22.6% yoy. They forecast minimal overall financial impact of COVID-19 virus for fiscal 2020, but do expect some changes in timings of revenues due to travel and logistics restrictions. Applied also said they were making good progress on regulatory approval for their acquisition of Kokusai Electric.

Austrian Sensor manufacturer AMS is pushing ahead with it’s plans to acquire Osram, and are pushing ahead to get what is known in Germany as a domination agreement to give AMS more control of Osram and to facilitate integrations efforts. AMS is asking Osram shareholders to approve the domination agreement which will require 75% approval at an EGM, the date of which is yet to be set.

ICInsights has published it’s latest report on worldwide Fab capacity, reporting that the top 5 semiconductor companies now supply 53% of global wafer capacity. The top 5 foundries are placed in the top 12, provide 24% of the worldwide capacity. Samsung with it’s large memory business holds the largest share with 15% of worldwide capacity, with TSMC 2nd with 12.8% and Micron 3rd with 9.4%. SK Hynix and Kioxia (formerly Toshiba Memory) making up the top 5 spots. It is interesting to note that 10years ago the top 5 companies only held 36% of the worldwide capacity showing how the industry is consolidating.

Qualcomm’s appeal against FTC’s antitrust victory against it was being heard in court last week in San Francisco. The judge stated that “Anticompetitive behaviour is prohibited under the Sherman Act. Hyper-competitive behaviour is not. This case asks us to draw the line between the two”

This week Samsung launched it’s next generation flagship phone which will be called Galaxy S20 and will have a 5G option and up to 4 cameras. They are hoping that 5G will revive demand for smartphones. Samsung also launch it’s next generation foldable phone the Galaxy Z Flip.

Photonics is one of the biggest growth areas in the IC market with a CAGR of over 20%. In 2013 the photonics IC market was 190million, this grew to 539million by 2017 and is expected to be between 1.3billion and 1.8billion by 2022, so the photonics market outlook is very bright.

Finally some sobering news and food for thought…

It is forecast that by 2030 there will be 20million manufacturing job layoffs due to robots powered by AI, big data and VR as Industry4.0 changes the way we live. In such an environment continued education and learning becomes essential. For the time being engineers are needed to create all these technologies, and the areas where most engineers will be needed will be AI & automation, Big Data, Generative Design and Digital Twins, Green Technology, VR/AR, robotics and 3D printing.