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Online Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)

Online Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)
by Daniel Nenni on 04-12-2020 at 9:00 am
Categories: Semiconductor Services, Threshold Systems

3D Finet Model

Our friends at Threshold Systems have a new ONLINE class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last February. This is normally a classroom affair but to accommodate the recent COVID-19 travel restrictions it is being offered virtually.

As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE.   Registration is HERE. And here is the updated course description:

Course Description:
The central theme of this seminar is an in-depth presentation of the key 10/7/5 nm node technical issues for Logic and Memory, including detailed process flows for these technologies.

This course addresses the issues associated with Advanced CMOS manufacturing with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 10nm and 7 nm FinFET technology and previews the upcoming manufacturing issues of the 5 nm Nanowire.

A key part of the course is a visual survey of leading-edge devices in Logic and Memory presented by the Fellow Emeritus of the world’s leading reverse engineering firm, TechInsights. His lecture is a visual feast of TEMs and SEMs of all of the latest and greatest devices being manufactured and is one of the highlights of the course.

An update on the status of EUV lithography will be also be presented by a world-class lithographer who manages an EUV tool. His explanations of how this technology works, and the latest EUV breakthroughs, are enlightening as they are insightful.

Finally, a detailed technology roadmap for the future of Logic, SOI, Flash Memory and DRAM process integration, as well as 3D packaging and 3D Monolithic fabrication will also be discussed.

Each section of the course will present the relevant technical issues in a clear and comprehensible fashion as well as discuss the proposed range of solutions and equipment requirements necessary to resolve each issue.

Course Notes:
The course notes are technically current, reproduced in high-resolution color and profusely illustrated with 700+ pages of high-quality 3D graphics and TEMs of real-world devices.

In addition, dynamic 3D models of semiconductor micro-structures are presented on-screen to clarify the structural details of FinFETs, 3D Flash and Nanowires. Click on the link below to preview a typical dynamic 3D image.

Date: May 27, 28, 29, 2020
Location: This course is held ONLINE
Class Schedule:
 Wednesday: 8:30 AM – 5:00 PM, PDT
Thursday: 9:00 AM – 5:00 PM, PDT
Friday: 9:00 AM – 5:00 PM, PDT
Tuition: $1,695

Online Instruction:
The Covid-19 pandemic and the travel restrictions it has imposed have changed the landscape of technical instruction from traditional instructor-lead classroom learning and toward a distributed learning experience that enables the instructor and the students to be in different locations. This learning solution eliminates high cost and inconvenience associated with having students travel to one location for instruction. It offers a flexibility and a convenience that traditional classroom instruction does not have. It is ideal for companies with a global business model and whose employees are scattered around the world.

The benefits of Online Learning are numerous:

  • a safe environment for both the students and the instructor
  • elimination of instructor travel costs
  • elimination of employee travel and lodging costs
  • minimal disruption of employee work schedules
  • reduced enrollment costs
  • the students do not all have to be in a single location. Remote Learning permits student attendance even if they are located in different countries.
  • unlike watching streamed video, remote instruction closely simulates the classroom experience and permits student questions and real-time student/instructor interaction
How Online Learning Works:

Shortly after you register a link will be emailed to you that will take you to the online classroom the day of the course, and the week before the class begins a binder of color course notes will be shipped to you via Fedex or UPS.

The class is three days long and will begin on May 27, 2020 at 8:30 PDT. On that day you simply click on the link that has been provided and you will be seamlessly taken to the online classroom. There you will see the opening slide of the course and a small inset image of the instructor. Once the class begins you will hear the instructors voice as he addresses the technical issues on each slide being presented. There will be a one-to-one correspondence between the slides being presented on the screen and the slides in your binder of course notes. Questions can be asked at any time by typing in the software’s question box and each question will be answered verbally by the instructor as soon as they are received.

In the unlikely event that you experience technical difficulties an IT expert will be on-hand to resolve any issues for you in real time.

Online learning is a simple, safe and convenient way to learn that offers a highly effective classroom experience without having to leave the safety and comfort of your own home or office.

What’s Included:

  • Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material
  • A high quality set of full-color lecture notes, including SEM & TEM micrographs of real-world IC structures that illustrate key technical points
  • A Diploma stating that you have successfully completed the seminar will be mailed to you at the end of the course

Who is the seminar intended for:

  • Equipment Suppliers & Metrology Engineers
  • Fabless Design Engineers and Managers
  • Foundry Interface Engineers and Managers
  • Device and Process Engineers
  • Design Engineers
  • Product Engineers
  • Process Development & Process Integration Engineers
  • Process Equipment Marketing Managers
  • Materials Supplier Marketing Managers  & Applications Engineers

Course Topics:

1. Process integration
The 10/7nm technology nodes represent a landmark in semiconductor manufacturing and they employs transistors that are faster and smaller than anything previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 10/7nm nodes and describes the technical issues that had to be resolved in order to make these nodes a reality.

  • The enduring myth of a technology node
  • Market forces: the shift to mobile
  • The Idsat equation
  • The motivations for High-k/Metal gates, strained Silicon
  • Sevice scaling metrics
  • Ion/Ioff curves, scaling methodology

2. Detailed 10nm Fabrication Sequence
The FinFET represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 10nm FinFET is the 3rd generation of non-planar transistor and involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 10nm FinFet structure and its fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 10nm fabrication sequence is presented (Front-end and Backend) that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty material requirements are pointed out at each phase of the manufacturing process, as well as the chemistries used.

  • Self-Aligned Quadruple Patterning (SAQP)
  • Fin-first and Fin-last integration strategies
  • Multiple Vt Hi-/Metal Gate integration strategies
  • Cobalt Contacts & Cobalt metallization
  • Contact over Active Gate methodology
  • Advanced Metallization strategies
  • Air-gap dielectrics

3. Nanowire Fabrication – the 5nm Node
Waiting in the wings is the Nanowire. The advent of this new and radically different 3D transistor features gate-all-around control of short channel effects and a high level of scalability. A detailed process flow of a Horizontal Nanowire fabrication process will be presented that is beautifully illustrated with colorful 3D graphics and which is technically accurate.

  • A step-by-step Horizontal Nanowire fabrication process flow
  • Key fabrication details and manufacturing problems
  • Nanowire SCE control and scaling
  • Resolving Nanowire capacitive coupling issues
  • Vertical versus Horizontal Nanowire architecture: advantages and disadvantages

4. DRAM Memory
DRAM memory haS evolved through many generations and multiple incarnations. Despite claims that DRAM memory is nearing its scaling limit, new technological developments keep pushing the scaling envelope to extremes. This part of the course examines the evolution of DRAM memory and presents a detailed DRAM process fabrication flow.

  • DRAM memory function and nomenclature
  • DRAM scaling limits
  • A DRAM process flow
  • The capacitor-less DRAM memory cell

 

5. 3D NAND Flash Memory
The advent of 3D NAND Flash memory is a game changer. 3D NAND Flash not only dramatically increases non-volatile memory capacity, it will also add at least three generations to the life of this memory technology. However, the structure and fabrication of this type of memory is radically different, even alien, to any traditional semiconductor fabrication methodology. This section of the course presents a step-by-step visual description of the unusual manufacturing methodology used to create 3D Flash memory, focusing on key problem areas and equipment opportunities. The fabrication methodology is presented as a series of short videos that clearly demonstrate the fabrication operations at each step of the process flow.

  • staircase fabrication methodology
  • the role of ALD in 3D Flash fabrication
  • controlling CDs in tall, vertical structures
  • detailed sequential video presentation of Samsung 3D NAND Flash
  • Intel-Micron 3D NAND Flash fabrication sequence
  • Toshiba BICS NAND Flash fabrication sequence

6. Advanced Lithography
Lithography is the “heartbeat” of semiconductor manufacturing and is also the single most expensive operation in any fabrication process. Without further advances in lithography continued scaling would difficult, if not impossible. Recently there have been significant breakthroughs in Extreme Ultra Violet (EUV) lithography that promise to radically alter and greatly simplify the way chips are manufactured. This section of the course begins with a concise and technically correct introduction to the subject and then provides in-depth insights into the latest developments in photolithography. Special attention is paid to EUV lithography, its capability, characteristics and the recent developments in this field.

  • Physical Limits of Lithography Tools
  • Immersion Lithography – principles and practice
  • Double, Triple and Quadruple patterning
  • EUV Lithography: status, problems and solutions
  • Resolution Enhancement Technologies
  • Photoresist: chemically amplified resist issues

7. Emerging Memory Technologies
here are at least three novel memory technologies waiting in the wings. Unlike traditional memory technologies that depend on electronic charge to store data, these memory technologies rely on resistance changes. Each type of memory has its own respective advantages and disadvantages and each one has the potential to play an important role in the evolution of electronic memory.

This section of the course will examine each type memory, discuss how it works, and what its relative advantages are in comparison with other new memory types.

  • Phase Change Memory (PCRAM), Cross-point memory; separating the hype from the reality
  • Resistive RAM (ReRAM) – a novel approach that comes in two variations
  • Spin Torque Transfer RAM (STT-RAM) – the brightest prospect?

8. Survey of leading edge devices
This part of the course presents a visual feast of TEMs and SEMs of real-world, leading edge devices for Logic, DRAM and Flash memory. The key architectural characteristics for a wide range of key devices will be presented and the engineering trade-offs and compromises that resulted in their specific architectures will be discussed. The Fellow Emeritus representative of the world’s leading chip reverse engineering firm will present the section of the course.

  • How to interpret Scanning and Transmission Electron microscopy images
  • A visual evolution of replacement gate metallization
  • DRAM structural analysis
  • 3D FLASH structural analysis
  • Currently available 14nm/10nm/7nm Logic offerings from various manufacturers

9. 3D Packaging Versus 3D Monolithic Fabrication
Unlike all other forms of advanced packaging that communicate by routing signals off the chip, 3D packaging permits multiple chips to be stacked on top of each other, and to communicate with each other using Thru-Silicon Vias (TSVs), as if they were all one unified microchip. An alternate is the 3D Monolithic approach, in which a second device layer is fabricated on a pre-existing device layer and electrically connected together employing standard nano-dimensional interconnects. Both approaches have advantages and disadvantages and promise to create a revolution in the functionality, performance and the design of electronic systems.

This part of the course identifies the underlying technological forces that have driven the development of Monolithic fabrication and 3D packaging, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of these revolutionary technologies.

  • TSV technology: design, processing and production
  • Interposers: the shortcut to 3D packaging
  • The 3D Monolithic fabrication process
  • Annealing 3D Monolithic structures
  • The Internet of Things (IoT)

10. The Way forward: a CMOS technology forecast
Ultimately, all good things must come to an end, and the end of FinFET technology appears to be within sight. No discussion of advanced CMOS technology is complete without a peek into the future, and this final section of the course looks ahead to the 5/3.5/2.5 nm CMOS nodes and forecasts the evolution of CMOS device technology for Logic, DRAM and Flash memory.

  • Is Moore’s law finally coming to an end?
  • New nanoscale effects and their impact on CMOS device architecture and materials
  • The transition to 3D devices
  • Future devices: Quantum well devices, Nanowires, Tunnel FETs, Quantum Wires
  • The next ten years …

REGISTER NOW!

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SiFive in a Virtual World Webinar Series 2020

SiFive in a Virtual World Webinar Series 2020
by Swamy Irrinki on 04-10-2020 at 6:00 pm
Categories: Events, IP, RISC-V, SiFive

Rapid Embedded Prototyping with SiFive Software

Introducing the SiFive Connect Webinar Series –A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions

After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached all corners of the globe and is here to stay. RISC-V cores are being designed into many SoCs and domain-specific custom silicon. To take our previous engagement with the global community to the next level, we’re launching the SiFive Connect Webinar Series as a highly educational and interactive platform for SoC developers to connect directly, on an ongoing basis, with industry experts. Targeted for engineers, architects, developers, researchers and students, attendees will learn about the RISC-V ecosystem and the latest RISC-V based cores and software, security solutions, SoC and system IP, various end market solutions and development platforms.

These bimonthly webinars will be one hour in duration, and each will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT – enabling the global community to choose the time that works best for them.

Registration is now open for the first two SiFive Connect webinars of 2020!

  • Thursday, April 16, 2020

Embedding Intelligence Everywhere with SiFive 7 Series Core IP

View Abstract & Register to Attend

  • Thursday, April 30, 2020

Rapid Embedded Prototyping with SiFive Software

View Abstract & Register to Attend

To view an extended list of upcoming topics, please visit https://www.sifive.com/resources/webinars/sifive-connect.

We look forward to engaging with you and sharing knowledge!

About SiFive

SiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit www.sifive.com.

Stay current with the latest SiFive updates via Facebook, Instagram, LinkedIn, Twitter, and YouTube.

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Wally Rhines: Mentoring Generations of Semiconductor and EDA Professionals

Wally Rhines: Mentoring Generations of Semiconductor and EDA Professionals
by Mike Gianfagna on 04-10-2020 at 10:00 am
Categories: Events, Wally Rhines
6 Comments

Wally Then and Now

I had the good fortune to catch a live webinar recently that was quite compelling – Conversation with Dr. Walden Rhines: Predicting Semiconductor Business Trends After Moore’s Law! Dr. Rhines, known to most as Wally, doesn’t need much of an introduction. Any semiconductor or EDA professional knows who he is and what he’s accomplished. His discussion about predicting the future didn’t disappoint. Wally is the rare individual who is articulate, knowledgeable and able to explain complicated phenomena in a way that is accessible to all. If you missed the live event, you will want to catch the replay here

You may wonder about the significance of the photo above.  Read on…

Wally’s discussion was based on his new book, “Predicting Semiconductor Business Trends After Moore’s Law!” The book is available on Amazon here.  To get you more interested in the webinar, there may be some free stuff, like a PDF version of the book in store for you if you watch it.

I don’t want to repeat the insights offered in the webinar here, it’s much more entertaining to hear them from Wally. I will offer a few topics just to whet your appetite. Do you know what the semiconductor learning curve is and how it informs the predictions of Moore’s Law? What about the Gompertz curve? This one has been around since 1825 and can be used to predict everything from the growth of tumors, population and product adoption. Want to understand how all this relates to semiconductor and Moore’s Law? Watch the webinar.

Do you ever wonder when silicon transistors will finally need to be replaced? Wally explains that with solid analytics. What about IC silicon revenue per unit area over time? What does that curve look like?  Again, watch the webinar. I could go on, but I’ll stop here.  By now, you should be looking to click one of the webinar links above. The entire event is under 40 minutes, including a very robust Q&A session. The questions posed to Wally are included below to further whet your appetite.

And regarding the photo above – this was the final slide for the final question below – How does Wally manage to look so young after 50 years in this dog-eat-dog business?  Wally’s answer to this one might be the best nugget of all.

  • Can you predict the revenue impact of Covid 19 on both the semiconductor and EDA industries?
  • Does your book suggest that Moore’s Law is not coming to an end?
  • What will drive Scale for semiconductor going forward if Moore’s law will not be true forever. Will it be innovative packaging, materials or some other factor?
  • If your consolidation vs specialization trend plays out, what will the company structure of the EDA industry look like in ten years?
  • How can you explain some of those remarkable ratios, like the constancy of revenue per unit area of silicon?
  • Will China be successful in its quest for self-sufficiency in semiconductors? How will semiconductor companies in the West be affected?
  • What are some future challenges for this next generation of neuromorphic computers?
  • Why has the EDA industry accelerated its growth in recent years?
  • Compute servers in the cloud were once dominated by Intel. Now NVIDIA, Google Tensor Flow and other hardware is showing up in the cloud.  What will things look like in the future?
  • How will the semiconductor industry cope with the need for better data security?
  • How should the semiconductor companies prepare their teams for transitioning from a “component / bottom up” focus to a “top down” approach? How can the many IC design expert’s transition to a “system-level” thinking and learn about many, likely very diverse applications?
  • The semiconductor industry has relied on parallel cost and learning curve (seen in chapter 2 of the blog) and past deviations from this have been quickly corrected like in the case of Test Equipment. With the introduction of EUV, the lithography curve is meant to go almost flat as ASML increase the price of its tools almost in line with their productivity. What do you think is the impact of this very significant cost inflation on the industry? Is it possible to bring the lithography curve back to trend despite a technological monopoly? If not, who bears the extra cost / sub-trend deflation?
  • In your opinion, what is going to be the role of Europe in the future semiconductor business? Any segment that can be led by European companies such as Infineon, Soitec or ST?
  • How does he see the role of all the backend next 10 years vs. past 10 years? Thinking about packaging and PCBs/Substrates as well?
  • What does he think is the impact of a move to chiplets architectures on the EDA industry?
  • What could change the shape / inflection points of his prediction for the transistor curve (chapter 4, fig 7, the S curve of Silicon)? Or what does he see that could materially change the Si/GDP penetration curve?
  • Ask Wally how he manages to look so young after 50 years in this dog-eat-dog business.
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Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs

Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs
by Herb Reiter on 04-10-2020 at 6:00 am
Categories: Cadence, EDA, Events

2d 3d Semiconductor Packaging SemiWiki Cadence

I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki webinar on Thursday, April 23, at 10 am PDT. You’ll get in-depth information about how Cadence makes planning, design and verification of next-generation heterogeneously integrated 2.5/3D-ICs and wafer-level packages cost-effective, easier and faster.

Our customers value the semiconductor industry for its fast pace of innovation as well as for providing better and cheaper solutions for an ever-broader range of – often heterogeneous – applications. A well-coordinated design and manufacturing supply chain, with domain experts at every stage, is the basis for all these accomplishments. Dozens of recent announcements of heterogeneously integrated 2.5/3D-IC designs, primarily from larger companies, have demonstrate how well heterogeneous integration can improve performance per Watt and increase functionality in a single IC package. However, until now, the high development cost, resource requirements and long development times have stopped many engineers from using these powerful solutions for bringing their ideas to market.

That’s a very familiar scenario to me. During my ASIC years, (1980 to 2000) I saw our design center engineers working 80+ hour weeks to meet tape-out schedules for, in today’s view, really small designs. How did our industry get from then 10 Million gate designs to today’s up to 10 Billion gate solutions – a 1000 x improvement?

The short answer is: AUTOMATION!  In more depth: This level of improvement was only possible, because TSMC and other wafer manufacturers developed, together with their Electronic Design Automation (EDA) partners, process design kits (PDKs). They specified exactly what the process technologies were capable of and what was not allowed. This PDK data (e.g. libraries, SPICE decks, design rules, layer information, etc.) enabled their mutual customers to accurately simulate what’s technically feasible and quickly iterate to improve performance and/or reduce unit cost of a design. Over time, design tools and methodologies became more user-friendly, managed larger design complexities and drove reducing cost per function. In addition to more powerful EDA tools, the initially very simple library elements became more and more complex building blocks and, available as verified soft IP (RTL code) or silicon-proven hard IP (GDSII), they simplified and accelerated ASIC design even further.

Back to the webinar. John Park will outline why and how Cadence, in cooperation with the big assembly and test houses (a.k.a. OSATs) and IC packaging experts at wafer foundries, developed a design environment for heterogeneously integrated 2.5/3D-ICs and wafer-level packages. Cadence is also simplifying the use of chiplets (silicon proven hard IP, implemented in bare die) as design-productivity enhancing building blocks.

In my view, the biggest advantage of the Cadence multi-die IC solution is that it links their proven and well-known design tools for IC, package and board (InnovusR, VirtuosoR, AllegroR), uses OrbitIOR and other proven tools, as well as recently introduced tools (e.g. ClarityR) to plan, design and verify your 2.5/3D-ICs. This Cadence solution will enable you to quickly become productive as developer of heterogeneously integrated 2.5/3D-ICs and wafer-level packages.

Please use this opportunity, register here and view this SemiWiki webinar replay.  A link to the replay will be sent to all registered people in case you miss it or want to review it again. It’s time well spent… Herb

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Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020

Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020
by Robert Castellano on 04-09-2020 at 10:00 am
Categories: Information Network, Semiconductor Services
2 Comments

Applied Materials Lam lower C2

Because of significant $4 billion in equipment pull-ins in Q4 from sales in Asia, I was reducing my semiconductor wafer front-end (WFE) equipment revenue growth from an earlier +5% to 0% in 2020. Now, based on CORVID-19, I am further reducing revenue growth to -6.9%.

Chart 1 also shows the cyclical nature of semiconductors and semiconductor equipment. In principle, semiconductor manufacturers increase production to meet customer demand. If demand increases, manufacturers will make capacity purchases of processing equipment to make more chips. This is why there is strong correlation between semiconductor revenue changes (blue line) and semiconductor equipment (red line).


Chart 1

GDP (black line), which measures the value of economic activity within a country, is often a factor in halting the increases in semi and semicap revenues. GDP is important because it gives information about how an economy is performing. The growth rate of GDP is often used as an indicator of the general health of the economy.

Thus, if a country has healthy economy (upward slope of black line), we often see an upward slope in semi and semicap revenues. The converse is also true. If the economy is doing well, individuals have money to make purchases of products using chips – smartphones, cars, TVs, etc.

Besides the significant drop in GDP, there are other factors corroborating my forecast.

Drop in Capex Spending
Table 1 shows announced and estimated capex spending for the top five semiconductor manufacturers. There are three caveats readers must recognize. First, capex includes building as well as equipment. Second, capex is a variable expenditure, and the numbers planned at the beginning of the year are never the amount of actual spend. Third, Samsung’s (OTC:SSNLF) capex spend are for its memory and foundry. These five companies represent about 60-65% of total spend, so it is a good representation.

According to Table 1, expected capex spend for these top five companies will decrease 12.1% in 2020, according to The Information Network’s report entitled “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts.”

Drop in Semiconductors and Semiconductor Equipment
Table 2 compares GDP, semiconductor and semiconductor equipment revenues for 2008-2009 and 2019-2020. A striking observation in the comparison of the two crises is the similarity of YoY changes in the year up to and including the year that GDP dropped in 2009 and forecast to drop in 2020. That’s despite the difference in origins of the recession.

The Global Financial Crisis began in 2007 with a depreciation in the subprime mortgage market in the United States, and it developed into an international banking crisis with the collapse of the investment bank Lehman Brothers on September 15, 2008. The crisis was nonetheless followed by a global economic downturn. This coming recession in 2020 has to do with CORVID-16.

At this time, I forecast semiconductor equipment revenues will drop 6.9% in 2020. I also forecast that semiconductor revenues will decrease 6.1% in 2020 to $434.0 billion.

Drop in Consumer Confidence
When consumer confidence is high, consumers make more purchases. When confidence is low, consumers tend to save more and spend less. Consumer confidence typically increases when the economy expands, and decreases when the economy contracts.

The University of Michigan’s consumer sentiment for the US was revised down to 89.1 in March of 2020 from a preliminary of 95.9 and 101 in February (Chart 2). It is the lowest reading since October of 2016 and the fourth largest one-month decline in nearly a half century.


Chart 2

ECRI’s Weekly Leading Index (WLI), is in free fall. According to ECRI, the nine-week drop in the WLI is more pronounced than anything it’s ever seen at this stage of a recession. Chart 3 shows WLI growth going back half a century. It looks like WLI growth has just fallen off a cliff, not having been this low since the immediate aftermath of the Lehman Brothers collapse in 2008.


Chart 3

The impact of this drop in revenues will primarily impact processing equipment companies AMAT and LRCX. ASML is another processing company that currently does not see the impact of COVID-19 beyond Q, but the company announced in a press release on March 30 it could affect Q2. The company noted:

“Due to the uncertainties regarding COVID-19, ASML has decided not to execute any share buybacks in Q2 2020. This decision follows the pause in the execution of the program in the first quarter, after having already performed share buybacks under the new program for an amount of approximately €507 million.”

KLA’s metrology/inspection equipment is very different from processing equipment such as lithography, etch, or deposition sold by peers.

KLA’s metrology/inspection equipment sales fare better during technology purchases versus capacity purchases of equipment to make more of the same chip. With the slowdown in global economies in 2020, there will be minimal capacity purchases but major technology purchases for the next processing node. KLA will benefit, as well as ASML for its EUV systems, but they represented only 31% of total revenues in 2019.

Once the pandemic is halted, large companies in the semiconductor and high-tech businesses should resume business as usual. Other large companies will be slower to recover, like airlines and hotels, as mentioned above. Small companies and mom and pop stores may never recover. Along with the elimination of their businesses goes their purchasing power – money that could be spent on smartphones, cars, and TVs.

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Learning to Live with the Gaps Between Design and Verification

Learning to Live with the Gaps Between Design and Verification
by Tom Simon on 04-09-2020 at 6:00 am
Categories: Siemens EDA

Learning to live with the gaps between design and verification

Whenever I am asked to explain how chip design works by someone who is unfamiliar with the process, I struggle to explain the different steps in the flow. It also makes me aware of the discrete separations between each phase of activities. Of course, when you speak to a novice it is not even possible to get more than one layer down in the explanation. For folks in in the industry we are painfully aware of the separate steps and partitions in the process. Not only does the design flow from high level front end representations through transformations to silicon transistors and geometry, there are also parallel processes that involve internal and external IP. Woven throughout this is the design verification process, which must work within each step of the process and also across the entire flow.

As designers, the first urge is to smooth over all the gaps and try to make them disappear. However, in a paper given by Mentor at DVCON in Silicon Valley this year they suggest acknowledging the gaps in the design flow and in some cases embracing them to improve the speed and effectiveness of the verification process. I had a chance to talk to Chris Giles, one of the coauthors of the paper along with Kurt Takara, on their view of the issue of gaps and his approach to dealing with them. Fortunately, in light of present-day circumstances, Mentor is offering a replay of the paper online for anyone interested in seeing its entire contents.

In their presentation they cover the main sources of gaps, such as documentation issues, models that are not accurate or incomplete, changes to any aspect of the project, organizational boundaries or team member skill sets. They point back to the time when RTL was first coming into use where designers would code the design and test benches in RTL sequentially. Without a gap between design and verification they would run these to verify the design. Of course, things are much different today with design teams and verification teams working as separate entities and using different tools for their jobs.

There is a stark choice to make. Do you throw the design over the wall and assume that the information needed to fully and properly verify the design intent and functionality made it through the gap? Or do you hope you have sufficient numbers of engineers that have expertise in design and verification to pull the project through? Chris spoke of taking this gap and embracing it by moving the intent verification into the design group and handing the functional verification to the verification team. Mentor tools play a role in this by ensuring that the tools each team would use are suited to the task and expertise of the users.

The presentation in the video goes into detail discussing which techniques are useful for various verification tasks by each prospective user. These include tools to help with code writing, static and formal lint tools, and CDC and RDC checkers. During the video Chris highlights each of these activities and how they might work when design gaps are used constructively.

Because all designs are hierarchical, verification flows need to not only work with hierarchy, but work to resolve issues that can arise due to the use of hierarchy. Mentor has worked out flows for hierarchical verification that work not only with black box views, but also use white box models to manage convergence issues efficiently and accurately. The presentation talks about their Hierarchical Data Model (HDM) for intent verification. The video also covers situations where designers need to handle intent verification, yet subsequent design transformations and optimization alter the design such that the intent is lost. This is a case where there is an unavoidable gap that must be acknowledged and dealt with. Chris and Kurt provide examples of how this can be done by applying specific techniques.

Verification is a huge topic with many facets. It is incumbent on engineering teams to understand potential sources of errors and methods of addressing them. Because gaps in the flow are unavoidable, being savvy about minimizing or taking advantage of them is a necessity. The video shows a range of specific cases and how they can be handled. Mentor is making the DVCON presentation available for viewing through the web. It goes into much more detail than is possible here and I strongly suggest checking it out.

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A cautionary tale for the digital economy

A cautionary tale for the digital economy
by Terry Daly on 04-08-2020 at 10:00 am
Categories: Foundries
9 Comments

TSMC Wafer

COVID-19 underscores the importance of US-based production for strategic industries

The COVID-19 pandemic has drawn intense focus on the need to repatriate pharmaceutical manufacturing back to the United States.  The increased awareness that a strategic adversary manufactures or controls up to 80% of the active pharmaceutical ingredients used to produce drugs has shocked the nation’s sensibility. What other strategic industries are at risk of offshore dependency? Foremost on the list is electronics, most especially the semiconductor industry.

No industry has a more pervasive and strategic impact on the economy than semiconductors. “Chips” are the essential infrastructure of the digital economy, embedded in every connected hardware platform.  They drive consumer electronics, telecommunications, media, the internet, the cloud, transport, medical discovery and medical devices, education, finance, energy, agriculture, government and more. US national security runs on chips, including defense, intelligence, cyber and space. To safeguard the digital economy during conflict or national crisis, the US Government must take a more proactive posture to guard against offshore dependency and supply disruption.

The semiconductor industry is a complex global network of companies including product design, design tools and intellectual property (IP), chip manufacturing, outsourced packaging and test (OSAT) and semiconductor equipment and materials. “Fabless” firms solely design chips. “Foundries” focus exclusively on manufacturing. The “Integrated Device Manufacturers” (IDMs) both design and manufacture chips. The US has capable manufacturers in Intel, TI, On Semiconductor and Micron, but as IDMs they only manufacture products they design.  With the benefit of their decades-long investments in the United States, for the products that they make, the US is well prepared.

However, for many other high-volume chips used across essential digital platforms, the US is critically dependent on offshore factories.  This is evident in the supply of leading-edge technologies and the equipment and materials central to the manufacturing process. Fabless product companies such as Qualcomm, AMD and Xilinx have virtually all leading-edge products (7 nanometer and below) manufactured offshore, mostly at TSMC in Taiwan. The commercial Foundries in the US, GLOBALFOUNDRIES and TowerJazz, do not offer leading edge technology. AMKOR, the only US-based commercial-scale OSAT, has all its manufacturing located offshore. Dutch equipment company ASML holds a virtual monopoly on lithography equipment, arguably the most critical step in chip production.  Key rare earth raw materials such as cobalt, gallium, tungsten and germanium are critical to chip production. China is estimated to hold at least 80% of world production of these and other rare earth materials.

A prolonged denial of access to suppliers in Taiwan, South Korea, Japan and elsewhere in Southeast Asia during time of crisis would severely risk supply of chips for US communications networks, data centers, medical devices, financial systems and the electric grid.  While the US has effective mitigation to assure the supply of critical parts for national security through the Department of Defense’s Trusted Foundry, its scope and scale are insufficient to address our nation’s other critical infrastructure needs. United States policy should target self-sufficiency for both national security and critical infrastructure needs.

Domestic “burst” capacity in chip manufacturing is a much tougher task than production of ventilators, masks and personal protective equipment – as important as these are to our current national emergency.  The issue is time.  To build, equip, qualify and ramp a new chip factory requires minimally up to two years, time well beyond that needed to meet an emergency.  Existing factories at Intel, GLOBALFOUNDRIES, TI, On Semiconductor and Micron could be re-purposed on a quicker timetable, but these companies would need access to the IP and know-how of offshore competitors such as TSMC, and potentially additional equipment, to build non-IDM and leading edge products. Alternately, Fabless firms could re-spin their product designs to be built on US-based IDM process technologies, a non-trivial effort requiring several months to achieve volume.  Invoking the Defense Production Act can trigger action but not solve the issue of time.

Decisive US policy is needed to re-balance the equation between government-led readiness and the continuation of an un-bridled free market approach to semiconductor manufacturing.

First, the Administration needs to adopt policy proposals that enhance, not diminish, the competitiveness of our leading semiconductor companies. For example, the pending decision to invoke the “foreign direct product rule” to inhibit supply of chips to Huawei will inflict severe financial damage to US equipment suppliers and hand hard-earned market share to Japan and South Korea.  Next, US should fund aggressive financial incentives for both US and global manufacturers (with focus on TSMC and Samsung) to build or expand leading-edge factories in the US.  This plan should include subsidies for capital and operating expenditures sufficient to eliminate current cost disadvantages versus Southeast Asia as well as competitive tax incentives. Creative public-private models can achieve the best of the innovative and efficient private sector while assuring adequate, responsive US-based supply.  Third, US should fund a Strategic Semiconductor Reserve comprised of US Government priority access to domestic “burst” manufacturing capacity, physical stockpiles of rare earth materials, and in concert with industry, a government-funded virtual finished goods inventory of chips and other components found in essential infrastructure platforms.  Finally, the US should expand advanced research funding to assure US leadership in Artificial Intelligence, 5G, quantum computing and other emerging technologies.

Whether in a Phase 4 “infrastructure” bill or a normal appropriation cycle, The President and Congress must think expansively in redressing the strategic risk inherent in the current US posture.  One prefers that a free trade regime govern independent investment decisions by US and global corporations.  But as COVID-19 has brought to light, establishing national readiness for exceptional circumstances requires implementation of pro-active public policy ahead of crisis.

Terry Daly is a retired semiconductor industry executive

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Best Practices for IP Reuse

Best Practices for IP Reuse
by Bernard Murphy on 04-08-2020 at 6:00 am
Categories: Cliosoft, EDA

Reuse

As someone who was heavily involved with rules for IP reuse for many years, I have a major sense of déja vu in writing again on the topic. But we (in SpyGlass) were primarily invested in atomic-level checks in RTL and gate-level designs. There’s a higher level of best practices in process we didn’t attempt to cover. ClioSoft just released a white paper (authored by Jeff Markham) on that topic and forwarded to me by my old Atrenta buddy Simon Rance (now VP Marketing at Cliosoft).

Jeff covers a lot of territory, on creation of IP and evaluation of commercial IP, with his own views on what the industry could do to make these easier. I’m more drawn to the question of what it takes to make an IP reusable because that was a hot topic when we started. There was a book called the IP Reuse Methodology Manual, then considered the bible for what you should and should not do. There’s was also a lot of debate about how practical it was to invest in making internally developed IP reusable.

I heard fairly generally that the effort to make an IP reusable is significant – maybe 3X the original cost of developing the IP. This would be to get it to a point that you could search a library by function, process, parametrics, documentation, that sort of thing, to find and compare this IP with other comparable solutions. Then you could download maybe a behavioral and abstract model to check it out in simulation and a floorplan. Then finally download the full thing with all requisite views and other collateral you would need to use it immediately in your design.

Nice idea and some semi design organizations actually organized to support that development. Perhaps some still do but for many it was a luxury they couldn’t afford. Reuse makes a lot of sense when you have a production line and are pumping out a lot of similar designs, which is what we were all expecting in that era of platform-based design.

Unfortunately for many who believed, markets did a 180 on their original dreams of platform-based design and massive reuse. I’m too disconnected from the details these days to make bold pronouncements, but I wouldn’t be surprised to hear that those dreams went up in smoke. That for most design teams today, reusable IP either comes from IP vendors or reuse has devolved to mean “here’s something fairly close that we used in the last design, adapt it as you see fit for the current design”.

In fact much of the reuse I have seen has evolved further to “we built this chip in the last generation, now it’s going to be a subsystem in this new generation”. Which makes a lot of sense when you think about it. That chip was proven in production, which is a pretty decent (though not perfect) stamp of certification. Good enough anyway when you make payroll by shipping product and you don’t have time to rebuild the subsystem.

Which is not to say that we don’t need to follow reuse best practices, with maybe some selectivity. Good engineering is built on good practices and becomes even more essential as we work on larger designs. Even if you’re going to use “copy and adapt” reuse, you still need to find a best candidate to start from, understand the functionality, parametrics, etc., etc. Maybe there’s something closer to what you need that would be a better starting point. Maybe there’s something in there that will fit the bill exactly – stranger things have happened.

Jeff has a good long list of suggestions. You could save yourselves a lot of time by following them. You can read more about Cliosoft HERE.

Also Read

WEBINAR REPLAY: AWS (Amazon) and ClioSoft Describe Best Cloud Practices

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

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Lithography Resolution Limits: Paired Features

Lithography Resolution Limits: Paired Features
by Fred Chen on 04-07-2020 at 10:00 am
Categories: Lithography

Lithography Resolution Limits Paired Features

As any semiconductor process advances to the next generation or “node”, a sticky point is how to achieve the required higher resolution. As noted in another article [1], multipatterning (the required use of repeated patterning steps for a particular feature) has been practiced already for many years, and many have looked to EUV lithography as a potential escape from more multipatterning. In reality, the requirement for multipatterning is dependent on the feature to which it is applied. This article is first in a series exploring key cases, to see when multipatterning may be avoided, and if it can’t be avoided, what is most likely the most practical way to do it. The first case to be considered will be the simplest: two features separated by a very small distance. These may represent two neighboring vias located at the ends of two separate long metal lines, for example (Figure 1).

Figure 1. Two neighboring vias at the ends of two long metal lines represent the basic case of two small features separated by a small distance.

The Rayleigh criterion

The Rayleigh criterion is a schoolbook formula giving the resolving power of an imaging system, with a given numerical aperture. The radius of the smallest spot that can be focused is given by r = 0.61 wavelength/numerical aperture. The numerical aperture here is basically the radius of the lens divided by the focusing distance (or focal length) [2]. If a second spot is located at the edge of the first spot, i.e., at this radial distance r, then it cannot be resolved. But once it is moved to a further distance, it can begin to be resolved. Hence, this distance defines a resolution limit for the minimum distance between two spot images (Figure 2).

Figure 2. The Rayleigh criterion defines the resolution between two features.

For an immersion lithography system, the wavelength is 193 nm, and the numerical aperture is 1.35, giving a minimum interspot distance of 87 nm. This distance might be reduced a little by the use of attenuated phase shifting masks; the improvement depends on the transmssion of the phase-shift mask [3]. For an EUV system, the wavelength is less narrowly defined (it is a pretty wide band), but nominally it is taken to be 13.5 nm, with a numerical aperture of 0.33, giving a minimum interspot distance of 25 nm. Unfortunately, to date, EUV lacks phase-shifting technology. A fundamental barrier is EUV’s relative lack of monochromaticity (it extends beyond the nominal 13.3-13.7 nm bandwidth), compared to the DUV excimer laser.

Getting below the Rayleigh criterion: Double patterning

To print two features close than the Rayleigh criterion will therefore require some form of double patterning. The simplest case would be to print one of the features using one mask, then the other with a second mask (Figure 3). This approach is often referred to as LELE, an abbreviation for “Litho-Etch-Litho-Etch”. A key drawback of this approach is the obviously critical dependence on the overlay between the two exposures.

Figure 3. The LELE (litho-etch-litho-etch) approach for double patterning, applied to the two vias of Figure 1.

In an alternative form of LELE, the second exposure “cuts” the first exposed feature (Figure 4). In other words, the second exposure has opposite tone to the first. This has somewhat better alignment of the two features, at least vertically in this case.

Figure 4. In this LELE variant, the second exposure cuts the first exposed feature, being opposite in tone.

Getting below the Rayleigh criterion: Print many and trim

Alternatively, it is possible to print an array of the features at a tight pitch, and remove (“trim”) the ones which are not required with a second mask exposure (Figure 5), or even leave them as “dummy” features. Printing arrayed features allows the space beween features to be reduced to less than 0.6 wavelength/numerical aperture (see Appendix). The second mask exposure overlay requirement would actually be a little relaxed compared to the above LELE case, but it still has to be tighter than the distance between features.

Figure 5. The array plus trim approach, applied to the vias of Figure 1. The shaded area represents a blocking mask to prevent the previously printed array features from being further etched.

No EUV advantage for sub-25 nm isolated pairs?

A careful consideration of the above techniques may make it clear that patterning isolated (or else sufficiently widely separated) pairs of features spaced by less than 25 nm can be done by two immersion exposures (LELE style), one EUV exposure plus one immersion exposure (array plus trim), or two EUV exposures (LELE or array plus trim). The immersion-only LELE approach is more sensitive to overlay than an array plus trim approach using EUV, but with current capabilities of ~2 nm already established with immersion tools [4], for distances of ~15-20 nm, there is no real advantage in going to EUV for this case.

Appendix: Rayleigh criterion (k1=0.61) vs. k1<0.61

Some of you may have the reasonable question, how does the Rayleigh criterion above not conflict with the low k1 (distance = k1 * wavelength/numerical aperture, k1<0.61) cases commonly encountered in immersion lithography? This will be covered more explicitly in the next article, but for now the question can be answered with reference to Figure 6. Basically, the Rayleigh criterion addresses the smallest image of a point, i.e., the point spread function. For an assembly of features, the point spread function is mathematically convolved with the locations of the features. When the features are spread widely, the width of the point spread function obviously dominates the image. However, when the features are densely packed together, at distances comparable to the Rayleigh criterion or even less, the width of the point spread function no longer impacts the image, but instead the spatial frequency corresponding to the pitch of the features determines the image. The point spread function only contributes to the blur (contrast degradation) of the image.

Figure 6. When the point spread function is convolved with a wide pitch (top) it dominates the image. When it is convolved with a dense pitch of comparable dimensions (bottom), the pitch dominates the image.

More quantitatively, we can examine the image produced by the (coherent) illumination of two points in the object plane. This is shown in Figure 7.

Figure 7. Two points separated by a given distance in the object plane appear wider in the image plane, when the object separation is at the Rayleigh criterion or less.

When the two objects are separated by the Rayleigh criterion or less, the image shows a wider than actual separation. Furthermore, the peak intensities are reduced and the central region shows higher intensity throughout. It is due to the growing influence of the neighboring point’s diffracted field in the image plane.

References

[1] https://www.linkedin.com/pulse/how-semiconductor-industry-got-itself-multipatterning-frederick-chen/

[2] B. E. A. Saleh and M. C. Teich, Fundamentals of Photonics (John Wiley & Sons, 1991), p.131.

[3] R. Socha et al., “Resolution Enhancement with High Transmission Attenuating Phase Shift Masks,” Proc. SPIE 3748, 290 (1999).

[4] https://www.evaluationengineering.com/home/article/13012512/asml-ships-new-immersion-lithography-platform

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Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP

Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP
by Mike Gianfagna on 04-07-2020 at 6:00 am
Categories: Events, IP, Synopsys

ARC HS5x HS6x block diagram

Synopsys issued a press release this morning that has some important news – Synopsys Introduces New 64-bit ARC Processor IP Delivering Up to 3x Performance Increase for High-End Embedded Applications. At first glance, one could assume this is just an announcement for some new additions to the popular ARC processor family. While that is true, there’s a lot more to the story. The newly announced processor IP has the potential to change the way embedded systems are designed.

I had the opportunity to chat with Mike Thompson, senior product marketing manager, ARC Processors at Synopsys. Before I get into more details, a bit about Mike. He drives the definition and marketing of the high-end ARC microprocessor products at Synopsys. Mike knows something about this market, having been involved in design and support of microprocessors, microcontrollers, IP cores, and the development of embedded applications and tools for over 30 years at places like MIPS, ZiLOG, Philips, AMD, and Actel. He holds a commanding view of the market and its needs.

One more important item before we dig into the details. Today, April 7, Mike is presenting the newly announcement processor IP at the Linley Spring Processor Conference, which is now a virtual event. His presentation is from 11:40 AM – 12:00 PM, Pacific time. I highly recommend you join that event if you’re registered for the conference.

“The growing complexity of high-end embedded systems such as in networking, storage, and wireless equipment demands greater processor functionality and performance without sacrificing power efficiency,” said Mike Demler, senior analyst at The Linley Group. “Synopsys’ new ARC HS5x and HS6x CPUs meet those needs, but they also provide the configurability and scalability needed to support future embedded-system requirements as well.”

OK, so why do I think is this announcement is a big deal? First, the basics. The following sentence from the press release says it well:

“The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 Instruction Set Architecture (ISA) and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions, making them the highest performance ARC processors to date.”

Setting a new performance bar is important, but that’s just the beginning of the story. These new processor cores extend capabilities in many directions, creating a new “canvas” if you will for embedded applications. Some capabilities make the job easier; some create fundamentally new opportunities. Regarding making the job easier, the 64-bit processor supports up to a 52-bit physical address space, which can directly address up to 4.5 petabytes. That’s a lot of room for innovation and significantly larger than anything else available.

There is support for up to 12 coherent CPU cores per processor cluster with L1 cache coherency. Mike explained that most applications today support four CPU cores, with a few offering up to eight. 12 cores, without degraded throughput, opens up the opportunity for new applications. The processors can be configured for real-time operation or with an advanced memory management unit (MMU) that supports symmetric multiprocessing (SMP) Linux and other high-end operating systems.

Another noteworthy capability is support for up to 16 user-implemented hardware accelerators with memory coherency. Hardware accelerators represent the “secret sauce” for many applications. Mike explained that few processors support hardware accelerators directly and those that do only support one. 16 changes the game. Mike listed some more features that make these processor cores extremely flexible and provide a lot of power optimization opportunities:

  • Support for asynchronous clocking for all CPU cores and hardware accelerators that allows the cores to be clocked at different speeds than the interconnect and other cores in the processor cluster
  • Support for individual power domains for all CPU cores, all hardware accelerators and the interconnect itself
  • Support for the industry standard ACE interfaces to easily connect to a network-on-chip (NoC) that might be implemented in the SoC
  • Coherency between the CPU cores with snooping, and coherency between the hardware accelerators with support for snooping
  • Cluster shared memory, under software control that can be used to move data between the CPU cores, the hardware accelerators and the NoC
  • High-bandwidth, low latency access to up to 16 MB of closely coupled memory (CCM) that is shareable between the CPU cores and hardware accelerators, providing single cycle access to local memory

At this point in our discussion, I felt that the application of these new cores was only limited by the imagination of the designer. This technology is quite complex – a direct quote from Mike drives the point home:

“We verify this IP with a few trillion vectors on a 100,000-server farm.”

I was starting to get dizzy. The new processors are backward compatible the EM, HS3x and HS4x processors, very convenient. Software development is supported by Synopsys’ ARC MetaWare Development Toolkit that includes an advanced C/C++ compiler optimized for the processors’ superscalar architecture, a multicore debugger to debug and profile code and a fast instruction set simulator (ISS) for pre-hardware software development. A cycle-accurate simulator is also available for design optimization and verification. Open-source software support for the processors includes the Zephyr real-time operating system, an optimized Linux kernel, the GNU Compiler Collection (GCC), GNU Debugger (GDB), and the associated GNU programming utilities (binutils).

ARC Processor EXtension (APEX) technology that enables the support of custom instructions is also included with these processors, as it is with all ARC processors. Mike mentioned that something like 80% of ARC users take advantage of this capability.

We also discussed the need many users have to understand what kind of performance they can expect from synthesizable IP in a particular technology. Mike described a very valuable service whereby Synopsys can run a benchmark implementation of a customer’s design in a target technology to reduce risk.  I know from first-hand experience how important this can be.

The stated application areas for the new IP are: solid state drives (SSDs), wireless baseband, wireless control, home networking, cloud networking and edge networking. Given the strong support for hardware accelerators, I’ll be interested to see what new applications are invented by the customer base. As I mentioned, please connect to Mike’s presentation at the Linley Spring Processor Conference if you can.

Also Read:

Security in I/O Interconnects

Synopsys Tutorial on Dependable System Design

Use Existing High Speed Interfaces for Silicon Test