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Synopsys announced an addition to its popular DesignWare IP portfolio recently that has some significant ramifications. The company announced the industry’s first complete USB4 IP solution. Before we get into the details of the announcement, let’s take a quick look at the USB standard and why it’s important.
Standards have a varying degree of impact and stickiness. Some last, others don’t. I can recall many years ago while working at a hardware accelerator company called Zycad we had a design services organization. One of the leaders in that group jumped on a very early spec of USB 1.0 and began aggressively building a team and infrastructure to support it for some very large companies. Many of us wondered why all the commotion about yet another communication standard. As history has proven, we were wrong and the design manger in question was right. The USB standard has been the centerpiece for wired data and power for over 20 years.
The 3.x versions of the standard did muddy the waters a bit with reference to multiple cable types. USB4 promises to fix all that with one connector and a converged connectivity standard. About a year ago, Intel announced it would contribute its Thunderbolt 3 specification to the USB Promoter Group and that formed the foundation for USB4. The standard physical connection going forward will look like a USB-C connector. Anyone with a late model Apple laptop will know what that looks like. The standard supports double the speed of USB 3.x (40Gbps vs. 20Gbps) with backward compatibility and over 50 companies are now supporting adoption, so things will be picking up fast.
Back to the Synopsys announcement. Leading edge IP announcements often detail a first set of deliverables with more to come, sometimes many more to come. This is not what Synopsys announced. Rather, the company is providing a complete IP solution for the new standard, including IP for the controller, router, PHY, and verification. Multiple high-speed interface protocols, including USB4, DisplayPort 1.4a TX, PCI Express, and Thunderbolt 3 are supported, so SoC designers have options. There is already a test chip tapeout of the IP in an advanced 5nm FinFET process, so robustness across process, voltage, and temperature variations has been demonstrated.
The new IP is designed to meet the functionality, power, performance, and area requirements of applications such as storage, PC, and tablet SoC designs as well as software development debug and easy deployment of artificial intelligence (AI) applications at the edge. The completeness of this offering should lower risk and enhance adoption for the new standard.
“As an active member of the USB Implementers Forum (USB-IF) for more than 20 years, Synopsys has helped to advance USB specifications while developing IP products that ease the integration and adoption of the latest USB technologies,” said Jeff Ravencraft, president and COO of USB-IF. “Initial USB4 products are expected to appear in late 2020 and the early availability of integration-ready USB4 IP is critical to helping designers incorporate the USB4 interface into their SoCs. Synopsys continues to support the industry by helping designers ensure interoperability and connectivity with billions of USB-enabled devices worldwide.”
“Synopsys has been at the forefront of providing high-quality, complete IP solutions through every generation of widely used interface standards such as USB,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “By providing a complete USB4 IP solution, backed by billions of SoCs shipped with DesignWare USB IP and our long track record of technical expertise, Synopsys enables designers to accelerate the integration of high-performance USB4 functionality into their SoCs with significantly less risk.”
As I listened last Friday to Automotive News Publisher Jason Stein interview Scott Corwin, managing partner and “Future of Mobility” practice leader at Deloitte Consulting, regarding potential COVID-19 recovery scenarios for the mobility industry I realized that the vast analytical powers of Deloitte had met its match. Corwin had more qualifications on his insights than actual data and knowledge regarding what the future might hold.
The Deloitte scenarios – described as “passing storm,” “good company,” “sunrise in the East,” and “lone wolves” – are based on taking into account the potential depth and severity of the pandemic and the resulting government response. What the scenarios reflect is Deloitte’s ability to “tell a story.” What they lack is a reflection and quantification of events unfolding in real-time and their implications for consumer behavior and economic outcomes.
In its attempt to capture the “big picture,” Deloitte is missing the obvious reality confronting consumers and business owners every day for the past three months. To survive and compete today we must rely on our own wits and our own resources. We cannot count on the government – any government – and we can’t even rely on traditional customer behavior.
There are four intractable variables we have all been forced to confront: the pandemic itself, the nature of mobility demand, the behavior of auto makers, the priorities of governments and regulators. Students of viral pandemics will know that COVID-19 will be with us indefinitely. There will be no end to the pandemic. So it is best to proceed based on that assumption and take all appropriate measures.
For mobility operators, consumer decision-making will be unpredictable so it is probably best to prepare for the worst while hoping for the best. Service providers and employers should seek the lowest common denominator as to acceptable protocols for returning to a new business as usual.
For auto makers this will mean real-time daily factory worker testing to achieve reliable and scalable vehicle production. For dealers it means online vehicle sales with touchless dealer-delivery must be accelerated. It will take time to ramp up testing. It will take time to ramp up touchless vehicle sales and delivery – but this is the new normal.
As for government assistance, the best that can be hoped for is financial assistance. By now, it is clear, at least in the U.S., that the government will not step in to lead testing and tracing activities, nor will it provide specific worker protection guidelines with appropriate enforcement. It is every man, woman, and company for him or her or itself.
Strategy Analytics reached out to consumers in the U.S. and the U.K. to ask them about their car buying, transport usage, and ride hailing plans post-COVID-19. The survey was conducted in May.
The survey reflected some key shifts in transportation preferences with long- and short-term implications – some of which may appear obvious:
Usage of all mobility services will likely fall in COVID-19 recovery.
Owned car usage is likely to remain unchanged or increase.
For ride-hailing UX, air/surface cleaning and plastic partitions are of modest importance to most riders.
Driverless technology does not add great value to ride-hailing UX, even during a pandemic.
With regard to car shopping, most but not all remote activities and features are of interest.
Though remote inventory browsing and sales completion are broadly appealing, some advanced tech-driven walkthroughs are not of great interest.
Smart or clean surfaces are of greater value than removable or customizable cockpit barriers.
For me, the most important takeaways from the study was the importance of partitions in taxis and ride hailing circumstances. While the interest in partitions was expressed by exactly half of respondents, that level of interest ought to tip that COVID-19 compensation measure into a must-do category. Dealers should also note the survey’s flagging of remote service as a high customer priority.
As we come to grips with what COVID-19 has done to our lives and our livelihoods we must be as honest and open as possible. Experts have made clear that COVID-19 is not a single thing. COVID-19 is a mutating coronavirus that even before its mutation was impacting different people and different communities in different ways.
Even as I write these words researchers are working diligently to understand precisely what COVID-19 is and how it effects human organisms. They are doing this research with the knowledge that COVID-19 itself is constantly evolving – as is our reaction to it.
Most notable of all, though, is the emotional reaction of us human beings. No two people have the same understanding or the same response to COVID-19. This was made personally clear to me as I pondered visiting my mother on the occasion of her 94th birthday next Monday.
I am not alone in seeking to visit my mother and the logistics involved in this decision are complex. My mother has four children – including myself – with nine grandchildren, two great grandchildren, two daughters-in-law, one spouse of a grand-daughter, and four unmarried partners of grandchildren.
My mother’s birthday is on Monday, June 15th; she lives at an assisted living facility in Connecticut where the next phase of re-opening (including restaurants and retirement homes) occurs June 17th; my preferred lodging provider, Marriott, re-opens to the general public June 20th. One of my siblings does not believe the coronavirus is dangerous at all. One of my siblings thinks it’s a bad idea to fly to Connecticut and then proceed to visit with my mother. The feelings of grandchildren, spouses, boyfriends, and girlfriends are most likely mixed.
My family is not unlike every other family in America – torn and tortured by COVID-19 decisions and societal and economic impacts. Mobility service providers, car makers,, and new car dealers will be best served by assuming: A) COVID-19 will never go away; B) every customer has deep COVID-19 concerns; C) governments are incapable of solving this crisis.
Under these circumstances it will be best to establish world class policies on cleaning, testing, and distancing in the hopes of returning to an operating environment – in vehicles, in factories, and in showrooms – that is acceptable to even the most fearful and worried among us. Only the lowest common denominator can get us through – which is why most of my family members will be joining my mother on her 94th birthday via Zoom. My mother has already become something of a medical miracle – but like all of us, she won’t outlast COVID-19. With a little care she can learn to live with it – like the rest of us.
According to experts, there are five key benefits of crowdfunding platforms: efficiency, reach, easier presentation, built-in PR and marketing, and near-immediate validation of concept, which explains why crowdfunding has become an extremely useful alternative to venture capital (VC), and has also allowed non-traditional projects, such as those started by in-need families or hopeful creatives, a new audience to pitch their cause. To date, $34 billion has been raised through crowdfunding initiatives, adding roughly $65 billion to the global economy in line with projections that show a possible $90 billion valuation for all crowdfunding sources, surpassing venture capital funding in the process. [2]
Limitations of Current Crowdfunding Platforms [1]
1. High fees: Crowdfunding platforms take a fee for every project listed. Sometimes, this is a flat fee while others require a percentage of the total proceeds raised by contributors. This cut into the availability of funds and strains the fundraising process when start-ups are looking for every single dollar to help.
2. Fine print rules and regulations: Not all platforms accept services as a possible project and demand real tangible products, such mindset cripple’s innovation and narrow the horizon of new products and services.
3. DIY Marketing and Adverting: With few exception platforms will not help with spreading the word about new startups, which means startups need to pay for marketing and adverting yet another strain on limited funds available for them, and take their focus from innovation and creativity.
4. Scam startups: In some cases, startups turn up as scams and produce nothing leaving investors with empty hands and no way to get their money back.
5. Intellectual property risk: In some case startups have no protection of their IP , and leaving them exposed to experience investors who can take the idea and enter the market early with all the resources they have.
With all the above limitations of current crowdfunding platforms, blockchain technology, among all its benefits, can be best put to use by providing provable milestones as contingencies for giving, with smart contracts releasing funds only once milestones establish that the money is being used the way that it is said to be. By providing greater oversight into individual campaigns and reducing the amount of trust required to donate in good conscience, crowdfunding can become an even more legitimate means of funding a vast spectrum of projects and causes. [2]
How Blockchain helps Crowdfunding
1. The Magic of Decentralization: Startups are not going to rely on any platform or combination of platforms to enable creators to raise funds. Startups no longer be beholden to the rules, regulations, and whims of the most popular crowdfunding platforms on the internet. Literally, any project has a chance of getting visibility and getting funded. It also eliminates the problem of fees. While blockchain upkeep does cost a bit of money, it will cut back drastically on transaction fees. This makes crowdfunding less expensive for creators and investors. [1]
2. Tokenization: Instead of using crowdfunding to enable preorders of upcoming tangible products, blockchain could rely on asset tokenization to provide investors with equity or some similar concept of ownership, for example Initial Coin Offering (ICO). That way, investors will see success proportional to the eventual success of the company. This could potentially open whole new worlds of investment opportunity. Startups could save money on hiring employees by compensating them partially in fractional ownership of the business, converting it into an employee-owned enterprise. Asset tokens become their own form of currency in this model, enabling organizations to do more like hire professionals like marketers and advertisers [1]
3. High availability and Immediate provision: Any project using a blockchain-based crowdfunding model can potentially get funded. Also, any person with an internet connection can contribute to those projects. Blockchain-based crowdfunders wouldn’t have to worry about the “fraud” that have plagued modern-day crowdfunding projects. Instead contributors will immediately receive fractional enterprise or product ownership.[1]
4. Smart Contracts to Enforce Funding Terms: There are several ways in which blockchain-enabled smart contracts could provide greater accountability in crowdfunding. Primarily, these contracts would provide built-in milestones that would prevent funds from being released without provenance as to a project or campaign’s legitimacy. This would prevent large sums of money from being squandered by those who are either ill-intended or not qualified to be running a crowdfunding campaign in the first place. [2]
A little over a month ago, I wrote about the substantial support that Silicon Catalyst and Arm were providing for chip startups. There have been many incubators for technology companies over the years. These organizations typically provide office space, some basic infrastructure, advisory help and sometimes access to seed capital. Silicon Catalyst is also an incubator, but there are some important differences in its model that make Silicon Catalyst a potent force to cultivate semiconductor innovation. See my prior post for more details on that.
The big news from Silicon Catalyst is that there is now a MEMS startup ecosystem available in the incubator as well as a chip startup ecosystem. While its interests in innovation and participation isn’t limited to MEMS, STMicroelectronics has joined the Silicon Catalyst ecosystem. This announcement isn’t the beginning of Silicon Catalyst’s MEMS startup ecosystem. The organization already has quite an array of technology available. Physical design is supported by Mentor’s Tanner L-Edit; design analysis is covered by ANSYS; modeling and simulation by Soft-MEMS and Coventor; test by EAG Laboratories; design rule checking by Mentor and design services by AMFitzgerald. And now, the world-class MEMS capabilities of ST will become part of this new and growing startup ecosystem. As was the case with Arm, ST is joining Silicon Catalyst as a Strategic Partner and an In-Kind Partner.
There’s more news on the MEMS front from Silicon Catalyst. Paul Pickering, a recognized expert in MEMS technology, has joined a growing team of full-time operational leaders at Silicon Catalyst as the Managing Partner of the MEMS startup ecosystem. Prior to joining Silicon Catalyst, Paul was the Chief Revenue Officer for Micralyne Inc. based in Edmonton Alberta, Canada. Micralyne is a world-renowned manufacturer of microfabricated and MEMS products for the communications, energy, life sciences and transportation markets. In 2019, Micralyne became part of Teledyne Technologies. Paul also served as EVP, sales and marketing for both Exar Corporation and Xpedion Design Systems, a venture-backed EDA company that was acquired by Agilent in 2006. Paul co-founded two start-up companies and has consulted with numerous other small and large technology companies. He has been associated with Silicon Catalyst since 2015.
I had a chance to speak with Paul recently. He explained that MEMS, or a micro-electromechanical system is essentially a device with mechanical and electronic components that is miniaturized to dimensions similar to those used to build integrated circuits. This technology allows the integration of sensors (e.g., pressure, temperature, air flow) with the microelectronics that processes the information gathered by those sensors.
Paul estimated there are 30 – 100 MEMS devices in a typical cell phone and over 100 MEMS devices in a late model automobile. The edge devices that comprise IoT systems have made MEMS truly ubiquitous. MEMS do leverage silicon processing technology but also require some unique fabrication and assembly enhancements. Consider that testing an integrated circuit requires digital stimulus but testing a MEMS device requires precise physical input.
This adjacency makes the design and manufacturing of MEMS devices a natural extension for semiconductor design and manufacturing. Paul explained that there is a lot of university research on MEMS structures and processing methods. This work has spawned substantial startup activity in the MEMS area and many of those startups are involved with Silicon Catalyst.
After my conversation with Paul, the extension of Silicon Catalyst’s chip ecosystem to MEMS started to make a lot of sense. Paul went on to say, “MEMS technology has become an important enabler for advanced chip designs across many markets. The research and startup activity associated with MEMS is quite robust, and I’m delighted to be leading the efforts to nurture these startups at Silicon Catalyst.”
Pete Rodriguez, CEO of Silicon Catalyst also commented, “I am pleased to bring a well-known industry expert like Paul Pickering on board to lead our new MEMS startup incubator in addition to welcoming STMicroelectronics as a new Strategic and In-Kind Partner. These developments help enable our mission of accelerating business growth for startups in the semiconductor market. The addition of ST’s market leading MEMS capabilities and Paul’s technology and management skills will expand our reach into rapidly evolving innovations in the sensor and actuator markets.”
ST Microelectronics also commented. According to the press release, “Innovation through silicon is driving advancements in technology. Hardware development is challenging, which is why Silicon Catalyst plays a key role in enabling silicon start-ups to develop their technology and fueling the new cycle of semiconductor innovation,” said Kirk Ouellette, Vice President Strategic Marketing and Strategy Development, STMicroelectronics. “ST has a strong collaborative R&D and industrialization culture, which makes a perfect fit with Silicon Catalyst. As both a Strategic and In-Kind Partner, ST looks forward to providing guidance and resources for start-up partners as well as gaining access to cutting-edge silicon innovation.”
If you are building a startup in the MEMS or chip area, Silicon Catalyst will be conducting a Fall screening review of all applicants. The deadline for submissions is July 6, 2020 and you can start the Silicon Catalyst application process here.
There is an old saying popularized by Mark Twain that goes “There are three kinds of lies: lies, damned lies, and statistics.” It turns out that no one can say who originated this saying, yet despite however you might feel about statistics, they play an important role in verifying analog designs. The truth is that there are large numbers of process parameters that can vary between chips and within a single chip. As much as foundries try to maintain consistency, there are variations that can affect chip performance and yield. It is absolutely necessary for project teams to understand the effects of these variations so they can determine product behavior and yield. Thus, statistical analysis becomes extremely important in the design process.
MunEDA is offering a webinar that reviews variation analysis methods and dives deeper into how they can be used efficiently to give designers what they need to ensure proper design performance. Michael Pronath, MunEDA Vice President of Products and Solutions provides a cogent introduction and summary of variation analysis methods. He starts with an overview that includes PVT corner analysis, Monte Carlo (MC) Sigma-to-Spec/Cpk, MC pass fail yield estimate and Worst Case Analysis (WCA) for yield optimization, design centering, high sigma analysis and hierarchical verification.
MunEDA’s WiCkeD Monte Carlo Analysis (MCA) comes with many features that make understanding the results much easier. Their results viewer shows the MC results and shows sigma levels against an ideal Gaussian fit. Complete statistical information is available for each design parameter in an easy to digest interface. MunEDA’s Quantile plot shows how well the results fit various parametric estimates. From this it is easy to see if the tails are long or symmetrical, etc. For each performance value, such as slew etc., users can look at the parameter influence analysis to see how sensitive they are to the process parameters. To help identify the source of sensitivities, they offer a view of hierarchical MC sensitivities that goes from block level to device or parameter level.
The real substance of the webinar is in the descriptions of the advanced Monte Carlo methods offered in MunEDA’s WiCkeD. We all know that the killing issue with MC is when it’s run brute force, huge numbers of simulations are needed to get meaningful results. For high sigma designs the number of runs required becomes astronomical. Over the last few decades tremendous progress has been made in devising methods to get meaningful results with much less time and resources.
Michael has a deep understanding of the methods and technology, so hearing him discuss the various approaches available in the MunEDA product line is fascinating and very intelligible. He goes through each of the following: quasi-random MC sampling, sequential sampling, scaled sampling, and combining PVT corners and MC sampling. I will not venture here to repeat or duplicate what he goes over. However, is it worth pointing out that the techniques he covers are extremely effective at saving analysis time by dramatically reducing the number of needed simulation runs.
Methods such as worst case analysis can even provide better results than what can be achieved with pure sampling methods. The methods also scale well for larger designs. Of course, MC was first used on memory cells, which were used many times in a single design, and were easy to simulate on their own. Now, much larger analog blocks and designs must be analyzed for yield and performance out to high sigma values because of high production volumes and high reliability applications.
Can we predict where bugs are most likely to be found, to better direct testing? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, again through a paper in software verification we find equally relevant to hardware. Feel free to comment if you agree or disagree.
This is a deeply technical paper. In the interests of space and time we’re going to abstract our high-level takeaways. Predicting defects in software has history in complexity analysis, measuring how difficult it would be to fully test a function. This paper is one of many taking a modern look at prediction, comparing complexity and other static metrics with machine learning guides to prediction.
In this paper, the “image” in which ML will recognize features is derived from abstract syntax trees extracted from the code, a novel feature the authors say provides a richer base for recognizing code semantics than do other methods. From this they build a recurrent neural network to learn syntactic and semantic features of the code. That is fed into a stage to capture local contextual information for code segments and next into an attention layer, a technique commonly used in machine translation to highlight critical features in the network. From there layers are run through activation functions to generate probabilities, in their case measured per input source file.
In their testing they ran training on Java projects with labeled bugs, looking at a range of different approaches from random forest networks, to deep belief networks and CNNs. They find that their method predicts more accurately than the comparison methods by 7%-14%, depending on test case. It should be noted however that their accuracy on average is ~50%. This is currently a technique for general guidance, not pinpoint accuracy.
Paul’s view
I see an analogy with a chess grandmaster, looking at the board to assess intuitively whether he sees a good position for white or a good position for black. Here you’re effectively looking at code to intuitively spot weak points. Definitely an interesting idea.
Generally, for a commercial tool I want to see well into the 90’s in terms of accuracy, but I have to admit I’m impressed that they can get to 50% accuracy just on eyeballing the code. On that alone I give it a thumbs up. I also noticed this is a very active area of research – there are a lot of related paper citations. I see nothing in this method restricted to software. Similar methods on Verilog and VHDL should be equally fruitful. I’d very much like to see research start in that direction.
There’s a lot to learn from the paper, worth a longer discussion, such as how they use LSTM to combine understanding of other nearby lines in the code with learnings from similar looking lines of code in other files or projects.
Here I’ll mention a more application-centric point. Should 50% accuracy mean this is only of academic interest today? I don’t think so. If, based on my intuitive eyeball I decide some code looks a bit dodgy, that’s maybe not interesting to invest my own personal time to figure out specifically why, but I could use that information to prioritize DV runs, run those tests first. I could use my “intuitive lint” solely for that guidance. Think of it as a smart scheduler, yet another way to squeeze more efficiency into the overall verification flow.
Jim’s view
You know, anything to do with AI, ML is hot. We’re still in that golden age for investment where the core technology is pretty solid and we’re still scratching the surface of possible applications. They’re popping up all over the place. Anywhere you can get something more than you can through traditional statistical methods, that’s interesting. I’m not too worried about the 50% accuracy. They’ll be able to tune the accuracy by application I’m guessing. Some applications may allow for more accuracy. I think this is an area that definitely warrants more investment. Someone should do a proof of concept fairly quickly with a handful of engineers, to see if they can increase the confidence level.
I’ll also add that this is extra interesting because Lint is getting hot again. Look at SpyGlass. Look at Real Intent. Put ML together with a verification method finding a second wind, two hot domains coming together? That is always going to look like a good bet.
My view
This is my home turf, so of course I’m going to like it. We did some work on McCabe complexity metrics back in Atrenta. I don’t know how many customers used that capability, but the concept remains intuitively reasonable. Combine that general principle with ML and training to fold some level of experience into the mix and it really starts to sound interesting. Now I’m wondering if a similar line of reasoning could apply to grading testbenches..
Johnny Shen CEO and Kenying Kwan Chairman of Board
Alchip was founded in 2003 by a group of Silicon Valley veterans that followed a similar path of working for semiconductor companies then moving to the EDA/IP/ASIC ecosystem. In fact, I used to play basketball with the Alchip co-founder/chairman during that time and can tell you he is a fierce competitor. Good thing too because the ASIC business is fiercely competitive, absolutely.
I saw in the news that Alchip is moving into the North America ASIC Market. Why now?
Coming to North America has always been part of our long-range plan. We started when we began putting assets in place beginning last November. There is huge demand in North America for the High-Performance ASICs that are our core competency. We didn’t so much make the decision to come as we have been asked by a number of large hperscalers, OEMs, and fabless device companies, both established and start-ups, to make our services more locally available. We’ve opened an office in Milpitas headed by Hiroyuki Nagashima, who formerly ran our business in Japan, and have staffed both design services and business management capabilities.
I know Alchip has a huge presence in Europe and Asia Pacific region, but you’re probably not a familiar name to many in the US. Can you tell a bit about the company?
We were founded in 2003 and all of executive management have Silicon Valley roots and are alumnae of top-tier North American engineering and business schools. As important as our pedigree is the fact that we registered record revenue for the second quarter of this year and anticipate record revenue for 2020, despite the current business environment. But more germane to the question: We became a publicly traded company in 2014. Some our more important technology milestones include completing 16nm and 12nm AI and automotive devices over the past 2-years and we will soon announce the successful tape-oust of sub-10nm designs.
ASICs are a huge industry. Is there any particular area you’re focusing on and why?
As I mentioned earlier, we are a high-performance computing ASIC company. A lot of ASIC companies try to be everything to everybody. But our legacy has always been to work on the leading-edge, hand-in-glove with our foundry partner,TSMC. Right now, for instance, we have one 7nm design in production and multiple 7nm tape-outs underway. This is the legacy that makes us attractive to hyperscalers and start-ups alike for high performance applications including artificial intelligence for cloud inference and training.
You talked a great deal about high performance computing, what are some of the specific attributes you bring to the challenges?
The ASIC business is complex from a both a business model and technical model perspective. We like to think that we put the “s” in Specific with a Flexible Business Model that has five different entry points and three different exit points. We have developed a design methodology for large, high power ICs, best-in-class 3rd Party IP, and advanced 2.5D package technology.
From both a business model and technology perspective it’s important to point out that we have developed a best-in-class IP portfolio to lower design risk and shrink time-to-volume. This allow us to focus on what we do best, then differentiate ourselves by working with others, then leveraging what they do best into a world-class ASIC flow.
Across the board,, our technology optimizes our design flows and methodologies to maximize our client’s time-to-design and time-to-market with maximum yield results.
OK, but it’s all about proof. Can you tell us about some of the other work you’ve done in other parts of the world?
Interestingly, North America is the beneficiary of world-class thinking. We have helped our clients go-to-market with industry-leading high-performance chips for supercomputing and server applications. To date, we’ve totaled had more than 400 advanced technology tape outs. That’s more than 20 advanced technology a year. That’s a number that I think any other company will have a hard time matching.
Can you give me a bit more detail as to what differentiates your design flow and methodologies?
Alchip’s design platform provides a unique clocking methodology that improves overall clock network capacitance and power; minimizes clock skew and insertion delay; and maximizes routing resource. Most importantly, it minimize on-chip variation to deliver significantly better yields at advanced nodes. Our design platform also offers a knowledge-based design flow for different applications in a manageable QoR range at each design steps to achieve superior power, performance and area witin a controllable design cycle for large scale designs. This translates into faster time-to-market and ensure one-pass silicon success.
Some ASIC companies decided to develop their own IP and yet you have turned to leading 3rd party IP partners. Why?
Building an HPC is complex and requires very specialized IP. Complexity requires collaboration and I think strategically, we recognize that no one company can cost-effectively be all things to all people. If it is commercially available IP, we want to collaborate, not compete with our best-in-class IP partners. However want to compete with our parters, but an IP block is not available, we won’t let that be a roadblock to success. So we focus on the specialized IP that they our IP partners don’t have. That’s why for instance, we provide proprietary macros such as D2D IP for PFN (12nm) APLinkl1.0..
Why is advanced packaging so important to high performance computing applications. What services do you offer?
Packaging is the new ‘Moore’s Law’ for high-performance computing challenges. Understanding and applying the technology is critical to meeting the demand for more functionality and greater performance in a smaller physical footprint.
We just rolled out a CoWoS program. This is new for us and new for the industry; it requires a significant investment our our part. But that investment is important to ease our customer’s long range roadmap concerns. CoWoS is critical to f today’s HPC ASICs because it incorporates multiple side-by-side die on a silicon interposer. The CoWoS service rolled out today covers multiple package designs. Looking further down the road we’re also working with customers and making investments in INFO technology. Yes, this requires a huge investment on our part. But it says to the marketing, we’re committed and ready.
COVID-19 really turned the world economy on its ear. How is Alchip fairing?
As I said earlier, we recorded a record first quarter have forecast a positive outlook for the remainder of the year. Our work force was minimally impacted and we are looking for a record second quarter and will be working on multiple 7nm tape-outs.
The impact on COVID-19 has been insignificant on our existing business. We are working at full capacity and people can work from home or the office. The associated travel ban may eventually slow business development. But we have repeat business from existing customers that has kept our pipeline full. For us, 2020 will be a record year. The current situation acutally favors the outlook for high-performance computing because of the growing importance and emphasis on cloud computing and that’s our sweet spot.
Congratulations. But what does the rest of the year look like?
The HPC market remains a major revenue contributor in terms of both production shipment. Project NREs will also account for a considerable part of the company’s total revenue. We are seeing that 7nm HPC shipments will be a critical factor to growth in the second half of the year. At the same time, we are seeing only non-significant impact from Covid-19
Looking forward, and in that same vain, what is the outlook for the High-Performance Computing Market, specifically, the High-Performance Computing Market in North America?
According to MarketsAndMarkets, the global High-performance Computing (HPC) Market was valued at $35.8 billion in 2019 and is expected to reach a value of $50.32 billion by 2025, at a CAGR of 7.02%. Growing adoption of HPC solutions and services across diverse industries such as datacenters, finanicial institutions, autonomous vehicles, and 5G infrastructure, is the major growth driver. Geographically, North America became the largest HPC market last year and is expected to hold that position through 2025. With Alchip’s track record for high-performance ASICs in cloud service appliations in other geographical areas, we are very well positioned to serve North America HPC customers with proven design solutions manufactured on TSMC leading edge technologies.
About Alchip
Alchip Technologies Ltd., headquartered in Taipei, Taiwan, is a leading global provider of silicon design and production services for system companies developing complex and high-volume ASICs and SoCs. The company was founded by semiconductor veterans from Silicon Valley and Japan in 2003 and provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced, including 7nm processes. Customers include global leaders in AI, HPC/supercomputer, mobile phones, entertainment device, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661) and is a TSMC-certified Value Chain Aggregator.
Moortec recently launched a new in-chip technology for highly distributed, real-time thermal analysis on TSMC’s N5 process. I got the opportunity to hear a live briefing from Moortec’s CEO, Stephen Crosher about this technology and how it expands Moortec’s capabilities. At first glance, this appears to be a product evolution kind of announcement. That is actually not the case, however. This new capability opens up new markets and applications for Moortec that are quite important. Let me elaborate.
Up to now, embedded sensing has focused on monitoring the overall process, voltage and temperature profile of the chip in a coarse-grained manner. The technology addresses device reliability and enhanced performance optimization by supporting power management and voltage/frequency scaling strategies. Moortec’s newly announced technology, called Distributed Thermal Sensor (DTS) is 7X smaller than previous versions and offers high accuracy measurements across a wide temperature range with lower latency through a higher sampling rate.
These improvements open up a new set of in-chip monitoring and optimization capabilities. The increased gate density of advanced FinFET technology presents new challenges in power optimization and lifetime reliability with a focus on thermal stress and electromigration. Stephen pointed out the need to monitor and manage aging effects is critical since FinFET devices have yet to experience 20 years of actual operating life.
DTS technology can now be placed not just at locations inside a cluster of CPU cores but the thermal sensors are so small they can be placed deep within individual cores, much closer to hotspots. The sensor data is then sent to a central hub. This flexibility allows fine-grained monitoring and control of temperature gradients across the chip as well as load balancing of the actual CPUs. The addition of more temperature sensing at strategic locations around the chip facilitates very tight control of temperature and power, allowing improved reliability and performance with lower power consumption. Thanks to the speed of the DTS devices all this can be done in real time.
Some applications of DTS and the associated market areas include:
Workload distribution and thermal load-balancing [Data Center, HPC]
Reduction of thermal stress for reliability [Automotive]
Enhanced user experience through better battery life [5G & Consumer]
Stephen went on to say: “We’ve seen a clear need for tighter thermal control of semiconductor devices. Multi-core architectures applied to AI, automotive, consumer and many other applications, benefiting from highly distributed sensing schemes to minimize system-level power consumption, optimize data throughput, and improve product lifetimes. We are confident that this extension to Moortec’s portfolio will enable our customers to maximize the performance of their silicon and further strengthen the long-term collaboration we have with TSMC.”
DTS technology design kits were made available in early 2020 and Moortec reports that the technology has already been licensed to several major customers. You can learn more about Moortec’s new distributed thermal sensor technology here.
Adnan Hamid, CEO of Breker, has an interesting background. He was born in China to diplomat parents in the Bangladesh embassy. After I’m sure an equally interesting childhood, he got his BSEE/CS at Princeton. Where, like most of us he had to make money on the side, in his case working for a professor in the Psych lab on artificial intelligence projects. This was before deep learning got hot. They were working on planning algorithms, more of a rule-based approach to AI. You tell the tool what endpoint you want to get to, and it figures out how.
Adnan joined AMD as a new grad, assigned to create testbenches, a task he quickly recognized would be mammoth and never-ending. He thought back to the work he’d done in the psych lab, wanting to try planning as an approach to test generation. Tell a tool this is the result you want to get to, give it a bunch of strategies and let the tool figure out reasonable test cases. From that, Adnan started Breker, where they pioneered portable stimulus starting from graph-based models because they’re easy for us simple humans to understand. Which of course evolved further into an even broader standard for system-level verification.
Breker has, among other capabilities, an app for security verification based on this standard. I wanted to get his take on why security verification is hard and what characteristics a solution needs to have, independent of any product viewpoint. That led to an interesting discussion.
Where Security is Most Important
We started with the business motivation. For all the advantages of the IoT, the disadvantage is that nothing now is a closed system. Everything by default can be hacked, traced, identities stolen, caused to misbehave. This is a huge problem for the DoD who face very sophisticated attackers. It’s a huge problem for the government and infrastructure, given the antiquated IT equipment on which they depend, it’s a huge problem for financial institutions, for businesses whose reputation rests on the security of their systems, and on and on. So #1, security now come with a societal price tag and a financial price tag, both huge. Much of it demands six-9’s (99.9999%) levels of security which somehow we have to prove.
Defining the Requirement
The second problem is not so much a technology problem as a people problem. How do you know you’ve tested enough? This is of course a classic verification problem but the classic solution – hit some level of coverage through randomized testing – doesn’t work. For security we need to check all the vulnerabilities of a particular target. It would take forever to get to six-9s. Plus a lot of what you’d be testing would be meaningless. What you really want is to test exhaustively within a realistic range of possibilities – like a semi-formal approach to dynamic verification. In fact, formal is already good at doing this at the IP level and in some sub-systems. What we need is to carry that concept over into full system testing.
How do you get there? Definitely not by writing a test, then another test, ad infinitum. Or by randomizing those tests. First, the range of possibilities needs to be captured in a way we can visualize easily. What are the possible master/slave paths in this system? For all the possible access and privilege combinations on those endpoints, which are allowed? Then in the memory map, which regions are accessible to which devices and under what conditions?
This might all seem rather trivial but Breker finds that simply constructing these access rule tables, no tools required, will often reveal gaps in understanding. Architect/designers have to fill out each entry and when they do, they realize they actually don’t know the right answer for some cases. Because we really are human after all.
Testing Compliance
Once the tables are filled out, tools can get involved. Now you’re back to that question of whether you want to hit six-9s or just do the best you can within a schedule. Which will of course depend on the application of the product. If you do have to hit six-9s, you have to do exhaustive testing, that semi-formal kind of testing at the system level. AI planning algorithms, starting from PSS models, are actually pretty good at that.
That’s Adnan’s view. If it’s critical to business or national security, you have to hit a high level of confidence. If you have to hit a high level of confidence, you need to use a semi-formal (realistic exhaustive) approach. And the best way to do that is through planning algorithms to generate exhaustive tests over a PSS graph.
In the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. In the second, Talking Sense with Moortec…’See no evil’, we bizarrely saw how Sir Francis Drake, Admiral Nelson and Clint Eastwood all had something in common with Mizaru, one of the 3 wise monkeys (Kikazaru and Iwazaru being the other two).
In the final blog, I would like to consider Iwazaru…’speak no evil’.
In polite society (think ‘Sense & Sensibility’ or ‘Pride & Prejudice’ in 19th Century British literature), it used to be said that children should be seen but not heard. Then as they grew up, they were expected to only politely comment on experiences…this politeness has (allegedly) carried through British society. Roll on 200 years and we are now accused of being the masters of the understatement, or more likely, not saying what we really mean!
This can pose a few challenges; under UK Health & Safety Law, it is as much an offence not to notify of a potential hazard, as it is to be the perpetrator of the offence, that doesn’t sit well with the ‘be positive’ messaging. It’s pretty clear that Iwazaru is likely to keep ‘shtum’.
There are so many rules about verbal etiquette…I’ve heard it said that one shouldn’t discuss money, religion or politics on a first date…wise words I’m sure, yet what do you talk about?! All these negative comments about talking up or speaking your mind. In history it is typically only the brave who speak out, often under hardship or duress…they are commonly seen as trouble makers or more recently as ‘the whistle-blower’. Yet, when does whistle-blowing become heroic having moved on from ‘telling tales’…I guess it depends on your point of view, for many it’s the definition of the truth.
Back to our SoC, we know we have a solid engineering team who want the truth as a collective entity. A great way to get at that truth, without relying on heroes or whistle-blowers, is the use of established in-chip monitoring IP. Whether you want to do the basics of monitoring temperature as an ‘insurance policy’ or do more in-depth analysis and optimisation by using multiple types of sensor to support, for example, Adaptive Voltage Scaling (AVS), these monitors can provide a lot of real-time data. My colleague Richard McPartland covered this in his recent blog entitled “Key Applications For In-Chip Monitoring … In-Die Process Speed Detection”
So is there hope for our three monkeys in SoC design? Iwazaru doesn’t want to talk negatively, Mizaru will always ‘turn a blind eye’ and Kikazaru only sees positive things, none of them is prepared to step up…it would appear that in-chip monitoring is the only option, to provide real time data about what is going on in your chip. And let’s be honest, surely no-one will keep quiet if they know of an issue, that could cost several million dollars in mask costs alone…so maybe the UK Health and Safety law should apply to SoC development too?!
If you have missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE
