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Accelerating Functional Safety Verification

Accelerating Functional Safety Verification
by Bernard Murphy on 10-24-2019 at 6:00 am
Categories: Automotive, EDA, Synopsys

FuSa Verification

Verifying a design for functional safety requirements for an IP or SoC per ISO 26262 is a complex process that can’t be encapsulated in one tool. Process complexities depend on whether the Tier1 or OEM is targeting safety-levels ASIL-A , B, C or D, where ASIL-D applies to anything truly safety-critical such as airbag controls or automatic braking and steering. A concern for any IP maker or SoC integrator is the implications of safety element out of context (SEooC) testing which may impose additional requirements from higher levels in the integration-chain. You also need to know that tools used in your flow meet the appropriate confidence levels (TCL) to align with the target ASIL level.

Figure 1: Synopsys Unified Functional Safety Verification Solution

Demonstrating and documenting compliance to the next level of integrators is what ISO 26262 compliance is all about and why you need safety managers, processes, culture and systematic methods to generate supporting documentation for your integrator consumers. That documentation includes FMEA reports to determine and justify where failures might occur so that safety mechanisms can be planned to mitigate those failures, and FMEDA reports to demonstrate that those mechanisms deliver as expected in simulated modeling of failures. Integrators also want to see tool safety manuals and certifications. All of this is needed in support of audits each member of the chain will run on their suppliers and that their consumers will run on them.

Anyone building IP or SoCs for modern automotive markets must invest significant resources and infrastructure to meet these needs. One way Synopsys aims to simplify and accelerate the task is in offering a unified functional safety verification solution. This includes more than I had expected, starting with a unified umbrella for fault campaign management. The tool that supports this step is the VC Functional Safety Manager which triggered part of my surprise in that it starts with FMEA analysis. That step has been historically left to design teams to handle since the questions it asks hovers on the edge between design know-how/intent and the design structure. You obviously can’t automate all of this away but it can be simplified through ability to import baseline architectural info from spreadsheets, ability to specify failure modes and safety mechanisms, and maps all of this to a detailed FMEDA.

The manager provides preliminary estimates of coverage through estimates of safety mechanism versus fault mode coverage and initial ISO 26262 metrics, so you can guide design improvements (for example adding or changing safety mechanisms). Design details for these estimates are extracted from existing RTL/netlist data for the design.

The manager will also execute the fault campaign, generating tool setup, running the fault sims and updating the ISO 26262 metrics and iterating as needed. Finally the manager will export the FMEA and FMEDA documentation, per component and for the SoC as appropriate, in a form that can be handed off to assessors and consumers at the next level of integration.

A lot of tools run under the manager. These include TestMAX FuSa (functional safety), a fast-static analysis (interestingly based on SpyGlass) to calculate early single point fault metrics and provide information on how to improve these grades. For analog circuitry, TestMAX Custom Fault will analyze analog/AMS designs for functional safety and coverage. For digital circuitry, the Z01X fault simulator runs concurrent fault sims in support of the fault campaign and the VC Formal app complements this by classifying faults according to controllability and observability reducing simulation cycles (why check a fault if you can’t observe the consequences of that fault?). ZeBu emulation enables longer run-time analyses. Also Certitude can be used to test process robustness against systematic fault, a nice way to add certainty to the completes of the analysis.

Amid all the significant overhead in instrumenting and demonstrating compliance, especially to expectations for autonomous and semi-autonomous vehicles (ASIL-D), I can definitely see value in this level of integration, automation and pushbutton generation of audit deliverables. Integrators need less things to worry about in their own compliance activities. You can learn more about the Synopsys safety verification flow HERE.

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WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am
Categories: Cliosoft, EDA, Events

In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for most design managers, analog designers, and EDA system architects to watch and well worth the time for most layout engineers as well.

I think all in the audience will understand the need for reuse. But we don’t always consider all the ways that reuse can be applied. In its most basic form, it simply means to reuse parts of a design that were already created in a different design project. It is a straightforward concept when we think about major functional blocks or subsystems. The larger the function that is reused, the more likely it may need to be modified for use in a new design. The fact that some modification may be needed is not necessarily bad; it is just a bit of additional effort. Modifying the previous IP may be much more efficient than creating a new solution from scratch.

It is also not simply major functional blocks that can be reused. You may also need to tune analog functions for a given process. Reusable analog IP is highly valued.  For example, a PLL design for use in on design may be easily reused in another design on the same process. While it cannot be directly reused in another process, it may be fine with some small modifications. This is especially valuable if the prior design is in silicon, and real performance data now exists for the block. Of course, the reuse of IP should also extend to all of your foundation IP – standard cell, IO cells, memory instances, PLLs, etc.

Saving all your IP is important. However, you need to be able to find the IP when you need it and also have the information you need to utilize that IP. ClioSoft’s designHUB® was built to make it easier to store, locate, and apply your valuable IP. designHUB® first started shipping in May of 2017 has been successfully deployed in many companies. This webinar goes into more detail on how you can use designHUB® in your design environment.

The primary presenter in the webinar is Karim Khalfan, ClioSoft’s Vice President of the Application Engineering. Karim has led the deployment of ClioSoft’s SOS7 design data and IP management into ClioSoft’s large customer base. He has also written several articles and white papers related to SoC design data management. Karim has a BSCS degree from the University of Texas and holds a patent on defining a universal data management adapter to be used for integration with any EDA tool. As you will see in the webinar, he is can clearly explain this technology.

To access the replay of this webinar, go to this page and click on “View recording.”  This webinar is one of several in this year’s SemiWiki Webinar Series. A list of upcoming webinars, as well as other available replays, can be found in the left column on the SemiWiki homepage.

 

Also Read

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

For EDA Users: The Cloud Should Not Be Just a Compute Farm

IP Provider Vidatronic Embraces the ClioSoft Design Management Platform

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LRCX – A recovery without memory? Korea share gain? TSMC bonus?- all upside

LRCX – A recovery without memory? Korea share gain? TSMC bonus?- all upside
by Robert Maire on 10-23-2019 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services

LAM will likely bounce on Korea gains & TSMC
Memory still sucks but TSMC is hot!
Korea upside from share gains?
Japan/Korea – The “Beer Barometer”

Looks like a good Q3….
We think when Lam reports their Q3 this wednesday it will likely be a positive catalyst for the stock as we think the report will be better than expected and guided and guidance for Q4 is likely to also be better than expected.

We are not suggesting that the cycle is over and we are “off to the races” but rather that there are some near term drivers that will cause a bounce off the bottom that we have been bouncing along on.

We would caution investors to not get overly excited as memory is still in the dumps and associated spending on memory is still weak at best.  Memory spend is not likely to recover any time soon given excess capacity and the current situation.

Logic/Foundry is Hot
Logic/foundry, however is hot, very hot, as we have heard from TSMC, which bumped up its capex plans by a whole lot and looks like they will have a very big “hockeystick” of spend at the end of the year. While a real, full blown recovery would be both memory and logic recovering at the same time, we will have to be happy with the industry bouncing nicely on a primarily logic lead recovery.

As we have repeated many times, we have been expecting a logic led recovery as memory remains over supplied as many machines remained idled.  Those machines have to come back on line first before the industry will even consider buying new memory tools…likely a long ways off.

Korea share gains at the expense of Japan
For several months we have talked about share gains we expect to see of US companies, like LRCX & AMAT versus Japanese companies like TEL & Hitachi in Korea due to the ongoing trade dispute between Korea and Japan which is far from over.

The dispute is far worse than the US/China trade dispute as it has pushed to the surface, decades long simmering animosity over past cultural/political issues.

Korea, its people, its government and its industry have all reacted very negatively, in unison, to Japan and its products.  We think this will mean substantial losses for TEL and Hitachi and gains for Applied & Lam as Korea seeks to replace all things Japanese with anything else.

Semes, a semiconductor equipment arm of Samsung is likely the biggest winner over the long run but in the near term its better to buy US equipment than Japanese.

We would expect to hear that Lam is doing better in Korea…wether they admit to or talk about share gains at the expense of the Japanese is another thing.

The “Beer Barometer”
In case you think I am joking or making this up take a look at Japanese beer sales in Korea.  Ashai beer from Japan has long been a dominant force in Korea with very large market share.

In August, Japanese beer sales in Korea were down 95% (yes you read that right) due to the dispute and a public boycott of Japanese beer.

While you may then think that this has nothing to do with semiconductor equipment, we have heard that the Koreans have asked that even US made semiconductor equipment, in some cases, not have Japanese manufactured sub components, so as to avoid anything related to Japan being imported into Korea

Japanese Beer Sales in Korea Link

Germany is benefiting at the expense of Japanese car makers as Korean purchases of Japanese cars is down 60%

Germany share Gains versus Japan in Korea

We think we will see similar, maybe not as bad, news as it relates to Japanese versus US made semiconductor equipment.

Collateral Benefit
Aside from what we think will be good news for Lam, we would also expect US suppliers to the industry to benefit. Two of our favorite suppliers to the industry that will definitely benefit from the upside we expect will be MKS Instruments (MKSI) and Ichor (ICHR).

We think there may even be more upside in these suppliers as Lam, Applied, ASML and KLAC have all run up in anticipation of some sort of a recovery but the sub suppliers and smaller market cap companies have lagged this run up.

This is how it works in all of the many past cycles we have been through…..the large cap names recover first followed a quarter or two later by the smaller cap names and sub suppliers to the industry.

The Stocks
We have no problem going out and buying in front of the quarter as we think there is an opportunity for a nice near term uptick, some of which we have seen a preview of.  In general, we think some of the smaller cap names have more upside as investors start looking around for other names not wanting to pay up for the large caps which have already had a strong run.

We also would not have any qualms about taking some money off the table after some strong quarterly news and gains as we may not get another catalyst after the quarterly reporting is done.  We also do run a small risk that after spending strongly for a couple of quarters, TSMC could slow down again before memory ever wakes up.  The odds of Korea and Japan kissing and making up is much lower and likely to be a longer term issue.  We still have the US/China trade dagger over the industries head but the administration seems to be pre-occupied doing other odd things and is less focused on trade…at least for a while.

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Statistically speaking you probably care about On-chip Variation

Statistically speaking you probably care about On-chip Variation
by admin on 10-22-2019 at 10:00 am
Categories: EDA, Events

There are some metaphorical similarities between reaching timing signoff and driving a car to your destination. Most of us get in the car, turn the key and push the gas pedal to make it go. While we might have a cursory understanding of what makes it go, there are actually a lot of “moving part” under the hood in each instance. For most car drivers it is not an issue if they don’t really understand the workings of their automobile. However, in the case of timing signoff, it’s pretty important that designers and engineering managers understand how things work.

Silvaco is in an interesting position when it comes to understanding timing signoff. They develop tools across the spectrum, from TCAD to SPICE, library characterization and timing tools. This is why their recent webinar about “On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective” was so interesting. With larger designs, smaller process nodes and higher volumes, timing signoff has become much more challenging over the years. On-chip variation has become a huge factor in determining silicon success and yield.

The webinar covered the various factors that lead to variation and how timing signoff methodologies have had to adapt to consider these new factors. When signoff methodology changes, the models that are used to drive the tools also need to change, to offer the information needed by the tools that use them. As a result, library characterization has been an area that has seen active development and significant advances.

The webinar presenter, Bernardo Culau, Director of Library Characterization at Silvaco, did an excellent job of reviewing how the needs and methods for timing signoff have evolved, from the early days of OCV modeling to the latest statistical methods. He provided an concise overview of the sources of variation and how each generation of sign off tools has progressed to reduce pessimism and increase efficiency to keep up with growing complexity.

Variation is caused by just about anything that can fluctuate during chip fabrication and later on during operation. On-chip variation specifically addresses difference in fabrication parameters, and operational temperature and voltage within a given die. This includes such things as channel width, dopant fluctuations, dishing, lithography issues, etc.

Bernardo untangled the alphabet soup of library formats and techniques. Among there were: OCV, SBOCV, AOCV, POCV and finally LVF. The variation modeling techniques needed vary with process node. Older nodes such as 90nm can get by with simpler models. By the time we get to 7nm, only the most advanced statistical methods can be relied on.

An important point he touched on was that statistical methods need to move from relying on Gaussian distributions and move to Moment Based LVF. More information needs to be included in the model files for the true distribution to be properly represented.

Bernardo concluded with an overview of the suite of Silvaco tools for library characterization. Their Viola tool uses parallel processing to complete cell characterization and is compatible with all the leading SPICE simulators, including Silvaco’s own SmartSpice. Cello is used for library migration, and they also offer a Liberty Library Analyzer. Their Jivaro tool can help improve efficiency by performing parasitic reduction with minimal impact on accuracy.  VarMan is their flagship solution for exploring the yield impacts on a design caused by variation.

If you want to improve your understanding of what is happening under the hood in timing signoff, this webinar provides a wealth of information. I for one like to know about the specifics, because the additional knowledge could make the difference between being stranded on the road or safely getting to your destination. The full replay of this webinar can be found through the Silvaco website.

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Safety and Platform-Based Design

Safety and Platform-Based Design
by Bernard Murphy on 10-22-2019 at 5:00 am
Categories: Arm, Arteris, Automotive, IP
1 Comment

Safety infrastructure in platform design

I was at Arm TechCon as usual this year and one of the first panels I covered was close to the kickoff, hosted by Andrew Hopkins (Dir System Technology at Arm), Kurt Shuler (VP marketing at Arteris IP) and Jens Benndorf (Managing Dir and COO at Dream Chip Technologies). The topic was implementing ISO 26262-compliant AI SoCs with Arm and Arteris IP, highly relevant since more and more of this class of SoC are appearing in cars. One thing that really stood out for me was the value of platform-based design in this area, something you might think would be old news for SoC design but which introduces some new considerations when safety becomes important.

A key aspect of platform-based design is being able to combine IP from multiple sources with differing levels of compliance to certain expectations, notably safety in this case. This can be most noticeable when you want to design part of the architecture to an ASIL D (safety critical) level while having enough safety diagnostic coverage to achieve ASIL B or C capabilities in other parts of the design. Designing an IP to this level entails a lot of overhead which may not be justified for safety-nominal (ASIL A/B) or even safety-indifferent (QM) components that you may want to use in your design.

How then can you get your SoC to higher ASIL compliance? The answer lies in being able to ensure that safety-nominal systems cannot corrupt safety-critical functions and can be tested or taken offline if they malfunction. This is all significantly mediated by the network between the IPs, as indicated in the figure above. Among other functions this requires health monitoring for all components and of course reporting faults to a safety controller which can channel problems upstream to decision-making functions (are we in trouble, should the driver grab the wheel, pay special attention, pull the car over to the side of the road?).

Monitoring functions (all provided through or together with the interconnect) include time-out checks for data requests, IP isolation through powering down the appropriate NoC socket connection to run live LBIST checks (at suitable times), and finally end-to-end ECC error detection/correction.

This ability to monitor, check and isolate faulty IP provides the means to ensure ASIL B,C or D compliance at the system level, but depends also on a “cannot-fail” subsystem called a safety island. This is a special function designed fully to ASIL D requirements, with lockstep CPUs, independent memories and run-time testable cache and many more mechanisms to ensure independence from the rest of the system. This safety island continuously monitors for faults and will report (at presumably programed levels of concern) to higher-level decision-making functions in the car.

Closing the loop, Jens talked about a reference platform design they have built at Dream Chip using these capabilities and how that has been spun into several production derivatives. The reference design is based on a quadcore A53, an ISP and vision processor, peripherals and memory interfaces, all connected through an Arteris IP Resilient NoC, together with the safety island. They have a cool demo of this functioning in an autonomous car according to Kurt.

Derivatives modify this platform with different numbers of CPUs in the cluster and different IP subsystems for the vision processor (GPU, NPU or a simpler processor) for active mirror replacements, front-camera and radar applications. In a pre-safety platform, spinning these derivatives would be no big deal. For systems requiring a higher ASIL (B, C, or D), it is a big deal and what makes it possible is this safety modularity around functions, the ability to monitor, isolate and ECC check through the interconnect and a carefully isolated safety island. All of these guarantee higher ASIL operation no matter what else in the SoC may go wrong.

You can learn more about this design by downloading the Arm TechCon presentation HERE.

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GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership

GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership
by Randy Smith on 10-21-2019 at 10:00 am
Categories: Events, Foundries, GlobalFoundries
1 Comment

I previously blogged on the GLOBALFOUNDRIES (GF) Technology Conference (GTC) held in Santa Clara, CA. The main takeaway that I shared in that blog was that GF’s announced “pivot” to a specialty foundry announced over a year ago, including its decision not to pursue 7nm and smaller nodes, appears to be working and GF is gaining momentum. There was not enough room in that blog to go into what I feel is another strategic decision GF made that is serving this transition well – its deep and broad relationship with Arm®. As many activities are going on between these companies, let me first break this into two broad categories – foundation IP and computing IP.

To have a thriving ecosystem on any given manufacturing process requires a strong collection of base-level IP, including standard cells, IO cells, memory compilers, and other basic building blocks. Collectively, I refer to this as foundation IP. Other IP providers and GF customers build their IP on top of the foundation IP. In my opinion, and I am admittedly biased1, TSMC’s rapid rise from $387M quarterly revenue in Q1 1998 to $2.5B by Q2 2006, coincided with its decision to have much of its foundation IP supplied by Artisan Components starting with TSMC’s 0.25-micron process in March of 1998. Arm announced its acquisition of Artisan® in August 2004. The foundry model took off in part due to the availability of foundation IP that was as good or better than what semiconductor manufacturers were developing themselves.

As a specialty manufacturer, GF has a large collection of processes. GF needs to make sure each process has a solid IP foundation. More than that, since each process is intended for a different field of use, that foundation IP should be tailored for the specific needs of designers using that process (e.g., low power design for a low power process, etc.) – a generic library is not very helpful. Along those lines, last month GF announced its 12LP+ solution, which makes use of Arm Artisan physical IP and ARM POP™  IP (more on POP IP later in this blog). These libraries are available now, and tape-outs are expected in 2020.

Arm Comprehensive Physical IP Platform at GF 12LP

  • Two logic library architectures (SC7.5, 9)
  • Nine memory compilers
  • GPIO for 1.8V and 3.3V
  • Specially optimized single rail 0.55V low-voltage compilers
  • Single-Fin Logic libraries to enable lowest power designs

Just two months ago, GF and Arm announced that they had taped out “an Arm-based 3D high-density test chip that will enable a new level of system performance and power efficiency for computing applications such as AI/ML and high-end consumer mobile and wireless solutions.” This unique project made use of breakthrough technology from both companies to come up with a more advanced packaging solution that should benefit GF customers needing a lower latency, higher bandwidth solution for applications such as AI and ML.

Gus Yeung

At GTC, there was a joint presentation by Ted Letavic, GF VP and Senior Fellow and Gus Yeung, GM VP and Fellow, Physical Design Group, Arm. Ted spoke about many innovations GF is developing under its specialty strategy, including IP coming from many other IP suppliers. There was again the GF Innovation Equation, which was prominent throughout the event and featured IP as a multiplier in supplying innovation to GF customers. Gus focused a bit more on ML,

Ted Letavic

showing the path Arm and GF are taking together in this rapidly evolving market. The partnership also includes Arm’s POP IP, which is a core-hardening acceleration technology. POP gives you Arm’s expertise captured in a way to accelerate your implementation of specific Arm cores while minimizing area, leakage, and dynamic power while also optimizing performance.

There is so much going on between GF and Arm, that I am sure to have left some things out. This relationship is certain to benefit both companies, and I am looking to further progress they can achieve together.

1 Randy Smith previously served as Artisan Components Director, Japan Sales, and Vice President of Corporate Ventures.

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WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior

WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior
by Daniel Nenni on 10-21-2019 at 6:00 am
Categories: Automotive, EDA, Events, Siemens EDA

Siemens Mentor recently announced PAVE360™, a very cool comprehensive pre silicon simulation environment. Autonomous cars are very popular here in Silicon Valley and quite safe on the highways since the average speed is 25mph (horrible traffic). In the city you need autonomous parking unless you want to waste precious time scavenging for a spot and climbing out your window since spaces continue to shrink and cars continue to grow. Kind of like airline seats.

The problem is that the lines of software code that power these new vehicles is increasing exponentially and validating the silicon and software integration is incredibly time consuming. I was very fortunate to work for one of the brilliant minds behind silicon simulation and I am honored to quote him here:

“PAVE360 represents the first output of an innovation process born from the combination of Mentor and Siemens employees, ideas, and technologies two years ago,“ said Ravi Subramanian, vice president and general manager of the IC Verification Solutions Division of Mentor, a Siemens business. “PAVE360 from Siemens delivers a comprehensive program to support the deep, cross-ecosystem collaboration necessary for our customers to develop powerful custom silicon and software solutions to power the autonomous vehicles revolution.“

To dig into PAVE360 further I organized a webinar with Mentor. I hope to see you there:

WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior

Abstract: Validating an SoC for intelligent vehicles requires much more than conventional methodologies have used. In fact, correctness is only defined in the context of the physical environment, vehicle dynamics and occupant survivability. Mentor/Siemens’ PAVE360 addresses this complexity with a holistic engineering methodology pioneered by the smartphone industry and refined to apply to intelligent vehicles.

Presented by David Fritz: With over 25 years of experience in the Semiconductor industry having held senior technical roles at NVidia, Qualcomm, Texas Instruments, and others, Mr. Fritz leads the global autonomous IC and validation initiative at Siemens Mentor. Mr. Fritz brings innovation and entrepreneurial drive of fast moving Silicon Valley companies to the Siemens Mentor team by applying transformative technologies to the challenges of autonomous and connected vehicles.

About PAVE360
Democratizing Automotive IC Design and Development
As advances in processing continue to play an increasingly prominent role in automotive evolution, carmakers are turning to custom silicon designs to deliver the “just right” blends of cost, power, performance and advanced features necessary to enable an autonomous future.

With PAVE360, chip design can be democratized, enabling carmakers, chipmakers, tier one suppliers, software houses and other vendors to collaborate on the development and customization of extraordinarily complex silicon devices for autonomous vehicles. PAVE360 delivers a robust platform for this collaboration, helping to speed chip design and software validation, and enabling the creation of model-specific silicon for the first-generation of self-driving cars.

PAVE360 establishes a design-simulation-emulation solution that scales from individual blocks of a system-on-chip’s (SoC’s) IP, to hardware and software on the SoCs, to vehicle subsystems, and up through deployment of vehicles in smart cities – a true “chip-to-city” approach based on the increasing digitalization of the automotive industry.

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ASML – In Line Qtr but big bookings – Logic Strong! Memory ? EUV?

ASML – In Line Qtr but big bookings – Logic Strong! Memory ? EUV?
by Robert Maire on 10-20-2019 at 6:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services, TSMC

ASML in line QTR with big Orders
Near term slippage w long term upside
Logic is strong but memory recovery unknown
EUV is finally a reality/commercialized

In line quarter- supplier slippage expected in Q4
Results were revenues of Euro 3B and EPS of Euro 1.49, more or less in line with earnings estimate if a tad bit light in revenue. Outlook for Q4 is Euro 4B with 4 EUV systems slipping into 2020 due to supplier issues (now resolved)

Logic is leading the recovery… Obviously TSMC
Over 70% of orders are from foundry/logic customers as everyone is getting in the queue now that EUV is in commercial production. TSMC is the leader in real EUV and likely accounts for the largest portion of those future EUV orders

Memory still an unknown
Several months ago we said that the recovery would be led by logic as the memory recovery would take longer than most people expected due to the sidelined capacity amid excess supply and weak pricing.

This is becoming clearer to most people as we have heard from Micron, which was weaker than many expected and now clearly hearing from ASML that memory business remains weak with unknown timing of a recovery.
Some are expecting a recovery early in 2020, but we would not get our hopes up as it could take all of 2020 to get memory back on track.

Huge orders Euro 5B and 23 EUV tools
ASML is selling out its capacity very quickly as we are now seeing a virtual avalanche of orders. EUV has been proven and no customer wants to be excluded from the party or perhaps run out of capacity.

Part of the huge ramp is the large ramp in the numbers of layers in a chip made with EUV, going from a few ,like 3-5, going to 12 to 15 (depending upon whom you believe). Basically the number of tools has to increase proportionately with the number of layers. Memory is still a long way away from using EUV so in our view the current memory weakness, while impacting DUV and immersion is not slowing down EUV.

In a perverse way, the weakness in EUV demand for memory is likely of benefit to the logic side of the industry as it doesn’t compete for limited EUV tool availability.

40 plus EUV tools should be very easy to book for next year as we are more than halfway there. I think we can get there even without any memory recovery.

Not worried about supplier slippage
Given the complexity of an EUV tool and the huge supply chain we are certainly going to see issues here and there. The fact that its only a one quarter slip suggests its not a big or systemic problem.

We would likely take a longer term view as to the overall trend and worry less about the actual ship date and whether it falls within one quarter or another. ASML is not in a “turns” business like dep and etch or other relatively simple to assemble tools.

It down to production execution
As we are now past the milestone of actual commercial EUV production we are past the point of invention, luck, and pain and suffering trying to get the technology to work and more focused on production issues and the ramp of manufacturing.

To be sure, there are still many issues out there, pellicles, resist, reticle inspection, but what we have is working well enough to push forward on the number of layers using EUV and thus more tools.

We have covered ASML for almost 25 years with much of that history watching the EUV saga play out, so it is interesting to see the final conclusion (or perhaps beginning) of an era.

The stock –
Priced for perfection in an imperfect world, but still pretty good. ASML’s stock has steadily climbing based on the view of a recovering chip sector. Some stocks in the space have gotten a bit ahead of themselves but we think ASML’s value increase is justified given where we are with EUV, the strong logic/foundry demand and overall positioning in the market. Some investors may be unhappy with the slippage, but we are less concerned as you have to look at the longer term.

Some investors may be unhappy with a quarter that was just “in line” but given the memory weakness, we think “in line” is very good performance as ASML is working with one hand (memory) tied behind its back.

Overall we remain constructive on the stock and would look at pull backs or weakness as an opportunity to build or enhance a position going forward.
The stock is not cheap but the performance and positioning support the valuation.

We think that ASML has the lowest China/US trade problem exposure (though not zero) and EUV sales are less impacted by near term economic gyrations as the backlog is likely very strong. All in all a relatively defensive position in a very cyclical industry.

Summary
ASML remains a virtual monopoly, with a huge defensive moat, upside potential in revenues and margins and a leading technology position. We expect margins and therefore profitability to increase steadily as EUV ramps over the next few years leading to long term upside. It remains one of our top picks in large caps in the space.

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TSMC – Solid Q3 Beat Guide- 5G Driver – Big Capex Bump – Flawless Execution

TSMC – Solid Q3 Beat Guide- 5G Driver – Big Capex Bump – Flawless Execution
by Robert Maire on 10-19-2019 at 6:00 am
Categories: Foundries, Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

TSMC puts up solid QTR, Capex increase for 5NM and capacity increase, 5G/mobile remains driver- HPC good 7NM, 27% of revs- Very nice margins!

In line quarter-Good guide
TSMC reported revenues of $9.4B and EPS of $0.62 , more or less in line with expectations, perhaps a touch below ” whisper” expectations which had been growing along with the lead times for 7NM. Gross margin was a nice 47.6%.
Q4 is expected to be between $10.2B and $10.3B with gross margins between 48% and 50%. This revenue outlook is well above current street expectations.

Large bump up in Capex
We have been talking about a logic led recovery, in chip equipment, given the strength at TSMC. TSMC bumped up their 2019 capex from $12.5B to $14 to $15B with initial outlook for 2020 to be similar to 2019.

This suggests a bit of a hockey stick like capex spend in the current Q4 of 2019.This hockey stick will show up in a better than expected guide from tool companies

We think this is likely a strong mix of not only 5NM spend but also 7NM capacity related spend given better than expected demand and long lead times currently seen by customers.

Capex intensity, currently at 40% is expected to come down in 2020 and further come down in 2021 to 30% to 35%

5G and mobile remains the big upside in demand
In our view, customers in the mobile space are all rushing to get to market first with 5G devices to try to stake a claim to market share and early dominance. This has created a strong “land rush” of orders to insure enough 5G chips to power those devices.

7NM was 27% of total sales which supports this strong demand and suggests strong pricing ability as well.

This is quite a strong ramp from the start of 7NM earlier in the year. We are sure that HPC (read that as AMD) is also clearly helping to drive demand over the top.

Smartphone was 49% of revenue with HPC at 29%.

We don’t think any significant portion of sales was due to inventory build or channel stuffing as fears of trade ware related cut offs have subsided in the market.

TSMC winning on both yield and packaging
In our view, we think that TSMC is attracting more customers and thus the longer lead times as they have both better yields and better packaging technology.

We think Samsung has had more struggles with yield and coming up to speed despite (and potentially because of ) EUV implementation.

We also think that TSMC’s advanced capabilities in packaging allow it to offer customers more and better options in 2.5 and 3D packaging.

As customers look for other strategies outside of Moore’s law scaling, such as “chiplets”, these packaging options become a critical differentiating and enabling technology. Some customers, such as AMD, are currently banking on advantages of a “chiplet” architecture.

Collateral impact on equipment companies
TSMC’s report , and large capex increase, confirms our view that there is a strong near term pick up in equipment demand despite memory “sucking wind”.

We think most equipment suppliers will report at least in line or likely better than expected results in the current quarter but more importantly will guide even higher going forward as orders from TSMC hit their order books.

This is very much in line with our “logic/foundry led recovery” that we have talked about for several months. While not a rip roaring semicap recovery, its better than the bouncing along the bottom that the industry has been stuck with and importantly puts an upward bias on business even though the slope may be low without memory.

The Stock – Nice quarter, but perhaps not up to the unrealistic expectations of the market
Its clear that chip stocks have been on a tear and along with the stocks, and so have expectations. Much of this in TSMC’s case is a combination of Apple talking about increasing supplier orders by 10% along with the extended lead times at TSMC 7NM. We think expectations and the stock both got a little bit ahead of themselves such that when the company reported an excellent quarter, such as it did, that investors were unimpressed as it didn’t blow away numbers.

We would use any weakness as an entry point to add to positions in TSMC.

They are now more dominant in foundry than ever before and if anything they are lengthening their lead over number two Samsung. Near term demand looks very good, margins are good and getting better.

Most importantly, TSMC continues to push Moore’s Law forward without any visible hiccups or delays…..perhaps they make it look too easy…..perhaps they should have a one quarter “oops” to make them look human and reset investors expectation of perfect performance in technology execution.

They have a very long runway of upside in 5G , with little competition, ahead of them. They are also the “real” engine behind AMD’s success and will get their fair share of the upside associated with that and other HPC business.

We like companies that have dominant or monopolistic-like positions, great execution on technology with a strong defensive “moat” . All this usually combines to show up in financial performance and future upside which we clearly have with TSMC.

We continue to be a buyer of the stock and would be more aggressive on pullbacks. Our only significant cautions would be trade and macro economic risk that all chip companies share.

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The New Silvaco CEO is SURGING!

The New Silvaco CEO is SURGING!
by Daniel Nenni on 10-18-2019 at 6:00 am
Categories: EDA, IP

One of my great pleasures in the semiconductor industry is meeting the people who have brought us to where we are today, at the forefront of modern life. One of those people is Babak Taheri, now CEO of Silvaco who I spent time with yesterday. Babak started in semiconductors around the same time I did 30+ years ago. He has a PhD in EECS and Neurosciences from UC Davis, a Masters Degree from San Jose State and his Bachelors from San Francisco State so he is truly a Silicon Valley native. He held executive positions in engineering, R&D, and corporate management at leading technology firms including Freescale, Cypress Semiconductor, Apple, Invensense, and SRI International, he is also the holder of 28 patents.

Babak came to Silvaco as the CTO last year and was bumped up to CEO in August when David Dutton decided to go back to the equipment manufacturing business. David however is still involved with Silvaco as the Vice Chairman of the board. Having known Silvaco since its beginning I am VERY impressed by this move.

Next week is the Silicon Valley Silvaco SURGE event where Babak will be giving the keynote : From Atoms to Systems. As we all know the semiconductor business is very systems orientated now so it will be interesting to see Babak’s perspective, absolutely.

SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, explore smart application integration, and discover innovative techniques for advanced semiconductor design. The event includes eight demo stations, a catered lunch, and cool prizes and giveaways for attendees.

  • Executive keynotes
  • Technology Tracks: TCAD, EDA and Design IP
  • Roadmap presentations
  • Customer and partner presentations and success stories
  • Eight unique demo stations
  • Networking with industry experts

SURGE is at the Santa Clara Marriott again this year so you can bet that the food will be great. Take a look at the agenda, after the keynotes there are EDA, TCAD, and IP tracks so something for everyone. As much as I love EDA, I’m all about IP these days so that is where I will be.

I hope to see you there!

About Silvaco
Silvaco Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia. For more information, visit Silvaco.com.