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March 27, 2020July 6, 2020

Filling the ASIC Void – Part 1

Filling the ASIC Void – Part 1
by Mike Gianfagna on 03-27-2020 at 6:00 am
Categories: Delta, Semiconductor Services
5 Comments

It started slowly at first. Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model. I was there for the first five years and the last six years. In between, I was chasing other dreams – that’s a story for another day.

The evolution of the ASIC business is actually a long story. Again, I’ll save that for another day. The “ASIC void” situation we face is easier to describe. I’ll focus on two forces of nature in this market – LSI Corporation, AKA LSI Logic (LSI) and IBM Microelectronics (IBM). Of course, there are many more excellent companies that have served this market, but the fates of LSI and IBM will illustrate my point. Beyond eSilicon, I’ve worked in the ASIC sector for most of my career and I can tell you that both LSI and IBM were formidable competitors.

Both had a substantial focus on the custom chip business. Both had an extensive library of differentiating semiconductor IP, access to and deep expertise with relevant manufacturing technologies, a bullet-proof design methodology and all the resources needed to get a chip through prototype and into production, repeatably and reliably. Both companies also had a flair for working closely with the customer, thanks to their extreme focus on the custom chip business.

In short, they were both very, very hard to beat. Around 2013, there was a disruption in The Force and things started to change. First, Avago bought LSI. Then there were more acquisitions, with LSI ultimately being deep inside a large, substantial and diversified company called Broadcom. Singular focus on ASICs is hard to accomplish in such an environment. Two years later, GLOBALFOUNDRIES (GF) acquired IBM Microelectronics. Did that make GF a foundry, an ASIC vendor or both? There was debate on that topic. Then, three years later GF spun out its custom silicon business (the IBM part) as Avera Semiconductor. Then, last year Marvell acquired Avera.

All this churn created a void in the ASIC market. At eSilicon, we heard the same thing from many customers – they were looking for a dedicated, focused ASIC company that had the IP, the right technology experience, a strong production track record and a willingness to be a partner to build game-changing, critically needed custom chips. Thanks to its deep expertise in 2.5D packaging and complex digital designs, eSilicon became a tier-1 ASIC supplier for the data center, high-performance networking, AI and 5G markets to help fill that void. A few months ago, eSilicon was acquired by Inphi with certain assets sold to Synopsys.

Late last year Dan Nenni posted a discussion on this topic, Where has the ASIC Business Gone? In that post, Dan referenced DELTA Microelectronics, a company with a specific focus on ASIC. Then last month, Presto Engineering acquired DELTA. I’ll discuss the relevance of these events in my next post on this topic. For now, I would like to catalog what it takes to be a contender to fill an ASIC void:

Design and manufacturing expertise in a market that requires custom chips
Differentiating IP and the skills to integrate it into a customer design
A solid design methodology and the discipline to enforce it
A willingness to partner with the customer – a shared vision for success is key
A solid track record of successful bring-up of designs in target systems

I invite you to ponder this list. Are these the right attributes to be a focused ASIC supplier and thus address potential gaps in this market?

March 26, 2020July 6, 2020

COVID-19 Chip Cycle – How deep, long and what shape?

COVID-19 Chip Cycle – How deep, long and what shape?
by Robert Maire on 03-26-2020 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
4 Comments

It is a demand driven downturn – harder to predict
It may not be “business as usual” after this virus
What systemic changes could the industry face?

Trying to figure out another cycle-driven by inorganic catalyst

Investors and industry participants in the semiconductor industry who are used to normal cyclical behavior of over and under supply driven by factors emanating from the technology industry itself now have to try to figure out the impact of an external damper unlike any we have previously seen.

We are truly in uncharted waters as the tech industry in general has continued to grow, perhaps at varying rates, but we haven’t seen a broad based, global downturn such as we may be in line for. Many would point to the economic crisis of 2008/2009 which was certainly negative but does not have the same “off a cliff with no skid marks” that the current global crisis has for its sudden sharp drop.

We would also point out that the semiconductor industry is famous for self inflicted cycles based on over supply from building way too much capacity. In fact we would argue that most chip cycles are self inflicted and most are supply side initiated.

The COVID-19 cycle is demand based as we haven’t had a sudden change in global chip capacity, as fabs have kept running but we can expect a demand drop that has yet to fully manifest itself.

Technology is always the first to get whacked
When the economy goes south, technology buys are the first to suffer. Consumers continue to buy food, shelter, fuel and guns & ammo but don’t buy the next gen Iphone or bigger flat screen. 5G can wait while I put food on the table. Given that smart phones are nothing more than containers of silicon, its clear that the chip industry will get it in the neck.

There are also a lot of other things in addition to the virus such as the oil market issues and the election which has all but been forgotten about. The effects on the technology market will persist long after the virus has been arrested and controlled.

There was a baseline assumption at one time that all the economic damage associated with COVID-19 would certainly be contained within the calendar year such that any business delayed by the virus out of H1 would just make H2 of 2020 that much stronger and it would all be a “wash” on an annualized basis.

The current trajectory as to the the length and depth of the “COVID-19 Chip Cycle” is unknown as to whether it is “V”, “U” or “L” shaped. Right now it feels at least like a “U” if not an extended “U” shape (a canoe…).

The chip industry was barely a quarter out of a “U” shaped memory driven down cycle, having been pulled out by technology spending on the foundry/logic side when we were ambushed by COVID-19.

Two types of spending cycles; Technology & Capacity
There are two types of spending cycles in the chip industry, technology driven spending versus capacity driven spending. Capacity driven spending is the bigger part and technology spend is more consistent.

The industry has been on a technology driven spending recovery that was just about to turn on a capacity driven push. While we think that technology driven spending to sustain Moore’s Law and 5NM/3NM will continue, we think that capacity spending will likely slow again, especially on the memory side as a drop in demand will get us back into an oversupply condition that we were just starting to emerge from.

The supply/demand balance in the chip industry remains a somewhat delicate balancing act and the COVID-19 elephant just jumped on one side.

One could argue that foundry/logic which has been the driver of the current recovery could falter as 5G, which is a big demand driver, is a “nice to have” not a “gotta have” as we could see 5G phone demand slow before the Iphone 12 ever launches.

On the plus side, work from home and remote learning for schools is clearly stressing demand for server capacity and overall cloud services which should bode well for Intel and AMD and associated chip companies

China Chip Equipment embargo likely off the table for now
At one point, not too long ago, it felt like we were only days away from imposing severe restrictions and licenses on the export of technology that could help China with 5G, such as semiconductor equipment.

We think the likelihood of that happening any time soon is just about zero as the US can’t do anything to upset China as China supplies 90% of our pharmaceuticals, the majority of our PPE (personal protective equipment) like masks, and probably a lot of ventilators.

Politicians have bigger fish to fry with fighting over a trillion dollars of a rescue package and pointing fingers at one another. So at least COVID-19 has crowded out other things we had to worry about in the chip industry. Probably no one cares if the Chinese dominate 5G as there won’t be a lot of demand to dominate.

There may be permanent systemic changes
There is a lot of complaining about corporate “bailouts”, stock buy backs, executive pay etc; associated with any financial rescue package. While much of this may be focused on airlines and other more directly impacted industries, even if the chip industry never gets a dime of bailout money there will likely be increased scrutiny on corporate behavior in general and there could even be some legislation associated with it.

Buy backs which have become very big in the chip industry during good times may become less popular. We would not be surprised to see an increased focus on semiconductor manufacturing moving to Asia as people have figured out we don’t even make our own pharmaceuticals any more.

Is an out sourced global supply chain a bad thing?
The technology industry has prided itself on how far and wide the supply chain for a technology can be. An Iphone is perhaps a poster child for supply chain logistics.

The problem is that broad and wide supply chains have been exposed as our soft underbelly, during COVID-19, that make us more susceptible to interruptions, even in some far away place, that can completely shut us down.

These supply chains work like dominoes that can cause a cascading effect to bring things to a halt.

Truly multinational companies that rely on the free movement of people and goods across borders with no friction might think twice about how they will deal with another global crisis as there is a high likelihood we will experience another one….not a question of if but rather when. That we haven’t had a global disruption like COVID-19 before is probably just pure luck.

Boards of large companies will start to ask and demand for plans to deal with global disruption just as they have local contingency plans today to deal with local disasters.

Will the world get less interconnected?
Maybe moving back to a more vertically integrated, local model is safer albeit a little more expensive. There is likely some political will for more isolationist economic behavior after COVID-19 is over.

The semiconductor industry in the US is a shell of its former self as most production and much technology has been off shored with the primary driver being economic savings which mean less when you can’t produce anything.

Balance sheet safety
We would point out that the semiconductor industry does seem to be relatively flush with cash as compared to cycles past. However there are some companies in the space that have a significant amount of debt (in some cases more than their cash) on their balance sheet.

The US has over 7 Trillion dollars in corporate debt, now more than ever, and about a third of our GDP. In previous cycles in the chip industry we have seen some companies go under due to debt load.

The popular model to lever up balance sheets with debt could potentially reverse itself as there are a long list of companies that will have their hand out for the government bailouts.

If we slow down buy backs, getting out of debt should be easy for most but there still are some that are deeply in debt, just a little less so in the semiconductor industry.

There are a handful of companies that could see COVID-19 related weakness push them closer to debt problems

M&A rebound?
Could we see the government loosen up its dislike of corporate mergers. If companies make the argument that getting together makes them stronger and more resistant to global issues then we could see a few more larger mergers happening under the right circumstances. There is probably not a lot left in the semiconductor industry but there are a few deals that didn’t happen that could be revisited….after all , valuations are a lot more attractive now, especially for those companies that have dry powder in the form of cash.

Stock valuations are attractive
We are seeing stock valuations that are now looking attractive on a P/E basis much as the stocks were getting too expensive just a couple of months ago.

We are seeing multiple contraction rather than expansion as some stocks are discounting an unrealistic level of contraction much as they were previously discounting too bright a future. Much of the sentiment will be determined on Q1 conference calls which are coming up. If we were management, we would probably take a very conservative view as going out on a limb will not likely be rewarded.

Investors also want to see a company reset expectations in one swoop rather than a death by a thousand cuts over the next few quarters

Investors will want some sort of comfort that we are at or near a COVID-19 bottom even though that may not be the real case… just lie to me and make me feel better…..

March 26, 2020July 18, 2025

SpyGlass Gets its VC

SpyGlass Gets its VC
by Bernard Murphy on 03-26-2020 at 6:00 am
Categories: EDA, Synopsys

It’s a matter of pride to me and many others from Atrenta days that the brand we built in SpyGlass has been so enduring. It seems that pretty much anyone who thinks of static RTL checking thinks SpyGlass. Even after Synopsys acquired Atrenta, they kept the name as-is, I’m sure because the brand recognition was so valuable.

Even good things must evolve. Synopsys verification has a strong “VC” brand and it was natural that SpyGlass should fold in under this, still with a strong connection to its founding identity. So now we have VC SpyGlass, in line with VC LP and VC Formal.

This isn’t just a rebranding. Synopsys have put a lot of work into this next generation SpyGlass, including 3X performance increase in half the memory, always a plus in any context and especially valuable when you want to screen full-chip RTL. But there are a number of other significant advantages which resonate all too clearly from my time at Atrenta.

One is a 10X reduction noise. Anyone who’s ever used a static verification tool knows that noise can be a huge pain. Simulation will only catch bugs exercised and detected by the tests you run. Static verification will catch all bugs within the range of checks it performs. But the devil’s bargain you make for this completeness is that it will also catch many things that aren’t problems or are just different manifestations of a problem it already reported. You may have to wade through a whole bunch of spurious errors to find the one or two real problems you need to fix.

Reducing this noise level is a very big deal. I remember the Atrenta team working on methods to compress errors by root cause as one approach to noise reduction. Other techniques used formal methods to weed out structurally apparent errors which are not functionally possible. It sounds like Synopsys has extended these methods further.

Another key advantage I cannot over-emphasize is completing compatibility with the Synopsys implementation tools. This starts with synthesis compatibility. Under the hood, SpyGlass does a quick synthesis so it can run a lot of checks on an elaborated graph. How effective (or noisy) that is depends very much on how well it mirrors the ultimate real implementation. At a superficial level that’s not such a big deal. You use one of the standard open-source synthesis platforms and you’re good, right?

Wrong. There are a number of places where using a different synthesis solution is likely to generate false errors or miss real errors: datapath and mux inferencing are just two examples. When a tool gets this stuff wrong, pretty soon it’s thrown out. We always wrestled with trying to match DC behavior as closely as we could, but you can never do as well as you can when using the real thing. No longer a problem in VC SpyGlass.

Another related problem was matching behavior in constraints. There’s a lot of useful information in those constraints to flag clocks, resets and so on. Especially useful in CDC and reset analysis and can also be useful in other aspects of static analysis. When is a clock really a clock? You can try to infer this bottom-up by just looking at the RTL, tracing back from register clocks. But that’s not foolproof. Constraints fix the ambiguity, but you need to interpret them the same way the implementation tools do. Not so bad in vanilla SDC but potentially much more difficult in Tcl. Again, no longer a problem in VC SpyGlass.

Finally, VC SpyGlass has unified debug with Verdi. Let’s face it, Verdi is the de facto standard for functional debug in the industry. Everybody uses it. We had an interface to Verdi when I was at Atrenta. But there are interfaces and then there are native integrations. Native integrations are invariably faster and more capable. You can switch back and forth between VC tools, retaining a consistent VC interface throughout.

I’m happy to see VC SpyGlass fully integrated the VC family. It confirms the value we created and a continuing bright future for the technology. You can learn more about VC SpyGlass HERE.

Also Read:

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Navigating Memory Choices for Your Next Low-Power Design

March 25, 2020July 18, 2025

Security in I/O Interconnects

Security in I/O Interconnects
by Mike Gianfagna on 03-25-2020 at 10:00 am
Categories: IP, Security, Synopsys

I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.

First, a bit about Richard. He is the technical marketing manager for DesignWare PCI Express (PCIe) Controller IP at Synopsys. He previously worked at NCR Microelectronics, Symbios Logic and over two decades at LSI Logic, including the position of architect for host interfaces there. Richard has seen a lot of complex design challenges in his career, and we spent some time discussing data/interconnect security in the context of his experience and the plans Synopsys is developing.

Richard began with a big picture view of the problems associated with a lack of security. Looking through a “cost” lens, here are some facts:

2013 – Target stores hacked; breach may have cost over $250 million
2016 – Yahoo hacked, dropped sale price to Verizon by $350 million
2017 – Equifax hacked, costs approaching $1.4 billion to date
Consumer confidence loss even more expensive

A lot of discussion around the issues above has centered on software. Things like encryption and establishing trusted sources. To make all this efficient and to add additional layers of protection requires a look at hardware. This is where Richard spent the bulk of his time during our discussion. At a hardware level, the “attack vectors” become quite diversified. Consider the following:

Supply chain: substituting a compromised component before end delivery – e.g. NIC card, BMC controller, SSD, potentially even CPUs, etc.
In-system component compromise: reprogramming (“hacking”) the firmware of a “good” device for nefarious purposes
Physical access attack: using a logic analyzer, oscilloscope, or purpose-built “monitoring” hardware to snoop system operation
- Edge devices are often in exposed areas subject to easy physical access

Do you have a headache yet? I did. All this can be quite subtle as well. Richard provided a good illustration: How many times have you plugged your phone into a USB port at an airport for a re-charge? Are you sure it was only charging your phone? We all know a USB port can do a lot more than charge your phone.

Next, Richard outlined the work going on at Synopsys to deal with these, and other security challenges. An effective approach requires a wide-ranging look at hardware security, from the SoC and its IP through the entire ecosystem. To begin with, one must consider servers, routers, individual PCs, tablets and smartphones. Getting into the details of each architecture is required as well. That opens up components such as CPUs, I/O controllers (NVMe, SAS, Ethernet, etc.) and even power and cooling units. At a lower level, IO interconnects (e.g. PCIe, CXL, etc.) need to adopt security features to provide a solid foundation for everything else. The bulk of our discussion was on security in I/O interconnects.

How does one secure I/O interconnects reliably? There are a lot of parts to the answer. Here’s a short version of the list:

Authentication
- Standard bodies are working on specs that leverage certificate concepts from the software world
- Components provisioned at manufacturing time with certificate chain & key pairs that can be matched against their pre-provisioned expectations
Measurement
- Run-time component checking of firmware, configuration, FPGA bit files, chip straps, etc.
- Components send signed measurement data to host for comparison with allowed values
Integrity (data encryption)
- Ensuring data on the wire is secure from observation *and* tampering

Getting all this done requires a lot of work from standards bodies and the associated implementation of those standards in hardware. Richard explained that Synopsys is active in many of these efforts and will be ready to support those standards in its IP and tools when they are announced. PCIe is the dominant I/O interconnect and this is likely where a lot of early work will be done across areas such as authentication, measurement and integrity.

Compute Express Link (CXL) is a new high-speed CPU interconnect standard. Richard pointed out that it’s based on PCIe and will likely build on PCIe security additions. It turns out there are a lot of interlocking pieces to affect real improvements in network and data security; low-level key exchanges, measurement algorithms and packet definitions that support encryption and integrity information to name a few. The last one has the added complexity of handling replay mechanisms for link error recovery in a way that doesn’t weaken cryptographic strength.

I have a new appreciation for the complexity of hardware-level security after my discussion with Richard. It’s comforting to know that Synopsys is active on many fronts and will be prepared to support early adopters. Expect to hear a lot more about these efforts over the coming months. Start thinking about how this impacts your future design work NOW and then talk to Synopsys. You can also learn more about the Synopsys DesignWare IP solutions for PCI Express here. You’ll find lots of information and resources there, including several good videos.

March 25, 2020January 11, 2022

Low Energy Electrons Set the Limits for EUV Lithography

Low Energy Electrons Set the Limits for EUV Lithography
by Fred Chen on 03-25-2020 at 6:00 am
Categories: Lithography
2 Comments

EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.

Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon. Photoelectrons initially released by EUV absorption are expected to be ~ 80 eV, and release energy by further ionization, producing secondary electrons [1]. The photoelectrons and secondary electrons can lose energy by plasmon generation as well [2]. Electrons with energies as low as 1.2 eV can still expose resists [3]. Dissociative electron attachment (DEA) can also occur at very low energies [4]. Consequently, the image is affected by the “blur” resulting from the spread of these electrons. An example is shown below in Figure 1. Even a few nm blur or a few nm blur difference can degrade the sub-20 nm image’s sensitivity to dose variations.

Figure 1. Secondary electron blur is modeled as a Gaussian function involved with the original non-blurred image, fitted with a Gaussian as well [5].

How far can the electrons travel?
A simple Monte Carlo simulation demonstrates that a fairly wide spread of electron paths is possible even with a low mean free path. In Figure 2, four simulation runs are shown, each representing 30 collisions of an electron, where the electron travels 1 nm in a random direction between collisions (including mostly elastic (no energy lost or gained) and inelastic low energy (<0.1 eV) transfers with phonons [6]), is shown to lead in some cases to travel distances approaching 10 nm. The “r” result is the net distance (regardless of direction) from the original starting point, treated here as (0, 0, 0) , i.e., r=sqrt(x^2+y^2+z^2).

The distribution of distances is shown in Figure 3. The mean final travel distance was 5.1 nm with a standard deviation of 2.25 nm, while the mean max distance was 6.5 nm with a standard deviation of 1.5 nm. Even with a limited sampling (N=20), the distribution of travel distances covers a fairly wide range of nanometers.

Figure 2. Simulations of electrons going through 30 collisions, mostly elastic, the remaining assumed to be low energy transfers to phonons [6].

Figure 3. Distribution of final and maximum travel distances after 20 simulation runs using the conditions of Figure 2.

Increasing or decreasing the travel distance between collisions will naturally increase or decrease the net travel distance as well. The inter-collision distance of 1 nm is comparable to the step size used in other recent related work [7, 8]. Measurements of resist loss from low energy electrons are also in excess of 1 nm [3, 4]. Of course, more collisions accumulated will lead to a wider range of travel distances as well. Another possibility to consider is net positive charge at the starting position, which might slow down further migration by Coulomb force attraction. Recent work, however, suggests this could be negligible [8].

Takeaway Thoughts
For a fully rigorous and complete EUV resist model, in addition to the aerial (photon-only) image input, we need to have the accurate representation of low energy electron blur. These simulation runs hint that it is somewhat oversimplified to have a fixed electron blur value. It is more prudent to consider a range of blur values. This is better for giving the process variation (PV) bands.

Appendix (Technical Note):
Simulations are run on an Excel sheet. Starting point (0, 0, 0). Random spherical coordinate system angle theta (0 to 180 deg) and phi (0 to 360 deg) selected using RANDBETWEEN function, while jump step is fixed (1 nm for this article). Jump = (jump step * sin(theta) * cos(phi), jump step * sin(theta) * sin(phi), jump step * cos(theta)). This is iterated 30 times for the runs in this article.

References
[1] J. Torok et al., “Secondary Electrons in EUV Lithography,” J. Photopolym. Sci. and Tech. 26, 625 (2013).

[2] G. Denbeaux et al., “The role of secondary electrons in EUV resist,” EUVL Workshop 2014.

[3] I. Bespalov et al., “Key Role of Very Low Energy Electrons in Tin-Based Molecular Resists for Extreme Ultraviolet Nanolithography,” ACS Appl. Mater. Interfaces 12, 9881 (2020).

[4] B. Sun, “Low-energy electron-induced chemistry of PMMA,” Master of Science thesis, July 2014.

[5] https://www.linkedin.com/pulse/from-shot-noise-stochastic-defects-dose-dependent-gaussian-chen/

[6] B. Ziaja, R. A. London, and J. Hajdu, “Ionization by Impact Electrons in Solids: Electron Mean Free Path Fitted Over a Wide Energy Range,” J. Appl. Phys. 99, 033514 (2006).

[7] H. Fukuda, “Localized and cascading secondary electron generation as causes of stochastic defects in extreme ultraviolet projection lithography,” J. Micro/Nanolith. MEMS MOEMS 18(1), 013503 (2019).

[8] L. Wiseheart et al., “Energy deposition and charging in EUV lithography: Monte Carlo studies,” Proc. SPIE 9776, 97762O (2016).

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
by Mike Gianfagna on 03-24-2020 at 10:00 am
Categories: Ansys, Inc., EDA, Events, Synopsys

I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration between Synopsys and ANSYS to solve them, you have a real winner in my view. The details of how industry-leading extraction and analysis tools from ANSYS are tied to industry-leading implementation tools from Synopsys are clearly worth a look.

You can view this webinar on Tuesday, March 31, 2020 at 10AM Pacific time. Mark that on your calendar. The registration link is included, above. I’ll repeat it later. Let’s first review who’s presenting at this webinar and what they’ll cover.

The first speaker is Rahul Deokar, director of marketing and business development for the Synopsys Fusion Design Platform, with focus on signoff products, including RedHawk Analysis Fusion. Rahul begins his presentation with a review of the technology trends and associated challenges and dangers presented by things like dynamic voltage drop and power integrity. He then presents Redhawk-SC and discusses its capabilities to effectively deal with the problems under discussion.

Rahul then describes RedHawk Analysis Fusion, a two-year project to combine the analysis capabilities of ANSYS RedHawk with the implementation capabilities of Synopsys ICC II/Fusion Compiler. Signoff quality analysis with a native integration to an industry-leading implementation flow at the block, subsystem and full-chip levels. This really got my attention.

Getting into more details, Rahul explains the benefits of block-level signoff accuracy, robust place & route optimization and the ability to access the latest distributed processing capabilities of RedHawk-SC. Rahul then summarizes the added features in the new release of RedHawk Fusion. The list is quite extensive and impressive. He also covers the power integrity design flow that is enabled by RedHawk Fusion. To give you a feeling for the what’s included, I’ll just mention one of the many capabilities covered:

Dynamic Power Shaping: optimizes peak current and reduces dynamic voltage drop via clock scheduling.

All the capabilities presented are illustrated with real design examples, including case studies of a 7nm design. To whet your appetite further, machine learning is also employed in the release.

Marc Swinnen then presents the details of ANSYS RedHawk-SC, their next-generation product for 7nm and below. Marc is the director of product marketing at ANSYS. The next-generation architecture for RedHawk was developed about four years ago and it’s called SeaScape – RedHawk-SC is based on it. Marc explains that the motivation for this new platform was two-fold:

Address the capacity requirements resulting from the dramatic increase in analysis at advanced nodes
Extend IR-drop analysis to handle the multi-physics considerations of new effects such as electromigration, inductance and thermal gradients

Marc explains that SeaScape uses the same approach for data organization that is used by big data and artificial intelligence tools. Marc goes on to detail the distributed architecture of SeaScape. The discussion is quite impressive and improvements in speed, capacity and efficiency are substantial. Marc also discusses chip-package co-analysis, a critical item for advanced 2.5 and 3D packaging.

Rahul then presents the results of actual customer designs using RedHawk Fusion. Several application areas, all at advanced nodes and from different parts of the world are covered. The webinar concludes with a Q&A session that shines more light on the types of designs this flow can be used on.

The depth of detail presented during this webinar, along with the unique collaboration of two major design tool suppliers make this webinar a must-see. You can register for the webinar here. Don’t miss this one.

Also Read:

Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Navigating Memory Choices for Your Next Low-Power Design

Hybrid Verification for Deep Sequential Convergence

March 24, 2020July 27, 2020

Mentor Masterclass on ML SoC Design

Mentor Masterclass on ML SoC Design
by Bernard Murphy on 03-24-2020 at 6:00 am
Categories: AI, EDA, Emulation, FPGA, Siemens EDA

I was scheduled to attend the Mentor tutorial at DVCon this year. Then coronavirus hit, two big sponsors dropped out and the schedule was shortened to three days. Mentor’s tutorial had to be moved to Wednesday and, as luck would have it, I already had commitments on that day. Mentor kindly sent me the slides and audio from the meeting and I’m glad they did because the content proved to be much richer than I had expected.

Lauro Rizzatti and Steve Bailey provided an intro and confirmed my suspicion that this class of solutions is targeted particularly at hardware accelerators. Could be ML, video, audio, wireless algorithms, any application-specific thing you need to speed up and/or reduce power in an edge device. Maybe a surveillance product, which had been getting by with a low-res image and ML software running on a CPU, now you must move to 4K resolution with faster recognition at the same power. You need a hardware accelerator. For this tutorial they use TinyYOLO for object recognition as their demo platform.

Russ Klein came next with a nod to algorithm design (in TensorFlow using Python) then algorithm partitioning and optimization. Sounds like a big yawn, right? Some basic partitioning, changing bus widths and fixed-point sizes, tweaking here tweaking there?

Wrong – very wrong.

This may be the best tutorial I have seen on the topic, from explanations of the mechanics behind convolution to how that maps into implementation. Not just for toy implementations, but through stepwise improvements all the way up to arrays of processing elements, close to the state of the art.

The process starts with a TinyYOLO algorithm running in TensorFlow executing on a laptop. This reads camera frames within a video feed, a scene of some kind, and aims to recognize certain objects – a dog, a bike, a car – and output the same scene feed with labeled bounding boxes around those objects. He noted that a single inference requires 5.2B floating point operations. It’s not practical to do this in software for real time recognition response.

They ran profiling on the software and of course all those multiply-accumulate (MAC) operations stuck up like a sore thumb, so that’s what they want to drop into hardware. Since this is a pitch for high-level synthesis (HLS), they want to convert that part of the algorithm to C++ for later synthesis to RTL.

But not all at once.

Russ and following speakers emphasized the importance of converting and verifying in steps. They break their neural net up into 9 stages and replace each stage, one at a time in the Python flow with a C++ implementation, verifying as they go. Once those all match, they replace all those stages and verify again. Now they can experiment with architecture.

Each stage come down to a bunch of nested loops; this is obviously where you can play with parallelism. As a simple example, an operation that in software might take 32 cycles can be squished into 1 cycle if the target technology makes that feasible.

Next is a common question for these 2D convolutions – what are you going to optimize for in on-chip memory? These images (with color depth) are huge, and they’re going to be processed through lots of planes, so you can’t do everything in local memory. Do you optimize to keep feature maps constant, or output channels constant, or use a tile approach where each can be constant over a tile but must change between tiles? Each architecture has pros and cons. Experimenting with different options in the C++ code, to first order, is just a matter of reordering nested loops.

However which option really works best relates in performance and power directly to on-chip memory architectures. Russ talked about several options and settled on shift registers, which can nicely support a sliding 3×3 convolution window and allow multiplies within that window to run in parallel.

Ultimately this led them to a processing element (PE) architecture, each element containing shift registers, a multiply and an adder. They can array these PEs to get further parallelism and were able to show they could process ~700B operations per second running at 600MHz. Since 5.2B operations are required per inference, that’s ~7ms per inference by my math.

There was also an interesting discussion, from John Stickley, on the verification framework. Remember that the goal is to always be able to reverify within the context of the original TensorFlow setup – replace a stage in the Python flow with a C++ equivalent or a synthesized RTL equivalent and reverify that they are indeed equivalent.

They run the TensorFlow system inside a Docker container with an appropriate version of the Ubuntu OS and TensorFlow framework, which they found greatly simplifies installation of the AI framework and the TinyYOLO (from Github), along with whatever C++ they were swapping in. This also made the full setup more easily portable. C++ blocks can then become transactors to an emulation or an FPGA prototype.

There’s a huge amount of detail I’m skipping in this short summary. You can get some sense or the architecture design from this link, though I hope Russ also write up his presentation as a white-paper.

March 23, 2020August 27, 2020

Reducing Your ASIC Production Risk!

Reducing Your ASIC Production Risk!
by Daniel Nenni on 03-23-2020 at 10:00 am
Categories: Delta, Semiconductor Services

Managing the ASIC manufacturing is one of the biggest challenges of chip projects.

Building an ASIC supply chain requires specific expertise. Throughout the process you’ll be confronted with hundreds of decisions that will require specific knowledge in order to be addressed correctly, avoid costly mistakes and lose time. How should your ASIC be designed for testability? Which packaging technology will ensure the optimal performance? How to
optimize test throughput and build up for volume production? How to quickly identify the root cause of failures?

Below highlights of some key points. For the full content, read the full paper, 5 Best Practices for Successfully Managing an ASIC Supply Chain.

Plan for Problems
With ASIC manufacturing, things may go wrong, and in most cases, they do. A design can change midway through the ASIC development process; an RF wire bond issue may be discovered; and yield may drop due to an unknown reason.

Analyse in advance the risks associated with your specific ASIC development project and make sure that both you and your partners clearly understand the risks and have a corrective action plan. Consider issues like response time, service, and relationship between vendors.

Aim for Just-in-Time Manufacturing
ASIC manufacturing can present a dilemma for smaller companies. On the one hand, producing larger quantities allows reduced costs and improved quality. On the other hand, producing larger quantities requires handling ASIC stock with special conditions.

Start by analysing the longevity and cumulative volume expectations of your product. Then, assuming you don’t have the facilities, resources and conditions to store chips, try to plan for ‘just-in-time’ ASIC delivery.

Start with Quality, Then Price
At some point, every company that markets a product containing ASIC faces the manufacturing dilemma – how to go into production using the cheapest, most efficient and highest quality methods? Is it using an external full-turnkey partner or taking full ownership and working directly with semiconductor suppliers (Customer Owned Tooling, or COT model).

Each model has pros and cons. As an earlier stage company, cutting production costs may be one of your priorities. Nevertheless, you still need to focus on your design core competencies rather than take the full burden of manufacturing. Best is if you can find a hybrid, ASIC to COT model, which offers the best of both worlds.

Learn More
Read the full e-book, 5 Best Practices for Successfully Managing an ASIC Supply Chain

March 23, 2020January 12, 2021

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
by Mike Gianfagna on 03-23-2020 at 6:00 am
Categories: AI, Cadence, EDA

Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one reason why a recent press release from Cadence regarding the new release of their digital full flow caught my attention.

The press release details the features of the new digital full flow release, which further optimizes power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and AI. According to the press release, “the flow features multiple industry-first capabilities including unified placement and physical optimization engines plus machine learning (ML) capabilities, enabling design excellence with up to 3X faster throughput and up to 20% improved PPA.”

Another key feature of the new release is iSpatial technology, which Cadence defines as follows: “The iSpatial technology integrates the Innovus™ Implementation System’s GigaPlace™ Placement Engine and the GigaOpt™ Optimizer into the Genus™ Synthesis Solution, providing techniques such as layer assignment, useful clock skew and via pillars. The iSpatial technology allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database.”

There are many significant capabilities discussed and results presented in the press release. I’d like to focus on the ML capabilities. In my previously mentioned post about Cadence, Paul Cunningham detailed the strategies Cadence uses for ML deployment. One was “ML inside”, where heuristic algorithms improve thanks to ML and another is “ML outside” where tools learn from prior runs in order to improve future results. It’s interesting to watch a strategy be used in an actual product, and it seemed to me this press release was announcing just that regarding AI/ML.

I got a chance to speak with Kam Kittrell, senior product management group director in the Digital & Signoff Group at Cadence about the press release and my hunch about AI/ML strategy implementation. It turns out the “unified placement and physical optimization engines plus machine learning” are primarily an application of “ML inside”, allowing the tool to do a better job predicting things like downstream delays and congestion. There is also an element of “ML outside” here as well since the flow can train with the details of a particular user’s design – things like libraries and delay settings, so the optimization takes on a design-specific focus. Hearing about a comprehensive strategy on AI/ML one week and then seeing it in action the following week is noteworthy.

The press release includes detailed quotes from MediaTek and Samsung executives about how ML is used for real designs and what results are delivered. Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence also comments on the impact the new flow release is having on customers. Another memorable quote came from Kam during my discussion with him. Regarding the importance of PPA optimization, which is an industry-wide focus, Kam pointed out that “millions of dollars are spent on tens of picoseconds”. I felt this comment accurately captured the dramatic numbers that characterize SoC design.

You can learn more about Cadence digital design and signoff capabilities here. You will find lots of good resources, including a discussion of all the steps in the design flow as well as videos and relevant articles.

March 22, 2020August 27, 2020

A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law

A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law
by Daniel Nenni on 03-22-2020 at 10:00 am
Categories: EDA, Events, Wally Rhines
3 Comments

Wally Rhines is one of the most prolific speakers the semiconductor industry has ever experienced. Wally is also one of the most read bloggers on SemiWiki.com, sharing his life’s story which is captured in his first book: From Wild West to Modern Life the Semiconductor Evolution.

On April 2^nd at 10am PDT we will host Wally on a live webinar for a presentation on his second book which will be made available for download during the event. There will also be a live Q&A. If you cannot attend the live version a link to the replay will be sent to all registrants. If you are not available to attend and want to ask Wally a question please include it in the comments section and I will make sure it gets answered. This is a must attend event, absolutely!

REGISTER HERE FOR REPLAY

Let’s start with Wally’s updated biography, yes he has a Wikipedia page, followed by the book introduction:

Wally Rhines is widely recognized as an expert in business value creation and technology for the semiconductor and electronic design automation (EDA) industries.

Dr. Rhines was CEO of Mentor Graphics (a “Big Three” EDA company with $1.3B+ revenue) for 24 years, has served on the boards of four public companies, managed the semiconductor business of Texas Instruments (TI), and is a spokesperson, writer and highly-sought-after speaker for the high-tech industry delivering more than twenty keynotes per year.

Dr. Rhines currently serves as CEO Emeritus of Mentor, a Siemens Business, consults for investors, corporations and the U.S. government on strategic directions, value creation and technology and serves on public and private boards.

Business achievements include major turnarounds, both at Texas Instruments, through his creation and management of the digital signal processing business, and at Mentor, where he managed more than 3X growth in revenue and a 10X increase in enterprise value before acquisition by Siemens AG.

Dr. Rhines’ technical expertise includes semiconductor design, process engineering and manufacturing as well as financial modeling of trends and value creation.

He has been deeply involved in global business development including projects in China and India.

As CEO and Director, he has managed businesses through difficulties including unfriendly takeover attempts, favorable outcomes for both the company and the activists, with three of the world’s leading activist investors, and volatile economic and business cycles.

He continues to seek new opportunities to grow businesses, particularly through private equity, consulting and personal investing.

https://en.wikipedia.org/wiki/Wally_Rhines

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Predicting Semiconductor Business Trends After Moore’s Law

Introduction
In 1952, AT&T sold licenses to patents and basic know-how for their newly developed solid-state transistor technology to any buyer willing to pay $50,000. As a result, the companies who chose to commercialize this technology competed on a level playing field with no initial competitive barriers such as patents or existing market share. They created what soon became the most significant example of a free market business operating in a world economy. Regulations for this new industry didn’t exist and the new companies created a hotbed of new ideas, new business approaches and financial growth. It was the “Wild West” of business. As a result, the semiconductor industry today provides the most significant example in recent history of free economics in worldwide commerce.

Without a formal licensing process, IBM’s development of the Winchester disk drive had a similar effect beginning in 1956. Over the next thirty years, the number of companies competing in the hard disk drive business peaked at eighty-five. Clayton Christensen of Harvard University did a study of the disk drive industry because it could be analyzed using nearly ideal conditions of supply, demand and free market economics (see Christensen, Clayton, “The Innovator’s Dilemma: When New Technologies Cause Great Firms to Fail”, Harvard Business Review Press, May 1, 1997.)

He used disk drive companies as a surrogate for other industries in the same way that biological researchers use fruit flies. Fruit flies are born, mature, reproduce and die in 24 hours so you can study biological effects over many generations. Christensen’s thesis was that the disk drive industry provided a research vehicle similar to fruit flies in that these companies were founded, grew and went out of business in a very short period of time.

The semiconductor industry exhibited life cycles that were longer than the disk drive industry but had the same free market characteristics. Over time this unfettered competition followed trends in a worldwide market that could be quantified and used to predict the future. Over the past forty years or more, I’ve collected data and made presentations showing how the actual economics and technology of the semiconductor industry can be used to predict its future direction and magnitude. This book is built upon excerpts of presentations made during the last thirty years that analyze the business and technology of the semiconductor industry. In most cases, the figures in the book are copies of the original slides as they were presented during one or more of those presentations. In general, they show how predictable the semiconductor industry has been. They should also provide insight into the future of the industry.

—Dr. Walden Rhines, December 2019

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