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Verific Design Automation, with offices in Kolkata, India and Alameda, CA, was founded in 1999 by EDA industry veteran Rob Dekker. Prior to founding Verific, Dekker was a software developer, manager and director at Exemplar Logic.
As a leading provider of SystemVerilog, VHDL, and UPF front-ends, Verific’s software
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[_relations:protected] => Array
(
)
[_previousValues:protected] => Array
(
)
[_options:protected] => Array
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[_deleted:protected] =>
[_readOnly:protected] =>
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(
)
[_whenSaveable:protected] => Array
(
)
[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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[_behaviors:protected] =>
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[_whenSaveable:protected] => Array
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[populated:protected] => 1
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Podcast EP196: A Look at the Upcoming IEDM Conference with the Publicity Chair and Vice Chair