Webinar: Advanced Packaging at Scale: Power, Performance, and Reliability in the Chiplet Era

How Will You Manage Power, Performance, and Reliability in the Chiplet Era?

Chiplet-based architectures, 2.5D integration, and system-in-package (SiP) designs are unlocking new levels of performance, scalability, and design flexibility. But moving beyond the monolithic SoC also introduces complex interactions among dies, interconnects, substrates, and packaging, creating new challenges in power delivery, thermal management, mechanical integrity, test, and long-term reliability.

At the same time, manufacturers must manage compound yield and rising production costs as the industry progresses from Known-Good-Die (KGD) to increasingly complex multi-die assemblies and Known-Good-Stack (KGS) methodologies. Traditional test and monitoring approaches are no longer enough to provide the visibility needed across die boundaries and throughout the product lifecycle.

Join our industry experts for a 40-minute webinar discussion exploring how design, test, manufacturing, and system teams are addressing these challenges through shift-left methodologies, evolving test standards, and deeper lifecycle observability and how the semiconductor ecosystem is working to deliver robust, power-efficient, and reliable multi-die systems at scale.

What you will learn:

• How emerging standards are enabling more effective test access across complex multi-die systems
• Why shift-left observability is essential for identifying power, thermal, and reliability risks earlier
• How production test strategies are evolving to address compound yield, KGD, and KGS requirements
• How package-level power delivery and thermal interactions can affect system performance and operating margins
• How lifecycle monitoring can improve in-field reliability, optimize performance, and help extend system lifetime

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