The next IP-SoC conference will be held in Grenoble, France, on December 6-7, 2016 after Shanghai in September and Bangalore, India, in April. This will be the 20[SUP]th[/SUP] edition of this unique IP centric event, as well as the celebration of Design And Reuse 20[SUP]th[/SUP] anniversary. Creating in 1997 a company fully dedicated… Read More
Tag: synopsys
Circuit Simulation Videos Show How To
One of the things that I miss most about attending trade shows like DAC in the old days was that you actually got to see EDA tools being demonstrated live in the exhibit area. You could see what the GUI looked like, how the dialogs worked, and learn what kind of control you could have during analysis. Most of what you see today at DAC in the… Read More
Drift is a Bad Thing for SPICE Circuit Simulators
My first job out of college was with Intel, located in Aloha, Oregon and I did circuit simulations using a proprietary SPICE circuit simulator called ASPEC that was maintained in-house. While doing some circuit simulations one day I noticed that an internal node in one of my circuits was gradually getting higher and higher, even… Read More
Synopsys Hosting Formal Methods in CAD Conference Next Week
FMCAD (Formal Methods in Computer Aided Design) is a technical conference with a 20-year pedigree. This is a conference for serious formal methods teams. Key notes are from Berkeley and UCLA, committee members are all formal heavyweights and best I can tell, there is no exhibitors area.… Read More
Getting out of DIY Mode for Virtual Prototypes
Virtual prototyping has, inexplicably, been largely a DIY thing so far. Tools and models have come from different sources with different approaches, and it has been up to the software development team to do the integration step and cobble together a toolchain and methodology that fits with their development effort.
That integration… Read More
Power-Aware Debug to Find Low-Power Simulation Bugs
When I worked at Intel designing custom chips my management would often ask me, “Will first silicon work?” My typical response was, “Yes, but only for the functions that we could afford to simulate before tape-out.” This snarky response would always cause a look of alarm, quickly followed by a second … Read More
Did My FPGA Just Fail?
Designing DRAMs at Intel back in the 1970s I first learned about Soft Errors and the curious effect of higher failure rates of DRAM chips in Denver, Colorado with a higher altitude than Aloha, OR. With the rapid growth of FPGA-based designs in 2016, we are still asking the same questions about the reliability of our chips used for safety-critical… Read More
Catching low-power simulation bugs earlier and faster
I’ve owned and used many generations of cell phones, starting back in the 1980’s with the Motorola DynaTAC phone and the biggest usability factor has always been the battery life, just how many hours of standby time will this phone provide and how many minutes of actual talk time before the battery needs to be recharged… Read More
MIPI DevCon 2016: Opened to non-MIPI Members!
The MIPI Alliance was founded in 2003 by large IDM to standardize chip-to-chip interfaces in the wireless phone (mobile) segment. The various MIPI specifications (CSI, DSI, DigRF and many more) have been adopted by the application processor chip makers (usually large IDM or fabless, like Intel or Qualcomm initially and many … Read More
10nm Will Be an Epic Process Node!
In the history of the fabless semiconductor industry the foundries have always been a process node or two behind the leading semiconductor manufacturers. Starting in Q1 2017, for the first time in fabless semiconductor history, the foundries will have a process node advantage. This is horrible news for some but great news for … Read More